€•Ä›      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ%/translations/zh_CN/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/zh_TW/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/it_IT/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/ja_JP/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/ko_KR/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/pt_BR/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/sp_SP/arch/riscv/vector”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³Œ?/var/lib/git/docbuild/linux/Documentation/arch/riscv/vector.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ)Vector Extension Support for RISC-V Linux”h]”hŒ)Vector Extension Support for RISC-V Linux”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hŒ‡This document briefly outlines the interface provided to userspace by Linux in
order to support the use of the RISC-V Vector Extension.”h]”hŒ‡This document briefly outlines the interface provided to userspace by Linux in
order to support the use of the RISC-V Vector Extension.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒ1.  prctl() Interface”h]”hŒ1.  prctl() Interface”…””}”(hhðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhíh²hh³hÇh´KubhÞ)”}”(hXÈ  Two new prctl() calls are added to allow programs to manage the enablement
status for the use of Vector in userspace. The intended usage guideline for
these interfaces is to give init systems a way to modify the availability of V
for processes running under its domain. Calling these interfaces is not
recommended in libraries routines because libraries should not override policies
configured from the parent process. Also, users must note that these interfaces
are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
to use in a portable code. To get the availability of V in an ELF program,
please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
auxiliary vector.”h]”(hXv  Two new prctl() calls are added to allow programs to manage the enablement
status for the use of Vector in userspace. The intended usage guideline for
these interfaces is to give init systems a way to modify the availability of V
for processes running under its domain. Calling these interfaces is not
recommended in libraries routines because libraries should not override policies
configured from the parent process. Also, users must note that these interfaces
are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
to use in a portable code. To get the availability of V in an ELF program,
please read ”…””}”(hhþh²hh³Nh´Nubh)”}”(hŒ:c:macro:`COMPAT_HWCAP_ISA_V`”h]”hŒliteral”“”)”}”(hj  h]”hŒCOMPAT_HWCAP_ISA_V”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”(Œxref”Œc”Œc-macro”eh"]”h$]”h&]”uh1j
  hj  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”Œarch/riscv/vector”Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰Œ	reftarget”ŒCOMPAT_HWCAP_ISA_V”uh1hh³hÇh´KhhþubhŒ bit of ”…””}”(hhþh²hh³Nh´Nubh)”}”(hŒ:c:macro:`ELF_HWCAP`”h]”j  )”}”(hj1  h]”hŒ	ELF_HWCAP”…””}”(hj3  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hj/  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  Œ	ELF_HWCAP”uh1hh³hÇh´KhhþubhŒ in the
auxiliary vector.”…””}”(hhþh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhíh²hubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX€  prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)

  Sets the Vector enablement status of the calling thread, where the control
  argument consists of two 2-bit enablement statuses and a bit for inheritance
  mode. Other threads of the calling process are unaffected.

  Enablement status is a tri-state value each occupying 2-bit of space in
  the control argument:

  * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
    enablement status on execve(). The system-wide default setting can be
    controlled via sysctl interface (see sysctl section below).

  * :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
    thread.

  * :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
    instructions under such condition will trap and casuse the termination of the thread.

  arg: The control argument is a 5-bit value consisting of 3 parts, and
  accessed by 3 masks respectively.

  The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
  PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT
  represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
  enablement status of current thread, and the setting at bit[3:2] takes place
  at next execve(). bit[4] defines the inheritance mode of the setting in
  bit[3:2].

      * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
        Vector enablement status for the calling thread. The calling thread is
        not able to turn off Vector once it has been enabled. The prctl() call
        fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
        but the current enablement status is not off. Setting
        PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
        the original enablement status.

      * :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
        Vector enablement setting for the calling thread at the next execve()
        system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
        then the enablement status will be decided by the system-wide
        enablement status when execve() happen.

      * :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
        mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
        is set then the following execve() will not clear the setting in both
        PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
        This setting persists across changes in the system-wide default value.

  Return value:
      * 0 on success;
      * EINVAL: Vector not supported, invalid enablement status for current or
        next mask;
      * EPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
        was enabled for the calling thread.

  On success:
      * A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
        immediately. The enablement status specified in
        PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
        all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
        set.
      * Every successful call overwrites a previous setting for the calling
        thread.
”h]”(hÞ)”}”(hŒ0prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)”h]”hŒ0prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg)”…””}”(hjc  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj_  ubhŒblock_quote”“”)”}”(hXè  Sets the Vector enablement status of the calling thread, where the control
argument consists of two 2-bit enablement statuses and a bit for inheritance
mode. Other threads of the calling process are unaffected.

Enablement status is a tri-state value each occupying 2-bit of space in
the control argument:

* :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
  enablement status on execve(). The system-wide default setting can be
  controlled via sysctl interface (see sysctl section below).

* :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
  thread.

* :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
  instructions under such condition will trap and casuse the termination of the thread.

arg: The control argument is a 5-bit value consisting of 3 parts, and
accessed by 3 masks respectively.

The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT
represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
enablement status of current thread, and the setting at bit[3:2] takes place
at next execve(). bit[4] defines the inheritance mode of the setting in
bit[3:2].

    * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
      Vector enablement status for the calling thread. The calling thread is
      not able to turn off Vector once it has been enabled. The prctl() call
      fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
      but the current enablement status is not off. Setting
      PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
      the original enablement status.

    * :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
      Vector enablement setting for the calling thread at the next execve()
      system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
      then the enablement status will be decided by the system-wide
      enablement status when execve() happen.

    * :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
      mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
      is set then the following execve() will not clear the setting in both
      PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
      This setting persists across changes in the system-wide default value.

Return value:
    * 0 on success;
    * EINVAL: Vector not supported, invalid enablement status for current or
      next mask;
    * EPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
      was enabled for the calling thread.

On success:
    * A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
      immediately. The enablement status specified in
      PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
      all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
      set.
    * Every successful call overwrites a previous setting for the calling
      thread.
”h]”(hÞ)”}”(hŒÒSets the Vector enablement status of the calling thread, where the control
argument consists of two 2-bit enablement statuses and a bit for inheritance
mode. Other threads of the calling process are unaffected.”h]”hŒÒSets the Vector enablement status of the calling thread, where the control
argument consists of two 2-bit enablement statuses and a bit for inheritance
mode. Other threads of the calling process are unaffected.”…””}”(hjw  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjs  ubhÞ)”}”(hŒ]Enablement status is a tri-state value each occupying 2-bit of space in
the control argument:”h]”hŒ]Enablement status is a tri-state value each occupying 2-bit of space in
the control argument:”…””}”(hj…  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjs  ubjY  )”}”(hhh]”(j^  )”}”(hŒÉ:c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
enablement status on execve(). The system-wide default setting can be
controlled via sysctl interface (see sysctl section below).
”h]”hÞ)”}”(hŒÈ:c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
enablement status on execve(). The system-wide default setting can be
controlled via sysctl interface (see sysctl section below).”h]”(h)”}”(hŒ):c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`”h]”j  )”}”(hj   h]”hŒPR_RISCV_V_VSTATE_CTRL_DEFAULT”…””}”(hj¢  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hjž  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  ŒPR_RISCV_V_VSTATE_CTRL_DEFAULT”uh1hh³hÇh´K!hjš  ubhŒŸ: Use the system-wide default
enablement status on execve(). The system-wide default setting can be
controlled via sysctl interface (see sysctl section below).”…””}”(hjš  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K!hj–  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj“  ubj^  )”}”(hŒM:c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
thread.
”h]”hÞ)”}”(hŒL:c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
thread.”h]”(h)”}”(hŒ$:c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`”h]”j  )”}”(hj×  h]”hŒPR_RISCV_V_VSTATE_CTRL_ON”…””}”(hjÙ  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hjÕ  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  ŒPR_RISCV_V_VSTATE_CTRL_ON”uh1hh³hÇh´K%hjÑ  ubhŒ(: Allow Vector to be run for the
thread.”…””}”(hjÑ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K%hjÍ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj“  ubj^  )”}”(hŒŸ:c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
instructions under such condition will trap and casuse the termination of the thread.
”h]”hÞ)”}”(hŒž:c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
instructions under such condition will trap and casuse the termination of the thread.”h]”(h)”}”(hŒ%:c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`”h]”j  )”}”(hj  h]”hŒPR_RISCV_V_VSTATE_CTRL_OFF”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hj  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  ŒPR_RISCV_V_VSTATE_CTRL_OFF”uh1hh³hÇh´K(hj  ubhŒy: Disallow Vector. Executing Vector
instructions under such condition will trap and casuse the termination of the thread.”…””}”(hj  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K(hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj“  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1jX  h³hÇh´K!hjs  ubhÞ)”}”(hŒgarg: The control argument is a 5-bit value consisting of 3 parts, and
accessed by 3 masks respectively.”h]”hŒgarg: The control argument is a 5-bit value consisting of 3 parts, and
accessed by 3 masks respectively.”…””}”(hjC  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K+hjs  ubhÞ)”}”(hXV  The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT
represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
enablement status of current thread, and the setting at bit[3:2] takes place
at next execve(). bit[4] defines the inheritance mode of the setting in
bit[3:2].”h]”hXV  The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT
represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
enablement status of current thread, and the setting at bit[3:2] takes place
at next execve(). bit[4] defines the inheritance mode of the setting in
bit[3:2].”…””}”(hjQ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K.hjs  ubjr  )”}”(hXm  * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
  Vector enablement status for the calling thread. The calling thread is
  not able to turn off Vector once it has been enabled. The prctl() call
  fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
  but the current enablement status is not off. Setting
  PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
  the original enablement status.

* :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
  Vector enablement setting for the calling thread at the next execve()
  system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
  then the enablement status will be decided by the system-wide
  enablement status when execve() happen.

* :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
  mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
  is set then the following execve() will not clear the setting in both
  PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
  This setting persists across changes in the system-wide default value.
”h]”jY  )”}”(hhh]”(j^  )”}”(hX·  :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
Vector enablement status for the calling thread. The calling thread is
not able to turn off Vector once it has been enabled. The prctl() call
fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
but the current enablement status is not off. Setting
PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
the original enablement status.
”h]”hÞ)”}”(hX¶  :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
Vector enablement status for the calling thread. The calling thread is
not able to turn off Vector once it has been enabled. The prctl() call
fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
but the current enablement status is not off. Setting
PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
the original enablement status.”h]”(h)”}”(hŒ*:c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`”h]”j  )”}”(hjp  h]”hŒPR_RISCV_V_VSTATE_CTRL_CUR_MASK”…””}”(hjr  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hjn  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  ŒPR_RISCV_V_VSTATE_CTRL_CUR_MASK”uh1hh³hÇh´K5hjj  ubhXŒ  : bit[1:0]: Account for the
Vector enablement status for the calling thread. The calling thread is
not able to turn off Vector once it has been enabled. The prctl() call
fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF
but the current enablement status is not off. Setting
PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back
the original enablement status.”…””}”(hjj  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K5hjf  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjc  ubj^  )”}”(hX8  :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
Vector enablement setting for the calling thread at the next execve()
system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
then the enablement status will be decided by the system-wide
enablement status when execve() happen.
”h]”hÞ)”}”(hX7  :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
Vector enablement setting for the calling thread at the next execve()
system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
then the enablement status will be decided by the system-wide
enablement status when execve() happen.”h]”(h)”}”(hŒ+:c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`”h]”j  )”}”(hj§  h]”hŒ PR_RISCV_V_VSTATE_CTRL_NEXT_MASK”…””}”(hj©  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hj¥  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  Œ PR_RISCV_V_VSTATE_CTRL_NEXT_MASK”uh1hh³hÇh´K=hj¡  ubhX  : bit[3:2]: Account for the
Vector enablement setting for the calling thread at the next execve()
system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask,
then the enablement status will be decided by the system-wide
enablement status when execve() happen.”…””}”(hj¡  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K=hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjc  ubj^  )”}”(hXZ  :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
is set then the following execve() will not clear the setting in both
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
This setting persists across changes in the system-wide default value.
”h]”hÞ)”}”(hXY  :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
is set then the following execve() will not clear the setting in both
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
This setting persists across changes in the system-wide default value.”h]”(h)”}”(hŒ):c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`”h]”j  )”}”(hjÞ  h]”hŒPR_RISCV_V_VSTATE_CTRL_INHERIT”…””}”(hjà  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hjÜ  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  ŒPR_RISCV_V_VSTATE_CTRL_INHERIT”uh1hh³hÇh´KChjØ  ubhX0  : bit[4]: the inheritance
mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
is set then the following execve() will not clear the setting in both
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT.
This setting persists across changes in the system-wide default value.”…””}”(hjØ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KChjÔ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjc  ubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´K5hj_  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jq  h³hÇh´K5hjs  ubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒãReturn value:
* 0 on success;
* EINVAL: Vector not supported, invalid enablement status for current or
  next mask;
* EPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
  was enabled for the calling thread.
”h]”(hŒterm”“”)”}”(hŒReturn value:”h]”hŒReturn value:”…””}”(hj$  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j"  h³hÇh´KNhj  ubhŒ
definition”“”)”}”(hhh]”jY  )”}”(hhh]”(j^  )”}”(hŒ0 on success;”h]”hÞ)”}”(hj<  h]”hŒ0 on success;”…””}”(hj>  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KJhj:  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj7  ubj^  )”}”(hŒQEINVAL: Vector not supported, invalid enablement status for current or
next mask;”h]”hÞ)”}”(hŒQEINVAL: Vector not supported, invalid enablement status for current or
next mask;”h]”hŒQEINVAL: Vector not supported, invalid enablement status for current or
next mask;”…””}”(hjU  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KKhjQ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj7  ubj^  )”}”(hŒkEPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
was enabled for the calling thread.
”h]”hÞ)”}”(hŒjEPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
was enabled for the calling thread.”h]”hŒjEPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector
was enabled for the calling thread.”…””}”(hjm  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KMhji  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj7  ubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´KJhj4  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j2  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  h³hÇh´KNhj  ubj  )”}”(hXh  On success:
* A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
  immediately. The enablement status specified in
  PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
  all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
  set.
* Every successful call overwrites a previous setting for the calling
  thread.
”h]”(j#  )”}”(hŒOn success:”h]”hŒOn success:”…””}”(hj—  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j"  h³hÇh´KWhj“  ubj3  )”}”(hhh]”jY  )”}”(hhh]”(j^  )”}”(hX  A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
immediately. The enablement status specified in
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
set.”h]”hÞ)”}”(hX  A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
immediately. The enablement status specified in
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
set.”h]”hX  A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
immediately. The enablement status specified in
PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or
all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
set.”…””}”(hj¯  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KQhj«  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj¨  ubj^  )”}”(hŒLEvery successful call overwrites a previous setting for the calling
thread.
”h]”hÞ)”}”(hŒKEvery successful call overwrites a previous setting for the calling
thread.”h]”hŒKEvery successful call overwrites a previous setting for the calling
thread.”…””}”(hjÇ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KVhjÃ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj¨  ubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´KQhj¥  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j2  hj“  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  h³hÇh´KWhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjs  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jq  h³hÇh´Khj_  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjZ  h²hh³hÇh´Nubj^  )”}”(hX½  prctl(PR_RISCV_V_GET_CONTROL)

  Gets the same Vector enablement status for the calling thread. Setting for
  next execve() call and the inheritance bit are all OR-ed together.

  Note that ELF programs are able to get the availability of V for itself by
  reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
  auxiliary vector.

  Return value:
      * a nonnegative value on success;
      * EINVAL: Vector not supported.
”h]”(hÞ)”}”(hŒprctl(PR_RISCV_V_GET_CONTROL)”h]”hŒprctl(PR_RISCV_V_GET_CONTROL)”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KYhjÿ  ubjr  )”}”(hXŽ  Gets the same Vector enablement status for the calling thread. Setting for
next execve() call and the inheritance bit are all OR-ed together.

Note that ELF programs are able to get the availability of V for itself by
reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
auxiliary vector.

Return value:
    * a nonnegative value on success;
    * EINVAL: Vector not supported.
”h]”(hÞ)”}”(hŒGets the same Vector enablement status for the calling thread. Setting for
next execve() call and the inheritance bit are all OR-ed together.”h]”hŒGets the same Vector enablement status for the calling thread. Setting for
next execve() call and the inheritance bit are all OR-ed together.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K[hj  ubhÞ)”}”(hŒ¥Note that ELF programs are able to get the availability of V for itself by
reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
auxiliary vector.”h]”(hŒSNote that ELF programs are able to get the availability of V for itself by
reading ”…””}”(hj#  h²hh³Nh´Nubh)”}”(hŒ:c:macro:`COMPAT_HWCAP_ISA_V`”h]”j  )”}”(hj-  h]”hŒCOMPAT_HWCAP_ISA_V”…””}”(hj/  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hj+  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  ŒCOMPAT_HWCAP_ISA_V”uh1hh³hÇh´K^hj#  ubhŒ bit of ”…””}”(hj#  h²hh³Nh´Nubh)”}”(hŒ:c:macro:`ELF_HWCAP`”h]”j  )”}”(hjP  h]”hŒ	ELF_HWCAP”…””}”(hjR  h²hh³Nh´Nubah}”(h]”h ]”(j  j  Œc-macro”eh"]”h$]”h&]”uh1j
  hjN  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”j#  Œ	refdomain”j  Œreftype”Œmacro”Œrefexplicit”‰Œrefwarn”‰j)  Œ	ELF_HWCAP”uh1hh³hÇh´K^hj#  ubhŒ in the
auxiliary vector.”…””}”(hj#  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K^hj  ubj  )”}”(hhh]”j  )”}”(hŒPReturn value:
* a nonnegative value on success;
* EINVAL: Vector not supported.
”h]”(j#  )”}”(hŒReturn value:”h]”hŒReturn value:”…””}”(hj~  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j"  h³hÇh´Kdhjz  ubj3  )”}”(hhh]”jY  )”}”(hhh]”(j^  )”}”(hŒa nonnegative value on success;”h]”hÞ)”}”(hj”  h]”hŒa nonnegative value on success;”…””}”(hj–  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kchj’  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj  ubj^  )”}”(hŒEINVAL: Vector not supported.
”h]”hÞ)”}”(hŒEINVAL: Vector not supported.”h]”hŒEINVAL: Vector not supported.”…””}”(hj­  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kdhj©  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´KchjŒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j2  hjz  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  h³hÇh´Kdhjw  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jq  h³hÇh´K[hjÿ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjZ  h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´Khhíh²hubeh}”(h]”Œprctl-interface”ah ]”h"]”Œ1. prctl() interface”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ)2.  System runtime configuration (sysctl)”h]”hŒ)2.  System runtime configuration (sysctl)”…””}”(hjö  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjó  h²hh³hÇh´KgubhÞ)”}”(hŒõTo mitigate the ABI impact of expansion of the signal stack, a
policy mechanism is provided to the administrators, distro maintainers, and
developers to control the default Vector enablement status for userspace
processes in form of sysctl knob:”h]”hŒõTo mitigate the ABI impact of expansion of the signal stack, a
policy mechanism is provided to the administrators, distro maintainers, and
developers to control the default Vector enablement status for userspace
processes in form of sysctl knob:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kihjó  h²hubjY  )”}”(hhh]”j^  )”}”(hXÌ  /proc/sys/abi/riscv_v_default_allow

  Writing the text representation of 0 or 1 to this file sets the default
  system enablement status for new starting userspace programs. Valid values
  are:

  * 0: Do not allow Vector code to be executed as the default for new processes.
  * 1: Allow Vector code to be executed as the default for new processes.

  Reading this file returns the current system default enablement status.

  At every execve() call, a new enablement status of the new process is set to
  the system default, unless:

    * PR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
      setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
      PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,

    * The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
      PR_RISCV_V_VSTATE_CTRL_DEFAULT.

  Modifying the system default enablement status does not affect the enablement
  status of any existing process of thread that do not make an execve() call.
”h]”(hÞ)”}”(hŒ#/proc/sys/abi/riscv_v_default_allow”h]”hŒ#/proc/sys/abi/riscv_v_default_allow”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Knhj  ubjr  )”}”(hX‰  Writing the text representation of 0 or 1 to this file sets the default
system enablement status for new starting userspace programs. Valid values
are:

* 0: Do not allow Vector code to be executed as the default for new processes.
* 1: Allow Vector code to be executed as the default for new processes.

Reading this file returns the current system default enablement status.

At every execve() call, a new enablement status of the new process is set to
the system default, unless:

  * PR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
    setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
    PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,

  * The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
    PR_RISCV_V_VSTATE_CTRL_DEFAULT.

Modifying the system default enablement status does not affect the enablement
status of any existing process of thread that do not make an execve() call.
”h]”(hÞ)”}”(hŒ—Writing the text representation of 0 or 1 to this file sets the default
system enablement status for new starting userspace programs. Valid values
are:”h]”hŒ—Writing the text representation of 0 or 1 to this file sets the default
system enablement status for new starting userspace programs. Valid values
are:”…””}”(hj+  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kphj'  ubjY  )”}”(hhh]”(j^  )”}”(hŒL0: Do not allow Vector code to be executed as the default for new processes.”h]”hÞ)”}”(hj>  h]”hŒL0: Do not allow Vector code to be executed as the default for new processes.”…””}”(hj@  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kthj<  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj9  ubj^  )”}”(hŒF1: Allow Vector code to be executed as the default for new processes.
”h]”hÞ)”}”(hŒE1: Allow Vector code to be executed as the default for new processes.”h]”hŒE1: Allow Vector code to be executed as the default for new processes.”…””}”(hjW  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KuhjS  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj9  ubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´Kthj'  ubhÞ)”}”(hŒGReading this file returns the current system default enablement status.”h]”hŒGReading this file returns the current system default enablement status.”…””}”(hjq  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kwhj'  ubhÞ)”}”(hŒhAt every execve() call, a new enablement status of the new process is set to
the system default, unless:”h]”hŒhAt every execve() call, a new enablement status of the new process is set to
the system default, unless:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kyhj'  ubjr  )”}”(hX   * PR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
  setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
  PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,

* The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
  PR_RISCV_V_VSTATE_CTRL_DEFAULT.
”h]”jY  )”}”(hhh]”(j^  )”}”(hŒžPR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,
”h]”hÞ)”}”(hŒPR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,”h]”hŒPR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the
setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or,”…””}”(hj˜  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K|hj”  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj‘  ubj^  )”}”(hŒWThe setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
PR_RISCV_V_VSTATE_CTRL_DEFAULT.
”h]”hÞ)”}”(hŒVThe setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
PR_RISCV_V_VSTATE_CTRL_DEFAULT.”h]”hŒVThe setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
PR_RISCV_V_VSTATE_CTRL_DEFAULT.”…””}”(hj°  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K€hj¬  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj‘  ubeh}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´K|hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jq  h³hÇh´K|hj'  ubhÞ)”}”(hŒ™Modifying the system default enablement status does not affect the enablement
status of any existing process of thread that do not make an execve() call.”h]”hŒ™Modifying the system default enablement status does not affect the enablement
status of any existing process of thread that do not make an execve() call.”…””}”(hjÐ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kƒhj'  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jq  h³hÇh´Kphj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”jA  jB  uh1jX  h³hÇh´Knhjó  h²hubeh}”(h]”Œ#system-runtime-configuration-sysctl”ah ]”h"]”Œ(2. system runtime configuration (sysctl)”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KgubhÉ)”}”(hhh]”(hÎ)”}”(hŒ-3.  Vector Register State Across System Calls”h]”hŒ-3.  Vector Register State Across System Calls”…””}”(hjû  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjø  h²hh³hÇh´K‡ubhÞ)”}”(hŒcAs indicated by version 1.0 of the V extension [1], vector registers are
clobbered by system calls.”h]”hŒcAs indicated by version 1.0 of the V extension [1], vector registers are
clobbered by system calls.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‰hjø  h²hubhÞ)”}”(hŒL1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc”h]”(hŒ1: ”…””}”(hj  h²hh³Nh´NubhŒ	reference”“”)”}”(hŒIhttps://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc”h]”hŒIhttps://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc”…””}”(hj!  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j#  uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KŒhjø  h²hubeh}”(h]”Œ)vector-register-state-across-system-calls”ah ]”h"]”Œ,3. vector register state across system calls”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K‡ubeh}”(h]”Œ)vector-extension-support-for-risc-v-linux”ah ]”h"]”Œ)vector extension support for risc-v linux”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”ji  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jC  j@  jð  jí  jõ  jò  j;  j8  uŒ	nametypes”}”(jC  ‰jð  ‰jõ  ‰j;  ‰uh}”(j@  hÊjí  híjò  jó  j8  jø  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.