sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/arch/riscv/hwprobemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/arch/riscv/hwprobe.rsthKubhsection)}(hhh](htitle)}(h!RISC-V Hardware Probing Interfaceh]h!RISC-V Hardware Probing Interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hmThe RISC-V hardware probing interface is based around a single syscall, which is defined in ::h]hlThe RISC-V hardware probing interface is based around a single syscall, which is defined in :}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh literal_block)}(hstruct riscv_hwprobe { __s64 key; __u64 value; }; long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, size_t cpusetsize, cpu_set_t *cpus, unsigned int flags);h]hstruct riscv_hwprobe { __s64 key; __u64 value; }; long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, size_t cpusetsize, cpu_set_t *cpus, unsigned int flags);}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhK hhhhubh)}(hXAThe arguments are split into three groups: an array of key-value pairs, a CPU set, and some flags. The key-value pairs are supplied with a count. Userspace must prepopulate the key field for each element, and the kernel will fill in the value if the key is recognized. If a key is unknown to the kernel, its key field will be cleared to -1, and its value set to 0. The CPU set is defined by CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor, arch, impl), the returned value will only be valid if all CPUs in the given set have the same value. Otherwise -1 will be returned. For boolean-like keys, the value returned will be a logical AND of the values for the specified CPUs. Usermode can supply NULL for ``cpus`` and 0 for ``cpusetsize`` as a shortcut for all online CPUs. The currently supported flags are:h](hXThe arguments are split into three groups: an array of key-value pairs, a CPU set, and some flags. The key-value pairs are supplied with a count. Userspace must prepopulate the key field for each element, and the kernel will fill in the value if the key is recognized. If a key is unknown to the kernel, its key field will be cleared to -1, and its value set to 0. The CPU set is defined by CPU_SET(3) with size }(hhhhhNhNubhliteral)}(h``cpusetsize``h]h cpusetsize}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubhX0 bytes. For value-like keys (eg. vendor, arch, impl), the returned value will only be valid if all CPUs in the given set have the same value. Otherwise -1 will be returned. For boolean-like keys, the value returned will be a logical AND of the values for the specified CPUs. Usermode can supply NULL for }(hhhhhNhNubh)}(h``cpus``h]hcpus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh and 0 for }(hhhhhNhNubh)}(h``cpusetsize``h]h cpusetsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubhF as a shortcut for all online CPUs. The currently supported flags are:}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh]h list_item)}(hX2:c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior of sys_riscv_hwprobe(). Instead of populating the values of keys for a given set of CPUs, the values of each key are given and the set of CPUs is reduced by sys_riscv_hwprobe() to only those which match each of the key-value pairs. How matching is done depends on the key type. For value-like keys, matching means to be the exact same as the value. For boolean-like keys, matching means the result of a logical AND of the pair's value with the CPU's value is exactly the same as the pair's value. Additionally, when ``cpus`` is an empty set, then it is initialized to all online CPUs which fit within it, i.e. the CPU set returned is the reduction of all the online CPUs which can be represented with a CPU set of size ``cpusetsize``. h]h)}(hX1:c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior of sys_riscv_hwprobe(). Instead of populating the values of keys for a given set of CPUs, the values of each key are given and the set of CPUs is reduced by sys_riscv_hwprobe() to only those which match each of the key-value pairs. How matching is done depends on the key type. For value-like keys, matching means to be the exact same as the value. For boolean-like keys, matching means the result of a logical AND of the pair's value with the CPU's value is exactly the same as the pair's value. Additionally, when ``cpus`` is an empty set, then it is initialized to all online CPUs which fit within it, i.e. the CPU set returned is the reduction of all the online CPUs which can be represented with a CPU set of size ``cpusetsize``.h](h)}(h#:c:macro:`RISCV_HWPROBE_WHICH_CPUS`h]h)}(hj@h]hRISCV_HWPROBE_WHICH_CPUS}(hjBhhhNhNubah}(h]h ](xrefcc-macroeh"]h$]h&]uh1hhj>ubah}(h]h ]h"]h$]h&]refdocarch/riscv/hwprobe refdomainjMreftypemacro refexplicitrefwarn reftargetRISCV_HWPROBE_WHICH_CPUSuh1hhhhKhj:ubhX:: This flag basically reverses the behavior of sys_riscv_hwprobe(). Instead of populating the values of keys for a given set of CPUs, the values of each key are given and the set of CPUs is reduced by sys_riscv_hwprobe() to only those which match each of the key-value pairs. How matching is done depends on the key type. For value-like keys, matching means to be the exact same as the value. For boolean-like keys, matching means the result of a logical AND of the pair’s value with the CPU’s value is exactly the same as the pair’s value. Additionally, when }(hj:hhhNhNubh)}(h``cpus``h]hcpus}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh is an empty set, then it is initialized to all online CPUs which fit within it, i.e. the CPU set returned is the reduction of all the online CPUs which can be represented with a CPU set of size }(hj:hhhNhNubh)}(h``cpusetsize``h]h cpusetsize}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:ubh.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1j4hj1hhhhhNubah}(h]h ]h"]h$]h&]bullet*uh1j/hhhKhhhhubh)}(hGAll other flags are reserved for future compatibility and must be zero.h]hGAll other flags are reserved for future compatibility and must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hhhhubh)}(hGOn success 0 is returned, on failure a negative error code is returned.h]hGOn success 0 is returned, on failure a negative error code is returned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hhhhubh)}(hThe following keys are defined:h]hThe following keys are defined:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hhhhubj0)}(hhh](j5)}(h:c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``, as defined by the RISC-V privileged architecture specification. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``, as defined by the RISC-V privileged architecture specification.h](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_MVENDORID`h]h)}(hjh]hRISCV_HWPROBE_KEY_MVENDORID}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_MVENDORIDuh1hhhhK0hjubh: Contains the value of }(hjhhhNhNubh)}(h ``mvendorid``h]h mvendorid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhA, as defined by the RISC-V privileged architecture specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j4hjhhhhhNubj5)}(h:c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as defined by the RISC-V privileged architecture specification. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as defined by the RISC-V privileged architecture specification.h](h)}(h$:c:macro:`RISCV_HWPROBE_KEY_MARCHID`h]h)}(hjh]hRISCV_HWPROBE_KEY_MARCHID}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_MARCHIDuh1hhhhK3hjubh: Contains the value of }(hjhhhNhNubh)}(h ``marchid``h]hmarchid}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhA, as defined by the RISC-V privileged architecture specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1j4hjhhhhhNubj5)}(h:c:macro:`RISCV_HWPROBE_KEY_MIMPID`: Contains the value of ``mimpid``, as defined by the RISC-V privileged architecture specification. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_MIMPID`: Contains the value of ``mimpid``, as defined by the RISC-V privileged architecture specification.h](h)}(h#:c:macro:`RISCV_HWPROBE_KEY_MIMPID`h]h)}(hjfh]hRISCV_HWPROBE_KEY_MIMPID}(hjhhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_MIMPIDuh1hhhhK6hj`ubh: Contains the value of }(hj`hhhNhNubh)}(h ``mimpid``h]hmimpid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`ubhA, as defined by the RISC-V privileged architecture specification.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK6hj\ubah}(h]h ]h"]h$]h&]uh1j4hjhhhhhNubj5)}(hX:c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base user-visible behavior that this kernel supports. The following base user ABIs are defined: * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken): * The ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base user-visible behavior that this kernel supports. The following base user ABIs are defined:h](h)}(h*:c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`h]h)}(hjh]hRISCV_HWPROBE_KEY_BASE_BEHAVIOR}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_BASE_BEHAVIORuh1hhhhK9hjubh{: A bitmask containing the base user-visible behavior that this kernel supports. The following base user ABIs are defined:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK9hjubj0)}(hhh]j5)}(hX:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken): * The ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). h](h)}(hX%:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken):h](h)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]h)}(hjh]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhK=hjubh: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK=hjubj0)}(hhh]j5)}(hThe ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). h]h)}(hThe ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO).h](hThe }(hjhhhNhNubh)}(h ``fence.i``h]hfence.i}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKBhj ubah}(h]h ]h"]h$]h&]uh1j4hj ubah}(h]h ]h"]h$]h&]jjuh1j/hhhKBhjubeh}(h]h ]h"]h$]h&]uh1j4hjubah}(h]h ]h"]h$]h&]jjuh1j/hhhK=hjubeh}(h]h ]h"]h$]h&]uh1j4hjhhhNhNubj5)}(hX4&:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as defined by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0"). * :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`h]h)}(hjYh]hRISCV_HWPROBE_KEY_IMA_EXT_0}(hj[hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjWubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_IMA_EXT_0uh1hhhhKFhjSubhC: A bitmask containing the extensions that are compatible with the }(hjShhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]h)}(hj|h]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hj~hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjzubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhKFhjSubh: base system behavior.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKFhjOubj0)}(hhh](j5)}(h:c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as defined by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. h]h)}(h:c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as defined by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.h](h)}(h:c:macro:`RISCV_HWPROBE_IMA_FD`h]h)}(hjh]hRISCV_HWPROBE_IMA_FD}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_IMA_FDuh1hhhhKJhjubh: The F and D extensions are supported, as defined by commit cd20cee (“FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum”) of the RISC-V ISA manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKJhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(hr:c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. h]h)}(hq:c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual.h](h)}(h:c:macro:`RISCV_HWPROBE_IMA_C`h]h)}(hjh]hRISCV_HWPROBE_IMA_C}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_IMA_Cuh1hhhhKNhjubhS: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h~:c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h:c:macro:`RISCV_HWPROBE_IMA_V`h]h)}(hjh]hRISCV_HWPROBE_IMA_V}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_IMA_Vuh1hhhhKQhjubh`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]hdefinition_list)}(hhh]hdefinition_list_item)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h](hterm)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension ish](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBA`h]h)}(hjbh]hRISCV_HWPROBE_EXT_ZBA}(hjdhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj`ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBAuh1hhhhKVhj\ubh): The Zba address generation extension is}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKVhjVubh definition)}(hhh]h)}(hLsupported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.h]hLsupported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jThhhKVhjQubah}(h]h ]h"]h$]h&]uh1jOhjKubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h](j[)}(hL:c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as definedh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBB`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZBB}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBBuh1hhhhKYhjubh,: The Zbb extension is supported, as defined}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKYhjubj)}(hhh]h)}(h6in version 1.0 of the Bit-Manipulation ISA extensions.h]h6in version 1.0 of the Bit-Manipulation ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKYhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h](j[)}(hL:c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as definedh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBS`h]h)}(hj&h]hRISCV_HWPROBE_EXT_ZBS}(hj(hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj$ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBSuh1hhhhK\hj ubh,: The Zbs extension is supported, as defined}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhK\hjubj)}(hhh]h)}(h6in version 1.0 of the Bit-Manipulation ISA extensions.h]h6in version 1.0 of the Bit-Manipulation ISA extensions.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjMubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhK\hjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h](j[)}(hJ:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZICBOZ}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZICBOZuh1hhhhK_hjubh': The Zicboz extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhK_hj}ubj)}(hhh]h)}(hEratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.h]hIratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jThhhK_hjzubah}(h]h ]h"]h$]h&]uh1jOhjvubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h](j[)}(hK:c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as definedh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBC`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZBC}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBCuh1hhhhKbhjubh+ The Zbc extension is supported, as defined}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKbhjubj)}(hhh]h)}(h6in version 1.0 of the Bit-Manipulation ISA extensions.h]h6in version 1.0 of the Bit-Manipulation ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKbhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZBKB`h]h)}(hjIh]hRISCV_HWPROBE_EXT_ZBKB}(hjKhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjGubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBKBuh1hhhhKehjCubh$ The Zbkb extension is supported, as}(hjChhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKehj?ubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjpubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jThhhKehj<ubah}(h]h ]h"]h$]h&]uh1jOhj8ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZBKC`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZBKC}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBKCuh1hhhhKhhjubh$ The Zbkc extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhhjubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZBKX`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZBKX}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZBKXuh1hhhhKkhjubh$ The Zbkx extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKkhjubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKkhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKND`h]h)}(hjlh]hRISCV_HWPROBE_EXT_ZKND}(hjnhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZKNDuh1hhhhKnhjfubh$ The Zknd extension is supported, as}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKnhjbubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jThhhKnhj_ubah}(h]h ]h"]h$]h&]uh1jOhj[ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKNE`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZKNE}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZKNEuh1hhhhKqhjubh$ The Zkne extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKqhjubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKqhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKNH`h]h)}(hj.h]hRISCV_HWPROBE_EXT_ZKNH}(hj0hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZKNHuh1hhhhKthj(ubh$ The Zknh extension is supported, as}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKthj$ubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjUubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jThhhKthj!ubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hG:c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, ash](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZKSED`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZKSED}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZKSEDuh1hhhhKwhjubh% The Zksed extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKwhjubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKwhjubah}(h]h ]h"]h$]h&]uh1jOhj~ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKSH`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZKSH}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZKSHuh1hhhhKzhjubh$ The Zksh extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKzhjubj)}(hhh]h)}(h;defined in version 1.0 of the Scalar Crypto ISA extensions.h]h;defined in version 1.0 of the Scalar Crypto ISA extensions.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKzhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h](j[)}(hK:c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as definedh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZKT`h]h)}(hjQ h]hRISCV_HWPROBE_EXT_ZKT}(hjS hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjO ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZKTuh1hhhhK}hjK ubh+ The Zkt extension is supported, as defined}(hjK hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhK}hjG ubj)}(hhh]h)}(h3in version 1.0 of the Scalar Crypto ISA extensions.h]h3in version 1.0 of the Scalar Crypto ISA extensions.}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjx ubah}(h]h ]h"]h$]h&]uh1jhjG ubeh}(h]h ]h"]h$]h&]uh1jThhhK}hjD ubah}(h]h ]h"]h$]h&]uh1jOhj@ ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVBB`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVBB}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVBBuh1hhhhKhj ubh$: The Zvbb extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVBC`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVBC}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVBCuh1hhhhKhj ubh$: The Zvbc extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj: ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVKB`h]h)}(hjt h]hRISCV_HWPROBE_EXT_ZVKB}(hjv hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjr ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKBuh1hhhhKhjn ubh$: The Zvkb extension is supported as}(hjn hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhjg ubah}(h]h ]h"]h$]h&]uh1jOhjc ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVKG`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVKG}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKGuh1hhhhKhj ubh$: The Zvkg extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`h]h)}(hj6 h]hRISCV_HWPROBE_EXT_ZVKNED}(hj8 hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj4 ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKNEDuh1hhhhKhj0 ubh&: The Zvkned extension is supported as}(hj0 hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj, ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj] ubah}(h]h ]h"]h$]h&]uh1jhj, ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj) ubah}(h]h ]h"]h$]h&]uh1jOhj% ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVKNHA}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKNHAuh1hhhhKhj ubh&: The Zvknha extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVKNHB}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKNHBuh1hhhhKhj ubh&: The Zvknhb extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`h]h)}(hjY h]hRISCV_HWPROBE_EXT_ZVKSED}(hj[ hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjW ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKSEDuh1hhhhKhjS ubh&: The Zvksed extension is supported as}(hjS hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjO ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjO ubeh}(h]h ]h"]h$]h&]uh1jThhhKhjL ubah}(h]h ]h"]h$]h&]uh1jOhjH ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hG:c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported ash](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZVKSH`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVKSH}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKSHuh1hhhhKhj ubh%: The Zvksh extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVKT`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZVKT}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVKTuh1hhhhKhj ubh$: The Zvkt extension is supported as}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h]hGdefined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(hu:c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported as defined in the RISC-V ISA manual. h]jP)}(hhh]jU)}(hr:c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported as defined in the RISC-V ISA manual. h](j[)}(hL:c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supportedh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZFH`h]h)}(hj| h]hRISCV_HWPROBE_EXT_ZFH}(hj~ hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjz ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZFHuh1hhhhKhjv ubh,: The Zfh extension version 1.0 is supported}(hjv hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjr ubj)}(hhh]h)}(h$as defined in the RISC-V ISA manual.h]h$as defined in the RISC-V ISA manual.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjr ubeh}(h]h ]h"]h$]h&]uh1jThhhKhjo ubah}(h]h ]h"]h$]h&]uh1jOhjk ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h{:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual. h]jP)}(hhh]jU)}(hx:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual. h](j[)}(hH:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 ish](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`h]h)}(hj h]hRISCV_HWPROBE_EXT_ZFHMIN}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZFHMINuh1hhhhKhj ubh%: The Zfhmin extension version 1.0 is}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj ubj)}(hhh]h)}(h.supported as defined in the RISC-V ISA manual.h]h.supported as defined in the RISC-V ISA manual.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj ubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual. h]jP)}(hhh]jU)}(h~:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual. h](j[)}(hK:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0h](h)}(h&:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`h]h)}(hj>h]hRISCV_HWPROBE_EXT_ZIHINTNTL}(hj@hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZIHINTNTLuh1hhhhKhj8ubh%: The Zihintntl extension version 1.0}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj4ubj)}(hhh]h)}(h1is supported as defined in the RISC-V ISA manual.h]h1is supported as defined in the RISC-V ISA manual.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj1ubah}(h]h ]h"]h$]h&]uh1jOhj-ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVFH`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZVFH}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVFHuh1hhhhKhjubh$: The Zvfh extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hodefined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]").h]hsdefined in the RISC-V Vector manual starting from commit e2ccd0548d6c (“Remove draft warnings from Zvfh[min]”).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). h](j[)}(hK:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported ash](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZVFHMIN}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVFHMINuh1hhhhKhjubh': The Zvfhmin extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hodefined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]").h]hsdefined in the RISC-V Vector manual starting from commit e2ccd0548d6c (“Remove draft warnings from Zvfh[min]”).}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). h](j[)}(hC:c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported ash](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZFA`h]h)}(hjah]hRISCV_HWPROBE_EXT_ZFA}(hjchhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj_ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZFAuh1hhhhKhj[ubh#: The Zfa extension is supported as}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjWubj)}(hhh]h)}(hWdefined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified").h]h[defined in the RISC-V ISA manual starting from commit 056b6ff467c7 (“Zfa is ratified”).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jThhhKhjTubah}(h]h ]h"]h$]h&]uh1jOhjPubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZTSO`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZTSO}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZTSOuh1hhhhKhjubh$: The Ztso extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(h\defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.")h]h`defined in the RISC-V ISA manual starting from commit 5618fb5a216b (“Ztso is now ratified.”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). h](j[)}(hG:c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported ash](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZACAS`h]h)}(hj#h]hRISCV_HWPROBE_EXT_ZACAS}(hj%hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj!ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZACASuh1hhhhKhjubh%: The Zacas extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hzdefined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified").h]h~defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c (“update to ratified”).}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h{:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual. h]jP)}(hhh]jU)}(hx:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZICNTR}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZICNTRuh1hhhhKhj~ubh": The Zicntr extension version 2.0}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjzubj)}(hhh]h)}(h1is supported as defined in the RISC-V ISA manual.h]h1is supported as defined in the RISC-V ISA manual.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jThhhKhjwubah}(h]h ]h"]h$]h&]uh1jOhjsubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") h](j[)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICOND`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZICOND}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZICONDuh1hhhhKhjubh&: The Zicond extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hdefined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff")h]hdefined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 (“Add changes requested by Ved during signoff”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). h](j[)}(hF:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension ish](h)}(h(:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`h]h)}(hjFh]hRISCV_HWPROBE_EXT_ZIHINTPAUSE}(hjHhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjDubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZIHINTPAUSEuh1hhhhKhj@ubh: The Zihintpause extension is}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj<ubj)}(hhh]h)}(hlsupported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified").h]hpsupported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 (“Zihintpause is ratified”).}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj9ubah}(h]h ]h"]h$]h&]uh1jOhj5ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(hy:c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual. h]jP)}(hhh]jU)}(hv:c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual. h](j[)}(hC:c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZIHPM`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZIHPM}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZIHPMuh1hhhhKhjubh!: The Zihpm extension version 2.0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(h1is supported as defined in the RISC-V ISA manual.h]h1is supported as defined in the RISC-V ISA manual.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE32X`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZVE32X}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVE32Xuh1hhhhKhjubhp: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE32F`h]h)}(hj8h]hRISCV_HWPROBE_EXT_ZVE32F}(hj:hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj6ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVE32Fuh1hhhhKhj2ubhp: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj.ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE64X`h]h)}(hjoh]hRISCV_HWPROBE_EXT_ZVE64X}(hjqhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjmubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVE64Xuh1hhhhKhjiubhp: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE64F`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZVE64F}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVE64Fuh1hhhhKhjubhp: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE64D`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZVE64D}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVE64Duh1hhhhKhjubhp: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). h](j[)}(hL:c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension ish](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZIMOP`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZIMOP}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZIMOPuh1hhhhKhjubh*: The Zimop May-Be-Operations extension is}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hisupported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0").h]hmsupported as defined in the RISC-V ISA manual starting from commit 58220614a5f (“Zimop is ratified/1.0”).}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjBubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h](j[)}(hH:c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standardh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCA`h]h)}(hj|h]hRISCV_HWPROBE_EXT_ZCA}(hj~hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjzubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZCAuh1hhhhKhjvubh(: The Zca extension part of Zc* standard}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjrubj)}(hhh]h)}(hextensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h]hextensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jThhhKhjoubah}(h]h ]h"]h$]h&]uh1jOhjkubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h](j[)}(hH:c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standardh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCB`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZCB}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZCBuh1hhhhKhjubh(: The Zcb extension part of Zc* standard}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hextensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h]hextensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h](j[)}(hH:c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standardh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCD`h]h)}(hj>h]hRISCV_HWPROBE_EXT_ZCD}(hj@hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj<ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZCDuh1hhhhKhj8ubh(: The Zcd extension part of Zc* standard}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhj4ubj)}(hhh]h)}(hextensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h]hextensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jThhhKhj1ubah}(h]h ]h"]h$]h&]uh1jOhj-ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h](j[)}(hH:c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standardh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCF`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZCF}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZCFuh1hhhhKhjubh(: The Zcf extension part of Zc* standard}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hextensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h]hextensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0"). h](j[)}(hL:c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension ish](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZCMOP`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZCMOP}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZCMOPuh1hhhhKhjubh*: The Zcmop May-Be-Operations extension is}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hisupported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0").h]hmsupported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 (“Zcmop is ratified/1.0”).}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual. h](j[)}(hG:c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported ash](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZAWRS`h]h)}(hjah]hRISCV_HWPROBE_EXT_ZAWRS}(hjchhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj_ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZAWRSuh1hhhhKhj[ubh%: The Zawrs extension is supported as}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjWubj)}(hhh]h)}(hbratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual.h]hfratified in commit 98918c844281 (“Merge pull request #1217 from riscv/zawrs”) of riscv-isa-manual.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jThhhKhjTubah}(h]h ]h"]h$]h&]uh1jOhjPubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). h](j[)}(hG:c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported ash](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZAAMO`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZAAMO}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZAAMOuh1hhhhKhjubh%: The Zaamo extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hvdefined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)").h]hzdefined in the in the RISC-V ISA manual starting from commit e87412e621f1 (“integrate Zaamo and Zalrsc text (#1304)”).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). h](j[)}(hI:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`h]h)}(hj#h]hRISCV_HWPROBE_EXT_ZALRSC}(hj%hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj!ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZALRSCuh1hhhhKhjubh&: The Zalrsc extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhKhjubj)}(hhh]h)}(hvdefined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)").h]hzdefined in the in the RISC-V ISA manual starting from commit e87412e621f1 (“integrate Zaamo and Zalrsc text (#1304)”).}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhKhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. h](j[)}(hE:c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_SUPM`h]h)}(hjh]hRISCV_HWPROBE_EXT_SUPM}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_SUPMuh1hhhhMhj~ubh$: The Supm extension is supported as}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhMhjzubj)}(hhh]h)}(h@defined in version 1.0 of the RISC-V Pointer Masking extensions.h]h@defined in version 1.0 of the RISC-V Pointer Masking extensions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jThhhMhjwubah}(h]h ]h"]h$]h&]uh1jOhjsubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h](j[)}(hK:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported ash](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZFBFMIN}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZFBFMINuh1hhhhMhjubh': The Zfbfmin extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhMhjubj)}(hhh]h)}(hcdefined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16").h]hgdefined in the RISC-V ISA manual starting from commit 4dc23d6229de (“Added Chapter title to BF16”).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhMhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h](j[)}(hM:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported ash](h)}(h%:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`h]h)}(hjFh]hRISCV_HWPROBE_EXT_ZVFBFMIN}(hjHhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjDubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVFBFMINuh1hhhhM hj@ubh(: The Zvfbfmin extension is supported as}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhM hj<ubj)}(hhh]h)}(hcdefined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16").h]hgdefined in the RISC-V ISA manual starting from commit 4dc23d6229de (“Added Chapter title to BF16”).}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjmubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jThhhM hj9ubah}(h]h ]h"]h$]h&]uh1jOhj5ubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h](j[)}(hM:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported ash](h)}(h%:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZVFBFWMA}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZVFBFWMAuh1hhhhM hjubh(: The Zvfbfwma extension is supported as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhM hjubj)}(hhh]h)}(hcdefined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16").h]hgdefined in the RISC-V ISA manual starting from commit 4dc23d6229de (“Added Chapter title to BF16”).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhM hjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h](j[)}(hJ:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, ash](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`h]h)}(hjh]hRISCV_HWPROBE_EXT_ZICBOM}(hj hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_EXT_ZICBOMuh1hhhhMhjubh': The Zicbom extension is supported, as}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhMhjubj)}(hhh]h)}(hEratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.h]hIratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhMhjubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1j4hjubeh}(h]h ]h"]h$]h&]jjuh1j/hhhKJhjOubeh}(h]h ]h"]h$]h&]uh1j4hjhhhNhNubj5)}(h:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. h](j[)}(hN:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values toh](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`h]h)}(hjuh]hRISCV_HWPROBE_KEY_CPUPERF_0}(hjwhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjsubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_CPUPERF_0uh1hhhhMhjoubh(: Deprecated. Returns similar values to}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhMhjkubj)}(hhh]h)}(h|:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value.h](h)}(h3:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`h]h)}(hjh]h(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERFuh1hhhhMhjubhI, but the key was mistakenly classified as a bitmask rather than a value.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jThhhMhjhubah}(h]h ]h"]h$]h&]uh1jOhjdubah}(h]h ]h"]h$]h&]uh1j4hjhhhNhNubj5)}(hX:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing the performance of misaligned scalar native word accesses on the selected set of processors. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of misaligned scalar accesses is unknown. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing the performance of misaligned scalar native word accesses on the selected set of processors.h](h)}(h3:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`h]h)}(hjh]h(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERFuh1hhhhMhjubhw: An enum value describing the performance of misaligned scalar native word accesses on the selected set of processors.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubj0)}(hhh](j5)}(hn:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of misaligned scalar accesses is unknown. h]h)}(hm:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of misaligned scalar accesses is unknown.h](h)}(h2:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`h]h)}(hj"h]h'RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN}(hj$hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_'RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWNuh1hhhhMhjubh;: The performance of misaligned scalar accesses is unknown.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow.h](h)}(h3:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`h]h)}(hjYh]h(RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED}(hj[hhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjWubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_(RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATEDuh1hhhhMhjSubh: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjOubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`h]h)}(hjh]h$RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_$RISCV_HWPROBE_MISALIGNED_SCALAR_SLOWuh1hhhhM!hjubh: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM!hjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`h]h)}(hjh]h$RISCV_HWPROBE_MISALIGNED_SCALAR_FAST}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_$RISCV_HWPROBE_MISALIGNED_SCALAR_FASTuh1hhhhM&hjubhh: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM&hjubah}(h]h ]h"]h$]h&]uh1j4hjubj5)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault.h](h)}(h6:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`h]h)}(hjh]h+RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_+RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTEDuh1hhhhM*hjubhc: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM*hjubah}(h]h ]h"]h$]h&]uh1j4hjubeh}(h]h ]h"]h$]h&]jjuh1j/hhhMhjubeh}(h]h ]h"]h$]h&]uh1j4hjhhhNhNubj5)}(hx:c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. h]h)}(hw:c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes.h](h)}(h.:c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`h]h)}(hjAh]h#RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE}(hjChhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_#RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZEuh1hhhhM.hj;ubhI: An unsigned int which represents the size of the Zicboz block in bytes.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM.hj7ubah}(h]h ]h"]h$]h&]uh1j4hjhhhhhNubj5)}(h:c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which represent the highest userspace virtual address usable. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which represent the highest userspace virtual address usable.h](h)}(h1:c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`h]h)}(hjxh]h&RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS}(hjzhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjvubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_&RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESSuh1hhhhM1hjrubhP: An unsigned long which represent the highest userspace virtual address usable.}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM1hjnubah}(h]h ]h"]h$]h&]uh1j4hjhhhhhNubj5)}(hM:c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`. h]h)}(hL:c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.h](h)}(h*:c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`h]h)}(hjh]hRISCV_HWPROBE_KEY_TIME_CSR_FREQ}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_KEY_TIME_CSR_FREQuh1hhhhM4hjubh: Frequency (in Hz) of }(hjhhhNhNubhtitle_reference)}(h `time CSR`h]htime CSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1j4hjhhhhhNubj5)}(hX:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the performance of misaligned vector accesses on the selected set of processors. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. h](jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the performance of misaligned vector accesses on the selected set of processors. h](j[)}(hQ:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing theh](h)}(h3:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`h]h)}(hjh]h(RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_(RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERFuh1hhhhM7hjubh: An enum value describing the}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhM7hjubj)}(hhh]h)}(hLperformance of misaligned vector accesses on the selected set of processors.h]hLperformance of misaligned vector accesses on the selected set of processors.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jThhhM7hjubah}(h]h ]h"]h$]h&]uh1jOhjubj0)}(hhh](j5)}(hn:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown. h]h)}(hm:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown.h](h)}(h2:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`h]h)}(hjXh]h'RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN}(hjZhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjVubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_'RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWNuh1hhhhM9hjRubh;: The performance of misaligned vector accesses is unknown.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM9hjNubah}(h]h ]h"]h$]h&]uh1j4hjKubj5)}(hX:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. h]h)}(hX:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`h]h)}(hjh]h$RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_$RISCV_HWPROBE_MISALIGNED_VECTOR_SLOWuh1hhhhM<hjubh: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM<hjubah}(h]h ]h"]h$]h&]uh1j4hjKubj5)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`h]h)}(hjh]h$RISCV_HWPROBE_MISALIGNED_VECTOR_FAST}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_$RISCV_HWPROBE_MISALIGNED_VECTOR_FASTuh1hhhhM@hjubh: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM@hjubah}(h]h ]h"]h$]h&]uh1j4hjKubj5)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault.h](h)}(h6:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`h]h)}(hjh]h+RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_+RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTEDuh1hhhhMChjubhc: Misaligned vector accesses are not supported at all and will generate a misaligned address fault.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMChjubah}(h]h ]h"]h$]h&]uh1j4hjKubeh}(h]h ]h"]h$]h&]jjuh1j/hhhM9hjubeh}(h]h ]h"]h$]h&]uh1j4hjhhhNhNubj5)}(hX:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * T-HEAD * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h/:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`h]h)}(hj@h]h$RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0}(hjBhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhj>ubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_$RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0uh1hhhhMFhj:ubhP: A bitmask containing the thead vendor extensions that are compatible with the }(hj:hhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]h)}(hjch]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjehhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjaubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_RISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhMFhj:ubh: base system behavior.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMFhj6ubj0)}(hhh]j5)}(hT-HEAD * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h](h)}(hT-HEADh]hT-HEAD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubj0)}(hhh]j5)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h]jP)}(hhh]jU)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h](j[)}(hI:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendorh](h)}(h0:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`h]h)}(hjh]h%RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR}(hjhhhNhNubah}(h]h ](jLjMc-macroeh"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]refdocjY refdomainjMreftypemacro refexplicitrefwarnj_%RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTORuh1hhhhMNhjubh: The xtheadvector vendor}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jZhhhMNhjubj)}(hhh]h)}(hextension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. 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