Wsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/arch/riscv/hwprobemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/pt_BR/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/arch/riscv/hwprobemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/arch/riscv/hwprobe.rsthKubhsection)}(hhh](htitle)}(h!RISC-V Hardware Probing Interfaceh]h!RISC-V Hardware Probing Interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hmThe RISC-V hardware probing interface is based around a single syscall, which is defined in ::h]hlThe RISC-V hardware probing interface is based around a single syscall, which is defined in :}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh literal_block)}(hstruct riscv_hwprobe { __s64 key; __u64 value; }; long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, size_t cpusetsize, cpu_set_t *cpus, unsigned int flags);h]hstruct riscv_hwprobe { __s64 key; __u64 value; }; long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, size_t cpusetsize, cpu_set_t *cpus, unsigned int flags);}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhK hhhhubh)}(hXAThe arguments are split into three groups: an array of key-value pairs, a CPU set, and some flags. The key-value pairs are supplied with a count. Userspace must prepopulate the key field for each element, and the kernel will fill in the value if the key is recognized. If a key is unknown to the kernel, its key field will be cleared to -1, and its value set to 0. The CPU set is defined by CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor, arch, impl), the returned value will only be valid if all CPUs in the given set have the same value. Otherwise -1 will be returned. For boolean-like keys, the value returned will be a logical AND of the values for the specified CPUs. Usermode can supply NULL for ``cpus`` and 0 for ``cpusetsize`` as a shortcut for all online CPUs. The currently supported flags are:h](hXThe arguments are split into three groups: an array of key-value pairs, a CPU set, and some flags. The key-value pairs are supplied with a count. Userspace must prepopulate the key field for each element, and the kernel will fill in the value if the key is recognized. If a key is unknown to the kernel, its key field will be cleared to -1, and its value set to 0. The CPU set is defined by CPU_SET(3) with size }(hhhhhNhNubhliteral)}(h``cpusetsize``h]h cpusetsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhubhX0 bytes. For value-like keys (eg. vendor, arch, impl), the returned value will only be valid if all CPUs in the given set have the same value. Otherwise -1 will be returned. For boolean-like keys, the value returned will be a logical AND of the values for the specified CPUs. Usermode can supply NULL for }(hhhhhNhNubj)}(h``cpus``h]hcpus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhubh and 0 for }(hhhhhNhNubj)}(h``cpusetsize``h]h cpusetsize}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhubhF as a shortcut for all online CPUs. The currently supported flags are:}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh]h list_item)}(hX2:c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior of sys_riscv_hwprobe(). Instead of populating the values of keys for a given set of CPUs, the values of each key are given and the set of CPUs is reduced by sys_riscv_hwprobe() to only those which match each of the key-value pairs. How matching is done depends on the key type. For value-like keys, matching means to be the exact same as the value. For boolean-like keys, matching means the result of a logical AND of the pair's value with the CPU's value is exactly the same as the pair's value. Additionally, when ``cpus`` is an empty set, then it is initialized to all online CPUs which fit within it, i.e. the CPU set returned is the reduction of all the online CPUs which can be represented with a CPU set of size ``cpusetsize``. h]h)}(hX1:c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior of sys_riscv_hwprobe(). Instead of populating the values of keys for a given set of CPUs, the values of each key are given and the set of CPUs is reduced by sys_riscv_hwprobe() to only those which match each of the key-value pairs. How matching is done depends on the key type. For value-like keys, matching means to be the exact same as the value. For boolean-like keys, matching means the result of a logical AND of the pair's value with the CPU's value is exactly the same as the pair's value. Additionally, when ``cpus`` is an empty set, then it is initialized to all online CPUs which fit within it, i.e. the CPU set returned is the reduction of all the online CPUs which can be represented with a CPU set of size ``cpusetsize``.h](h)}(h#:c:macro:`RISCV_HWPROBE_WHICH_CPUS`h]j)}(hjTh]hRISCV_HWPROBE_WHICH_CPUS}(hjVhhhNhNubah}(h]h ](xrefcc-macroeh"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]refdocarch/riscv/hwprobe refdomainjareftypemacro refexplicitrefwarn reftargetRISCV_HWPROBE_WHICH_CPUSuh1hhhhKhjNubhX:: This flag basically reverses the behavior of sys_riscv_hwprobe(). Instead of populating the values of keys for a given set of CPUs, the values of each key are given and the set of CPUs is reduced by sys_riscv_hwprobe() to only those which match each of the key-value pairs. How matching is done depends on the key type. For value-like keys, matching means to be the exact same as the value. For boolean-like keys, matching means the result of a logical AND of the pair’s value with the CPU’s value is exactly the same as the pair’s value. Additionally, when }(hjNhhhNhNubj)}(h``cpus``h]hcpus}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubh is an empty set, then it is initialized to all online CPUs which fit within it, i.e. the CPU set returned is the reduction of all the online CPUs which can be represented with a CPU set of size }(hjNhhhNhNubj)}(h``cpusetsize``h]h cpusetsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubh.}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jHhjEhhhhhNubah}(h]h ]h"]h$]h&]bullet*uh1jChhhKhhhhubh)}(hGAll other flags are reserved for future compatibility and must be zero.h]hGAll other flags are reserved for future compatibility and must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hhhhubh)}(hGOn success 0 is returned, on failure a negative error code is returned.h]hGOn success 0 is returned, on failure a negative error code is returned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hhhhubh)}(hThe following keys are defined:h]hThe following keys are defined:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hhhhubjD)}(hhh](jI)}(h:c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``, as defined by the RISC-V privileged architecture specification. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``, as defined by the RISC-V privileged architecture specification.h](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_MVENDORID`h]j)}(hjh]hRISCV_HWPROBE_KEY_MVENDORID}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_MVENDORIDuh1hhhhK0hjubh: Contains the value of }(hjhhhNhNubj)}(h ``mvendorid``h]h mvendorid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhA, as defined by the RISC-V privileged architecture specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(h:c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as defined by the RISC-V privileged architecture specification. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as defined by the RISC-V privileged architecture specification.h](h)}(h$:c:macro:`RISCV_HWPROBE_KEY_MARCHID`h]j)}(hj1h]hRISCV_HWPROBE_KEY_MARCHID}(hj3hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_MARCHIDuh1hhhhK3hj+ubh: Contains the value of }(hj+hhhNhNubj)}(h ``marchid``h]hmarchid}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubhA, as defined by the RISC-V privileged architecture specification.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK3hj'ubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(h:c:macro:`RISCV_HWPROBE_KEY_MIMPID`: Contains the value of ``mimpid``, as defined by the RISC-V privileged architecture specification. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_MIMPID`: Contains the value of ``mimpid``, as defined by the RISC-V privileged architecture specification.h](h)}(h#:c:macro:`RISCV_HWPROBE_KEY_MIMPID`h]j)}(hjzh]hRISCV_HWPROBE_KEY_MIMPID}(hj|hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_MIMPIDuh1hhhhK6hjtubh: Contains the value of }(hjthhhNhNubj)}(h ``mimpid``h]hmimpid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubhA, as defined by the RISC-V privileged architecture specification.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK6hjpubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(hX:c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base user-visible behavior that this kernel supports. The following base user ABIs are defined: * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken): * The ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base user-visible behavior that this kernel supports. The following base user ABIs are defined:h](h)}(h*:c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`h]j)}(hjh]hRISCV_HWPROBE_KEY_BASE_BEHAVIOR}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_BASE_BEHAVIORuh1hhhhK9hjubh{: A bitmask containing the base user-visible behavior that this kernel supports. The following base user ABIs are defined:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK9hjubjD)}(hhh]jI)}(hX:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken): * The ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). h](h)}(hX%:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken):h](h)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]j)}(hjh]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhK=hjubh: Support for rv32ima or rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the privileged ISA, with the following known exceptions (more exceptions may be added, but only if it can be demonstrated that the user ABI is not broken):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK=hjubjD)}(hhh]jI)}(hThe ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). h]h)}(hThe ``fence.i`` instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO).h](hThe }(hj%hhhNhNubj)}(h ``fence.i``h]hfence.i}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh instruction cannot be directly executed by userspace programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO).}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKBhj!ubah}(h]h ]h"]h$]h&]uh1jHhjubah}(h]h ]h"]h$]h&]jjuh1jChhhKBhjubeh}(h]h ]h"]h$]h&]uh1jHhjubah}(h]h ]h"]h$]h&]jjuh1jChhhK=hjubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(hX*:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as defined by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported as defined in the RISC-V ISA manual. Zfh is a superset of Zfhmin, so RISCV_HWPROBE_EXT_ZFHMIN is reported whenever RISCV_HWPROBE_EXT_ZFH is. * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). Zvfh is a superset of Zvfhmin, so RISCV_HWPROBE_EXT_ZVFHMIN is reported whenever RISCV_HWPROBE_EXT_ZVFH is. * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0"). * :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as ratified in commit 49f49c842ff9 ("Update to Rafified state") of riscv-zabha. * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZICFILP`: The Zicfilp extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 ("Update build-pdf.yml") of riscv-cfi. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`h]j)}(hjmh]hRISCV_HWPROBE_KEY_IMA_EXT_0}(hjohhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_IMA_EXT_0uh1hhhhKFhjgubh?: A bitmask containing extensions that are compatible with the }(hjghhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]j)}(hjh]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhKFhjgubh: base system behavior.}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKFhjcubjD)}(hhh](jI)}(h:c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as defined by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. h]h)}(h:c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as defined by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.h](h)}(h:c:macro:`RISCV_HWPROBE_IMA_FD`h]j)}(hjh]hRISCV_HWPROBE_IMA_FD}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_IMA_FDuh1hhhhKJhjubh: The F and D extensions are supported, as defined by commit cd20cee (“FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum”) of the RISC-V ISA manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKJhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(hr:c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. h]h)}(hq:c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual.h](h)}(h:c:macro:`RISCV_HWPROBE_IMA_C`h]j)}(hjh]hRISCV_HWPROBE_IMA_C}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_IMA_Cuh1hhhhKNhjubhS: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h~:c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h:c:macro:`RISCV_HWPROBE_IMA_V`h]j)}(hj2h]hRISCV_HWPROBE_IMA_V}(hj4hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_IMA_Vuh1hhhhKQhj,ubh`: The V extension is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKQhj(ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBA`h]j)}(hjih]hRISCV_HWPROBE_EXT_ZBA}(hjkhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBAuh1hhhhKThjcubhv: The Zba address generation extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKThj_ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBB`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZBB}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBBuh1hhhhKXhjubhc: The Zbb extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKXhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBS`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZBS}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBSuh1hhhhK[hjubhc: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZICBOZ}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICBOZuh1hhhhK^hjubhq: The Zicboz extension is supported, as ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZBC`h]j)}(hjEh]hRISCV_HWPROBE_EXT_ZBC}(hjGhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBCuh1hhhhKahj?ubhb The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKahj;ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZBKB`h]j)}(hj|h]hRISCV_HWPROBE_EXT_ZBKB}(hj~hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBKBuh1hhhhKdhjvubh` The Zbkb extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKdhjrubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZBKC`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZBKC}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBKCuh1hhhhKghjubh` The Zbkc extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKghjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZBKX`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZBKX}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZBKXuh1hhhhKjhjubh` The Zbkx extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKND`h]j)}(hj!h]hRISCV_HWPROBE_EXT_ZKND}(hj#hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZKNDuh1hhhhKmhjubh` The Zknd extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKNE`h]j)}(hjXh]hRISCV_HWPROBE_EXT_ZKNE}(hjZhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZKNEuh1hhhhKphjRubh` The Zkne extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKphjNubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKNH`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZKNH}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZKNHuh1hhhhKshjubh` The Zknh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKshjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZKSED`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZKSED}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZKSEDuh1hhhhKvhjubha The Zksed extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZKSH`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZKSH}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZKSHuh1hhhhKyhjubh` The Zksh extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZKT`h]j)}(hj4h]hRISCV_HWPROBE_EXT_ZKT}(hj6hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZKTuh1hhhhK|hj.ubh_ The Zkt extension is supported, as defined in version 1.0 of the Scalar Crypto ISA extensions.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK|hj*ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVBB`h]j)}(hjkh]hRISCV_HWPROBE_EXT_ZVBB}(hjmhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVBBuh1hhhhKhjeubhl: The Zvbb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjaubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVBC`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZVBC}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVBCuh1hhhhKhjubhl: The Zvbc extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVKB`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZVKB}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKBuh1hhhhKhjubhl: The Zvkb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVKG`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZVKG}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKGuh1hhhhKhj ubhl: The Zvkg extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKNED`h]j)}(hjGh]hRISCV_HWPROBE_EXT_ZVKNED}(hjIhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKNEDuh1hhhhKhjAubhn: The Zvkned extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj=ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`h]j)}(hj~h]hRISCV_HWPROBE_EXT_ZVKNHA}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKNHAuh1hhhhKhjxubhn: The Zvknha extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjtubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZVKNHB}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKNHBuh1hhhhKhjubhn: The Zvknhb extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVKSED`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZVKSED}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKSEDuh1hhhhKhjubhn: The Zvksed extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZVKSH`h]j)}(hj# h]hRISCV_HWPROBE_EXT_ZVKSH}(hj% hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj! ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKSHuh1hhhhKhj ubhm: The Zvksh extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVKT`h]j)}(hjZ h]hRISCV_HWPROBE_EXT_ZVKT}(hj\ hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjX ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVKTuh1hhhhKhjT ubhl: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.}(hjT hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjP ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported as defined in the RISC-V ISA manual. Zfh is a superset of Zfhmin, so RISCV_HWPROBE_EXT_ZFHMIN is reported whenever RISCV_HWPROBE_EXT_ZFH is. h]hdefinition_list)}(hhh]hdefinition_list_item)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported as defined in the RISC-V ISA manual. Zfh is a superset of Zfhmin, so RISCV_HWPROBE_EXT_ZFHMIN is reported whenever RISCV_HWPROBE_EXT_ZFH is. h](hterm)}(hL:c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supportedh](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZFH`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZFH}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZFHuh1hhhhKhj ubh,: The Zfh extension version 1.0 is supported}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j hhhKhj ubh definition)}(hhh]h)}(has defined in the RISC-V ISA manual. Zfh is a superset of Zfhmin, so RISCV_HWPROBE_EXT_ZFHMIN is reported whenever RISCV_HWPROBE_EXT_ZFH is.h]has defined in the RISC-V ISA manual. Zfh is a superset of Zfhmin, so RISCV_HWPROBE_EXT_ZFHMIN is reported whenever RISCV_HWPROBE_EXT_ZFH is.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(hx:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual. h]h)}(hw:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZFHMIN}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZFHMINuh1hhhhKhj ubhT: The Zfhmin extension version 1.0 is supported as defined in the RISC-V ISA manual.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h~:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual. h]h)}(h}:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual.h](h)}(h&:c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`h]j)}(hj1 h]hRISCV_HWPROBE_EXT_ZIHINTNTL}(hj3 hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj/ ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZIHINTNTLuh1hhhhKhj+ ubhW: The Zihintntl extension version 1.0 is supported as defined in the RISC-V ISA manual.}(hj+ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj' ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(hX+:c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). Zvfh is a superset of Zvfhmin, so RISCV_HWPROBE_EXT_ZVFHMIN is reported whenever RISCV_HWPROBE_EXT_ZVFH is. h]j )}(hhh]j )}(hX":c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). Zvfh is a superset of Zvfhmin, so RISCV_HWPROBE_EXT_ZVFHMIN is reported whenever RISCV_HWPROBE_EXT_ZVFH is. h](j )}(hE:c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported ash](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZVFH`h]j)}(hjo h]hRISCV_HWPROBE_EXT_ZVFH}(hjq hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjm ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVFHuh1hhhhKhji ubh$: The Zvfh extension is supported as}(hji hhhNhNubeh}(h]h ]h"]h$]h&]uh1j hhhKhje ubj )}(hhh]h)}(hdefined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). Zvfh is a superset of Zvfhmin, so RISCV_HWPROBE_EXT_ZVFHMIN is reported whenever RISCV_HWPROBE_EXT_ZVFH is.h]hdefined in the RISC-V Vector manual starting from commit e2ccd0548d6c (“Remove draft warnings from Zvfh[min]”). Zvfh is a superset of Zvfhmin, so RISCV_HWPROBE_EXT_ZVFHMIN is reported whenever RISCV_HWPROBE_EXT_ZVFH is.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j hje ubeh}(h]h ]h"]h$]h&]uh1j hhhKhjb ubah}(h]h ]h"]h$]h&]uh1j hj^ ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]").h](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZVFHMIN}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVFHMINuh1hhhhKhj ubh: The Zvfhmin extension is supported as defined in the RISC-V Vector manual starting from commit e2ccd0548d6c (“Remove draft warnings from Zvfh[min]”).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified").h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZFA`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZFA}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZFAuh1hhhhKhj ubh: The Zfa extension is supported as defined in the RISC-V ISA manual starting from commit 056b6ff467c7 (“Zfa is ratified”).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.")h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_ZTSO`h]j)}(hj7 h]hRISCV_HWPROBE_EXT_ZTSO}(hj9 hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj5 ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZTSOuh1hhhhKhj1 ubh: The Ztso extension is supported as defined in the RISC-V ISA manual starting from commit 5618fb5a216b (“Ztso is now ratified.”)}(hj1 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj- ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified").h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZACAS`h]j)}(hjn h]hRISCV_HWPROBE_EXT_ZACAS}(hjp hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjl ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZACASuh1hhhhKhjh ubh: The Zacas extension is supported as defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c (“update to ratified”).}(hjh hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjd ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(hx:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual. h]h)}(hw:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICNTR`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZICNTR}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICNTRuh1hhhhKhj ubhT: The Zicntr extension version 2.0 is supported as defined in the RISC-V ISA manual.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff")h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICOND`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZICOND}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICONDuh1hhhhKhj ubh: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 (“Add changes requested by Ved during signoff”)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified").h](h)}(h(:c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZIHINTPAUSE}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZIHINTPAUSEuh1hhhhKhj ubh: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 (“Zihintpause is ratified”).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(hv:c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual. h]h)}(hu:c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZIHPM`h]j)}(hjJ h]hRISCV_HWPROBE_EXT_ZIHPM}(hjL hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjH ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZIHPMuh1hhhhKhjD ubhS: The Zihpm extension version 2.0 is supported as defined in the RISC-V ISA manual.}(hjD hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@ ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE32X`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZVE32X}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVE32Xuh1hhhhKhj{ ubhp: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hj{ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjw ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE32F`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZVE32F}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVE32Fuh1hhhhKhj ubhp: The Vector sub-extension Zve32f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE64X`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZVE64X}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVE64Xuh1hhhhKhj ubhp: The Vector sub-extension Zve64x is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE64F`h]j)}(hj& h]hRISCV_HWPROBE_EXT_ZVE64F}(hj( hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj$ ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVE64Fuh1hhhhKhj ubhp: The Vector sub-extension Zve64f is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZVE64D`h]j)}(hj] h]hRISCV_HWPROBE_EXT_ZVE64D}(hj_ hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj[ ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVE64Duh1hhhhKhjW ubhp: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual.}(hjW hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjS ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0").h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZIMOP`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZIMOP}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZIMOPuh1hhhhKhj ubh: The Zimop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit 58220614a5f (“Zimop is ratified/1.0”).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCA`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZCA}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZCAuh1hhhhKhj ubh: The Zca extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCB`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZCB}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZCBuh1hhhhKhj ubh: The Zcb extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCD`h]j)}(hj9h]hRISCV_HWPROBE_EXT_ZCD}(hj;hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZCDuh1hhhhKhj3ubh: The Zcd extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj/ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.h](h)}(h :c:macro:`RISCV_HWPROBE_EXT_ZCF`h]j)}(hjph]hRISCV_HWPROBE_EXT_ZCF}(hjrhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZCFuh1hhhhKhjjubh: The Zcf extension part of Zc* standard extensions for code size reduction, as ratified in commit 8be3419c1c0 (“Zcf doesn’t exist on RV64 as it contains no instructions”) of riscv-code-size-reduction.}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjfubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 ("Zcmop is ratified/1.0").h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZCMOP`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZCMOP}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZCMOPuh1hhhhKhjubh: The Zcmop May-Be-Operations extension is supported as defined in the RISC-V ISA manual starting from commit c732a4f39a4 (“Zcmop is ratified/1.0”).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as ratified in commit 98918c844281 ("Merge pull request #1217 from riscv/zawrs") of riscv-isa-manual.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZAWRS`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZAWRS}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZAWRSuh1hhhhKhjubh: The Zawrs extension is supported as ratified in commit 98918c844281 (“Merge pull request #1217 from riscv/zawrs”) of riscv-isa-manual.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)").h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZAAMO`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZAAMO}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZAAMOuh1hhhhKhjubh: The Zaamo extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 (“integrate Zaamo and Zalrsc text (#1304)”).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZALASR`h]j)}(hjLh]hRISCV_HWPROBE_EXT_ZALASR}(hjNhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZALASRuh1hhhhKhjFubhp: The Zalasr extension is supported as frozen at commit 194f0094 (“Version 0.9 for freeze”) of riscv-zalasr.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjBubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)").h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZALRSC`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZALRSC}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZALRSCuh1hhhhMhj}ubh: The Zalrsc extension is supported as defined in the in the RISC-V ISA manual starting from commit e87412e621f1 (“integrate Zaamo and Zalrsc text (#1304)”).}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjyubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions.h](h)}(h!:c:macro:`RISCV_HWPROBE_EXT_SUPM`h]j)}(hjh]hRISCV_HWPROBE_EXT_SUPM}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_SUPMuh1hhhhMhjubhe: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16").h](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZFBFMIN}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZFBFMINuh1hhhhMhjubh: The Zfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de (“Added Chapter title to BF16”).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16").h](h)}(h%:c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`h]j)}(hj(h]hRISCV_HWPROBE_EXT_ZVFBFMIN}(hj*hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVFBFMINuh1hhhhM hj"ubh: The Zvfbfmin extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de (“Added Chapter title to BF16”).}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16"). h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de ("Added Chapter title to BF16").h](h)}(h%:c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`h]j)}(hj_h]hRISCV_HWPROBE_EXT_ZVFBFWMA}(hjahhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZVFBFWMAuh1hhhhMhjYubh: The Zvfbfwma extension is supported as defined in the RISC-V ISA manual starting from commit 4dc23d6229de (“Added Chapter title to BF16”).}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICBOM`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZICBOM}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICBOMuh1hhhhMhjubhq: The Zicbom extension is supported, as ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as ratified in commit 49f49c842ff9 ("Update to Rafified state") of riscv-zabha. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as ratified in commit 49f49c842ff9 ("Update to Rafified state") of riscv-zabha.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZABHA`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZABHA}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZABHAuh1hhhhMhjubhv: The Zabha extension is supported as ratified in commit 49f49c842ff9 (“Update to Rafified state”) of riscv-zabha.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICBOP`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZICBOP}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICBOPuh1hhhhMhjubhq: The Zicbop extension is supported, as ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZILSD`h]j)}(hj;h]hRISCV_HWPROBE_EXT_ZILSD}(hj=hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZILSDuh1hhhhMhj5ubh: The Zilsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 (“Integrating load/store pair for RV32 with the main manual”) of the riscv-isa-manual.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual.h](h)}(h":c:macro:`RISCV_HWPROBE_EXT_ZCLSD`h]j)}(hjrh]hRISCV_HWPROBE_EXT_ZCLSD}(hjthhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZCLSDuh1hhhhM"hjlubh: The Zclsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 (“Integrating load/store pair for RV32 with the main manual”) of the riscv-isa-manual.}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM"hjhubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICFILP`: The Zicfilp extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 ("Update build-pdf.yml") of riscv-cfi. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICFILP`: The Zicfilp extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 ("Update build-pdf.yml") of riscv-cfi.h](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZICFILP`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZICFILP}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICFILPuh1hhhhM&hjubh: The Zicfilp extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 (“Update build-pdf.yml”) of riscv-cfi.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM&hjubah}(h]h ]h"]h$]h&]uh1jHhjubeh}(h]h ]h"]h$]h&]jjuh1jChhhKJhjcubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(h:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value.h](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`h]j)}(hjh]hRISCV_HWPROBE_KEY_CPUPERF_0}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_CPUPERF_0uh1hhhhM+hjubh): Deprecated. Returns similar values to }(hjhhhNhNubh)}(h3:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`h]j)}(hjh]h(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERFuh1hhhhM+hjubhI, but the key was mistakenly classified as a bitmask rather than a value.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM+hjubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(hX:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing the performance of misaligned scalar native word accesses on the selected set of processors. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of misaligned scalar accesses is unknown. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses. * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing the performance of misaligned scalar native word accesses on the selected set of processors.h](h)}(h3:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`h]j)}(hjFh]h(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF}(hjHhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs(RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERFuh1hhhhM/hj@ubhw: An enum value describing the performance of misaligned scalar native word accesses on the selected set of processors.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM/hj<ubjD)}(hhh](jI)}(hn:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of misaligned scalar accesses is unknown. h]h)}(hm:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of misaligned scalar accesses is unknown.h](h)}(h2:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`h]j)}(hjzh]h'RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN}(hj|hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs'RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWNuh1hhhhM3hjtubh;: The performance of misaligned scalar accesses is unknown.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM3hjpubah}(h]h ]h"]h$]h&]uh1jHhjmubjI)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow.h](h)}(h3:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`h]j)}(hjh]h(RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs(RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATEDuh1hhhhM6hjubh: Misaligned scalar accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM6hjubah}(h]h ]h"]h$]h&]uh1jHhjmubjI)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`h]j)}(hjh]h$RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs$RISCV_HWPROBE_MISALIGNED_SCALAR_SLOWuh1hhhhM:hjubh: Misaligned scalar native word sized accesses are slower than the equivalent quantity of byte accesses. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM:hjubah}(h]h ]h"]h$]h&]uh1jHhjmubjI)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`h]j)}(hjh]h$RISCV_HWPROBE_MISALIGNED_SCALAR_FAST}(hj!hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs$RISCV_HWPROBE_MISALIGNED_SCALAR_FASTuh1hhhhM?hjubhh: Misaligned scalar native word sized accesses are faster than the equivalent quantity of byte accesses.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM?hjubah}(h]h ]h"]h$]h&]uh1jHhjmubjI)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault.h](h)}(h6:c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`h]j)}(hjVh]h+RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED}(hjXhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs+RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTEDuh1hhhhMChjPubhc: Misaligned scalar accesses are not supported at all and will generate a misaligned address fault.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMChjLubah}(h]h ]h"]h$]h&]uh1jHhjmubeh}(h]h ]h"]h$]h&]jjuh1jChhhM3hj<ubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(hx:c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. h]h)}(hw:c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes.h](h)}(h.:c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`h]j)}(hjh]h#RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs#RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZEuh1hhhhMGhjubhI: An unsigned int which represents the size of the Zicboz block in bytes.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMGhjubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(h:c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which represent the highest userspace virtual address usable. h]h)}(h:c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which represent the highest userspace virtual address usable.h](h)}(h1:c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`h]j)}(hjh]h&RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs&RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESSuh1hhhhMJhjubhP: An unsigned long which represent the highest userspace virtual address usable.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(hM:c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`. h]h)}(hL:c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.h](h)}(h*:c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`h]j)}(hjh]hRISCV_HWPROBE_KEY_TIME_CSR_FREQ}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_TIME_CSR_FREQuh1hhhhMMhjubh: Frequency (in Hz) of }(hjhhhNhNubhtitle_reference)}(h `time CSR`h]htime CSR}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMMhjubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(hX:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the performance of misaligned vector accesses on the selected set of processors. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the performance of misaligned vector accesses on the selected set of processors.h](h)}(h3:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`h]j)}(hjRh]h(RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF}(hjThhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs(RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERFuh1hhhhMOhjLubhk: An enum value describing the performance of misaligned vector accesses on the selected set of processors.}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMOhjHubjD)}(hhh](jI)}(hn:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown. h]h)}(hm:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown.h](h)}(h2:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`h]j)}(hjh]h'RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs'RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWNuh1hhhhMRhjubh;: The performance of misaligned vector accesses is unknown.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMRhj|ubah}(h]h ]h"]h$]h&]uh1jHhjyubjI)}(hX:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. h]h)}(hX:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`h]j)}(hjh]h$RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs$RISCV_HWPROBE_MISALIGNED_VECTOR_SLOWuh1hhhhMUhjubh: 32-bit misaligned accesses using vector registers are slower than the equivalent quantity of byte accesses via vector registers. Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMUhjubah}(h]h ]h"]h$]h&]uh1jHhjyubjI)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers.h](h)}(h/:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`h]j)}(hjh]h$RISCV_HWPROBE_MISALIGNED_VECTOR_FAST}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs$RISCV_HWPROBE_MISALIGNED_VECTOR_FASTuh1hhhhMYhjubh: 32-bit misaligned accesses using vector registers are faster than the equivalent quantity of byte accesses via vector registers.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jHhjyubjI)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. h]h)}(h:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault.h](h)}(h6:c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`h]j)}(hj+h]h+RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED}(hj-hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs+RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTEDuh1hhhhM\hj%ubhc: Misaligned vector accesses are not supported at all and will generate a misaligned address fault.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM\hj!ubah}(h]h ]h"]h$]h&]uh1jHhjyubeh}(h]h ]h"]h$]h&]jjuh1jChhhMRhjHubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(hXP:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the mips vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * MIPS * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor extension is supported in the MIPS ISA extensions spec. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the mips vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h.:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`h]j)}(hjnh]h#RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0}(hjphhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs#RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0uh1hhhhM_hjhubhO: A bitmask containing the mips vendor extensions that are compatible with the }(hjhhhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]j)}(hjh]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhM_hjhubh: base system behavior.}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM_hjdubjD)}(hhh]jI)}(hMIPS * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor extension is supported in the MIPS ISA extensions spec. h](h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjubjD)}(hhh]jI)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor extension is supported in the MIPS ISA extensions spec. h]h)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor extension is supported in the MIPS ISA extensions spec.h](h)}(h/:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`h]j)}(hjh]h$RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs$RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTLuh1hhhhMehjubhP: The xmipsexectl vendor extension is supported in the MIPS ISA extensions spec.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMehjubah}(h]h ]h"]h$]h&]uh1jHhjubah}(h]h ]h"]h$]h&]jjuh1jChhhMehjubeh}(h]h ]h"]h$]h&]uh1jHhjubah}(h]h ]h"]h$]h&]jjuh1jChhhMchjdubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(hX:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * T-HEAD * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h/:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`h]j)}(hj)h]h$RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0}(hj+hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs$RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0uh1hhhhMhhj#ubhP: A bitmask containing the thead vendor extensions that are compatible with the }(hj#hhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]j)}(hjLh]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjNhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhMhhj#ubh: base system behavior.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhhjubjD)}(hhh]jI)}(hT-HEAD * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h](h)}(hT-HEADh]hT-HEAD}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjvubjD)}(hhh]jI)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. "). h]h)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 ("Add T-Head VECTOR vendor extension. ").h](h)}(h0:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`h]j)}(hjh]h%RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs%RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTORuh1hhhhMnhjubh: The xtheadvector vendor extension is supported in the T-Head ISA extensions spec starting from commit a18c801634 (“Add T-Head VECTOR vendor extension. “).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMnhjubah}(h]h ]h"]h$]h&]uh1jHhjubah}(h]h ]h"]h$]h&]jjuh1jChhhMnhjvubeh}(h]h ]h"]h$]h&]uh1jHhjsubah}(h]h ]h"]h$]h&]jjuh1jChhhMlhjubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(hx:c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbom block in bytes. h]h)}(hw:c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbom block in bytes.h](h)}(h.:c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`h]j)}(hjh]h#RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs#RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZEuh1hhhhMrhjubhI: An unsigned int which represents the size of the Zicbom block in bytes.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMrhjubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(hX:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the sifive vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * SIFIVE * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Instruction Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Accumulate Instruction Extensions Specification. h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the sifive vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h0:c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`h]j)}(hjh]h%RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs%RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0uh1hhhhMuhjubhQ: A bitmask containing the sifive vendor extensions that are compatible with the }(hjhhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]j)}(hj>h]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hj@hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhMuhjubh: base system behavior.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMuhjubjD)}(hhh]jI)}(hXSIFIVE * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Instruction Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Accumulate Instruction Extensions Specification. h](h)}(hSIFIVEh]hSIFIVE}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhjhubjD)}(hhh](jI)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Extensions Specification. h]h)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Extensions Specification.h](h)}(h0:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`h]j)}(hjh]h%RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs%RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDODuh1hhhhM{hjubh}: The Xsfqmaccdod vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Extensions Specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM{hj}ubah}(h]h ]h"]h$]h&]uh1jHhjzubjI)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Instruction Extensions Specification. h]h)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Instruction Extensions Specification.h](h)}(h0:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`h]j)}(hjh]h%RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs%RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQuh1hhhhMhjubh: The Xsfqmaccqoq vendor extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication Instruction Extensions Specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjzubjI)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. h]h)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.h](h)}(h3:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`h]j)}(hjh]h(RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs(RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQFuh1hhhhMhjubh: The Xsfvfnrclipxfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjzubjI)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Accumulate Instruction Extensions Specification. h]h)}(h:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Accumulate Instruction Extensions Specification.h](h)}(h1:c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`h]j)}(hj,h]h&RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ}(hj.hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs&RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQuh1hhhhMhj&ubh: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Accumulate Instruction Extensions Specification.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj"ubah}(h]h ]h"]h$]h&]uh1jHhjzubeh}(h]h ]h"]h$]h&]jjuh1jChhhM{hjhubeh}(h]h ]h"]h$]h&]uh1jHhjeubah}(h]h ]h"]h$]h&]jjuh1jChhhMyhjubeh}(h]h ]h"]h$]h&]uh1jHhjhhhNhNubjI)}(hx:c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbop block in bytes. h]h)}(hw:c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbop block in bytes.h](h)}(h.:c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`h]j)}(hj{h]h#RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE}(hj}hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjs#RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZEuh1hhhhMhjuubhI: An unsigned int which represents the size of the Zicbop block in bytes.}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjqubah}(h]h ]h"]h$]h&]uh1jHhjhhhhhNubjI)}(hX^:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. * :c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 ("Update build-pdf.yml") of riscv-cfi. * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h](h)}(h:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.h](h)}(h&:c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`h]j)}(hjh]hRISCV_HWPROBE_KEY_IMA_EXT_1}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_KEY_IMA_EXT_1uh1hhhhMhjubhJ: A bitmask containing additional extensions that are compatible with the }(hjhhhNhNubh)}(h*:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`h]j)}(hjh]hRISCV_HWPROBE_BASE_BEHAVIOR_IMA}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_BASE_BEHAVIOR_IMAuh1hhhhMhjubh: base system behavior.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubjD)}(hhh](jI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 ("Update build-pdf.yml") of riscv-cfi. h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 ("Update build-pdf.yml") of riscv-cfi.h](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZICFISS`h]j)}(hj h]hRISCV_HWPROBE_EXT_ZICFISS}(hj hhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICFISSuh1hhhhMhjubh: The Zicfiss extension is supported, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified in commit 302a2d45c243 (“Update build-pdf.yml”) of riscv-cfi.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`h]j)}(hj@h]hRISCV_HWPROBE_EXT_ZICCLSM}(hjBhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICCLSMuh1hhhhMhj:ubh: The Zicclsm extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 (“Updated to ratified state.”)}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj6ubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h](h)}(h%:c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`h]j)}(hjwh]hRISCV_HWPROBE_EXT_ZICCAMOA}(hjyhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICCAMOAuh1hhhhMhjqubh: The Ziccamoa extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 (“Updated to ratified state.”)}(hjqhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjmubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZICCIF`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZICCIF}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICCIFuh1hhhhMhjubh: The Ziccif extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 (“Updated to ratified state.”)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h](h)}(h$:c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZICCRSE}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZICCRSEuh1hhhhMhjubh: The Ziccrse extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 (“Updated to ratified state.”)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jHhjubjI)}(h:c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h]h)}(h:c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.")h](h)}(h#:c:macro:`RISCV_HWPROBE_EXT_ZA64RS`h]j)}(hjh]hRISCV_HWPROBE_EXT_ZA64RS}(hjhhhNhNubah}(h]h ](j`jac-macroeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocjm refdomainjareftypemacro refexplicitrefwarnjsRISCV_HWPROBE_EXT_ZA64RSuh1hhhhMhjubh: The Za64rs extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 (“Updated to ratified state.”)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h 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