€•’Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ5/translations/zh_CN/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ5/translations/zh_TW/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ5/translations/it_IT/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ5/translations/ja_JP/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ5/translations/ko_KR/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ5/translations/pt_BR/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ5/translations/sp_SP/arch/powerpc/transactional_memory”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒTransactional Memory support”h]”hŒTransactional Memory support”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒO/var/lib/git/docbuild/linux/Documentation/arch/powerpc/transactional_memory.rst”h´KubhŒ paragraph”“”)”}”(hŒ’POWER kernel support for this feature is currently limited to supporting its use by user programs. It is not currently used by the kernel itself.”h]”hŒ’POWER kernel support for this feature is currently limited to supporting its use by user programs. It is not currently used by the kernel itself.”…””}”(hhÍh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhÌ)”}”(hŒpThis file aims to sum up how it is supported by Linux and what behaviour you can expect from your user programs.”h]”hŒpThis file aims to sum up how it is supported by Linux and what behaviour you can expect from your user programs.”…””}”(hhÛh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒBasic overview”h]”hŒBasic overview”…””}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhéh²hh³hÊh´K ubhÌ)”}”(hX.Hardware Transactional Memory is supported on POWER8 processors, and is a feature that enables a different form of atomic memory access. Several new instructions are presented to delimit transactions; transactions are guaranteed to either complete atomically or roll back and undo any partial changes.”h]”hX.Hardware Transactional Memory is supported on POWER8 processors, and is a feature that enables a different form of atomic memory access. Several new instructions are presented to delimit transactions; transactions are guaranteed to either complete atomically or roll back and undo any partial changes.”…””}”(hhúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khhéh²hubhÌ)”}”(hŒ&A simple transaction looks like this::”h]”hŒ%A simple transaction looks like this:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khhéh²hubhŒ literal_block”“”)”}”(hX†begin_move_money: tbegin beq abort_handler ld r4, SAVINGS_ACCT(r3) ld r5, CURRENT_ACCT(r3) subi r5, r5, 1 addi r4, r4, 1 std r4, SAVINGS_ACCT(r3) std r5, CURRENT_ACCT(r3) tend b continue abort_handler: ... test for odd failures ... /* Retry the transaction if it failed because it conflicted with * someone else: */ b begin_move_money”h]”hX†begin_move_money: tbegin beq abort_handler ld r4, SAVINGS_ACCT(r3) ld r5, CURRENT_ACCT(r3) subi r5, r5, 1 addi r4, r4, 1 std r4, SAVINGS_ACCT(r3) std r5, CURRENT_ACCT(r3) tend b continue abort_handler: ... test for odd failures ... /* Retry the transaction if it failed because it conflicted with * someone else: */ b begin_move_money”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1jh³hÊh´Khhéh²hubhÌ)”}”(hXÆThe 'tbegin' instruction denotes the start point, and 'tend' the end point. Between these points the processor is in 'Transactional' state; any memory references will complete in one go if there are no conflicts with other transactional or non-transactional accesses within the system. In this example, the transaction completes as though it were normal straight-line code IF no other processor has touched SAVINGS_ACCT(r3) or CURRENT_ACCT(r3); an atomic move of money from the current account to the savings account has been performed. Even though the normal ld/std instructions are used (note no lwarx/stwcx), either *both* SAVINGS_ACCT(r3) and CURRENT_ACCT(r3) will be updated, or neither will be updated.”h]”(hXyThe ‘tbegin’ instruction denotes the start point, and ‘tend’ the end point. Between these points the processor is in ‘Transactional’ state; any memory references will complete in one go if there are no conflicts with other transactional or non-transactional accesses within the system. In this example, the transaction completes as though it were normal straight-line code IF no other processor has touched SAVINGS_ACCT(r3) or CURRENT_ACCT(r3); an atomic move of money from the current account to the savings account has been performed. Even though the normal ld/std instructions are used (note no lwarx/stwcx), either ”…””}”(hj(h²hh³Nh´NubhŒemphasis”“”)”}”(hŒ*both*”h]”hŒboth”…””}”(hj2h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j0hj(ubhŒS SAVINGS_ACCT(r3) and CURRENT_ACCT(r3) will be updated, or neither will be updated.”…””}”(hj(h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K.hhéh²hubhÌ)”}”(hXpIf, in the meantime, there is a conflict with the locations accessed by the transaction, the transaction will be aborted by the CPU. Register and memory state will roll back to that at the 'tbegin', and control will continue from 'tbegin+4'. The branch to abort_handler will be taken this second time; the abort handler can check the cause of the failure, and retry.”h]”hXxIf, in the meantime, there is a conflict with the locations accessed by the transaction, the transaction will be aborted by the CPU. Register and memory state will roll back to that at the ‘tbegin’, and control will continue from ‘tbegin+4’. The branch to abort_handler will be taken this second time; the abort handler can check the cause of the failure, and retry.”…””}”(hjJh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K9hhéh²hubhÌ)”}”(hŒŠCheckpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR and a few other status/flag regs; see the ISA for details.”h]”hŒŠCheckpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR and a few other status/flag regs; see the ISA for details.”…””}”(hjXh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K?hhéh²hubeh}”(h]”Œbasic-overview”ah ]”h"]”Œbasic overview”ah$]”h&]”uh1hµhh·h²hh³hÊh´K ubh¶)”}”(hhh]”(h»)”}”(hŒCauses of transaction aborts”h]”hŒCauses of transaction aborts”…””}”(hjqh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjnh²hh³hÊh´KCubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ3Conflicts with cache lines used by other processors”h]”hÌ)”}”(hjˆh]”hŒ3Conflicts with cache lines used by other processors”…””}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KEhj†ubah}”(h]”h ]”h"]”h$]”h&]”uh1j„hjh²hh³hÊh´Nubj…)”}”(hŒSignals”h]”hÌ)”}”(hjŸh]”hŒSignals”…””}”(hj¡h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KFhjubah}”(h]”h ]”h"]”h$]”h&]”uh1j„hjh²hh³hÊh´Nubj…)”}”(hŒContext switches”h]”hÌ)”}”(hj¶h]”hŒContext switches”…””}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KGhj´ubah}”(h]”h ]”h"]”h$]”h&]”uh1j„hjh²hh³hÊh´Nubj…)”}”(hŒPSee the ISA for full documentation of everything that will abort transactions. ”h]”hÌ)”}”(hŒNSee the ISA for full documentation of everything that will abort transactions.”h]”hŒNSee the ISA for full documentation of everything that will abort transactions.”…””}”(hjÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KHhjËubah}”(h]”h ]”h"]”h$]”h&]”uh1j„hjh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jh³hÊh´KEhjnh²hubeh}”(h]”Œcauses-of-transaction-aborts”ah ]”h"]”Œcauses of transaction aborts”ah$]”h&]”uh1hµhh·h²hh³hÊh´KCubh¶)”}”(hhh]”(h»)”}”(hŒSyscalls”h]”hŒSyscalls”…””}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjóh²hh³hÊh´KLubhÌ)”}”(hŒ´Syscalls made from within an active transaction will not be performed and the transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT.”h]”hŒ´Syscalls made from within an active transaction will not be performed and the transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KNhjóh²hubhÌ)”}”(hXÚSyscalls made from within a suspended transaction are performed as normal and the transaction is not explicitly doomed by the kernel. However, what the kernel does to perform the syscall may result in the transaction being doomed by the hardware. The syscall is performed in suspended mode so any side effects will be persistent, independent of transaction success or failure. No guarantees are provided by the kernel about which syscalls will affect transaction success.”h]”hXÚSyscalls made from within a suspended transaction are performed as normal and the transaction is not explicitly doomed by the kernel. However, what the kernel does to perform the syscall may result in the transaction being doomed by the hardware. The syscall is performed in suspended mode so any side effects will be persistent, independent of transaction success or failure. No guarantees are provided by the kernel about which syscalls will affect transaction success.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KRhjóh²hubhÌ)”}”(hXrCare must be taken when relying on syscalls to abort during active transactions if the calls are made via a library. Libraries may cache values (which may give the appearance of success) or perform operations that cause transaction failure before entering the kernel (which may produce different failure codes). Examples are glibc's getpid() and lazy symbol resolution.”h]”hXtCare must be taken when relying on syscalls to abort during active transactions if the calls are made via a library. Libraries may cache values (which may give the appearance of success) or perform operations that cause transaction failure before entering the kernel (which may produce different failure codes). Examples are glibc’s getpid() and lazy symbol resolution.”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KZhjóh²hubeh}”(h]”Œsyscalls”ah ]”h"]”Œsyscalls”ah$]”h&]”uh1hµhh·h²hh³hÊh´KLubh¶)”}”(hhh]”(h»)”}”(hŒSignals”h]”hŒSignals”…””}”(hj9h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj6h²hh³hÊh´KbubhÌ)”}”(hXœDelivery of signals (both sync and async) during transactions provides a second thread state (ucontext/mcontext) to represent the second transactional register state. Signal delivery 'treclaim's to capture both register states, so signals abort transactions. The usual ucontext_t passed to the signal handler represents the checkpointed/original register state; the signal appears to have arisen at 'tbegin+4'.”h]”hX¤Delivery of signals (both sync and async) during transactions provides a second thread state (ucontext/mcontext) to represent the second transactional register state. Signal delivery ‘treclaim’s to capture both register states, so signals abort transactions. The usual ucontext_t passed to the signal handler represents the checkpointed/original register state; the signal appears to have arisen at ‘tbegin+4’.”…””}”(hjGh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kdhj6h²hubhÌ)”}”(hX*If the sighandler ucontext has uc_link set, a second ucontext has been delivered. For future compatibility the MSR.TS field should be checked to determine the transactional state -- if so, the second ucontext in uc->uc_link represents the active transactional registers at the point of the signal.”h]”hX*If the sighandler ucontext has uc_link set, a second ucontext has been delivered. For future compatibility the MSR.TS field should be checked to determine the transactional state -- if so, the second ucontext in uc->uc_link represents the active transactional registers at the point of the signal.”…””}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kkhj6h²hubhÌ)”}”(hŒsFor 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS field shows the transactional mode.”h]”hŒsFor 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS field shows the transactional mode.”…””}”(hjch²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kphj6h²hubhÌ)”}”(hŒßFor 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32 bits are stored in the MSR of the second ucontext, i.e. in uc->uc_link->uc_mcontext.regs->msr. The top word contains the transactional state TS.”h]”hŒáFor 32-bit processes, the mcontext’s MSR register is only 32 bits; the top 32 bits are stored in the MSR of the second ucontext, i.e. in uc->uc_link->uc_mcontext.regs->msr. The top word contains the transactional state TS.”…””}”(hjqh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kshj6h²hubhÌ)”}”(hŒŒHowever, basic signal handlers don't need to be aware of transactions and simply returning from the handler will deal with things correctly:”h]”hŒŽHowever, basic signal handlers don’t need to be aware of transactions and simply returning from the handler will deal with things correctly:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kxhj6h²hubhÌ)”}”(hŒßTransaction-aware signal handlers can read the transactional register state from the second ucontext. This will be necessary for crash handlers to determine, for example, the address of the instruction causing the SIGSEGV.”h]”hŒßTransaction-aware signal handlers can read the transactional register state from the second ucontext. This will be necessary for crash handlers to determine, for example, the address of the instruction causing the SIGSEGV.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K{hj6h²hubhÌ)”}”(hŒExample signal handler::”h]”hŒExample signal handler:”…””}”(hj›h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khj6h²hubj)”}”(hXÚ void crash_handler(int sig, siginfo_t *si, void *uc) { ucontext_t *ucp = uc; ucontext_t *transactional_ucp = ucp->uc_link; if (ucp_link) { u64 msr = ucp->uc_mcontext.regs->msr; /* May have transactional ucontext! */ #ifndef __powerpc64__ msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32; #endif if (MSR_TM_ACTIVE(msr)) { /* Yes, we crashed during a transaction. Oops. */ fprintf(stderr, "Transaction to be restarted at 0x%llx, but " "crashy instruction was at 0x%llx\n", ucp->uc_mcontext.regs->nip, transactional_ucp->uc_mcontext.regs->nip); } } fix_the_problem(ucp->dar); }”h]”hXÚ void crash_handler(int sig, siginfo_t *si, void *uc) { ucontext_t *ucp = uc; ucontext_t *transactional_ucp = ucp->uc_link; if (ucp_link) { u64 msr = ucp->uc_mcontext.regs->msr; /* May have transactional ucontext! */ #ifndef __powerpc64__ msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32; #endif if (MSR_TM_ACTIVE(msr)) { /* Yes, we crashed during a transaction. Oops. */ fprintf(stderr, "Transaction to be restarted at 0x%llx, but " "crashy instruction was at 0x%llx\n", ucp->uc_mcontext.regs->nip, transactional_ucp->uc_mcontext.regs->nip); } } fix_the_problem(ucp->dar); }”…””}”hj©sbah}”(h]”h ]”h"]”h$]”h&]”j&j'uh1jh³hÊh´Khj6h²hubhÌ)”}”(hX'When in an active transaction that takes a signal, we need to be careful with the stack. It's possible that the stack has moved back up after the tbegin. The obvious case here is when the tbegin is called inside a function that returns before a tend. In this case, the stack is part of the checkpointed transactional memory state. If we write over this non transactionally or in suspend, we are in trouble because if we get a tm abort, the program counter and stack pointer will be back at the tbegin but our in memory stack won't be valid anymore.”h]”hX+When in an active transaction that takes a signal, we need to be careful with the stack. It’s possible that the stack has moved back up after the tbegin. The obvious case here is when the tbegin is called inside a function that returns before a tend. In this case, the stack is part of the checkpointed transactional memory state. If we write over this non transactionally or in suspend, we are in trouble because if we get a tm abort, the program counter and stack pointer will be back at the tbegin but our in memory stack won’t be valid anymore.”…””}”(hj·h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K˜hj6h²hubhÌ)”}”(hXžTo avoid this, when taking a signal in an active transaction, we need to use the stack pointer from the checkpointed state, rather than the speculated state. This ensures that the signal context (written tm suspended) will be written below the stack required for the rollback. The transaction is aborted because of the treclaim, so any memory written between the tbegin and the signal will be rolled back anyway.”h]”hXžTo avoid this, when taking a signal in an active transaction, we need to use the stack pointer from the checkpointed state, rather than the speculated state. This ensures that the signal context (written tm suspended) will be written below the stack required for the rollback. The transaction is aborted because of the treclaim, so any memory written between the tbegin and the signal will be rolled back anyway.”…””}”(hjÅh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¡hj6h²hubhÌ)”}”(hŒ`For signals taken in non-TM or suspended mode, we use the normal/non-checkpointed stack pointer.”h]”hŒ`For signals taken in non-TM or suspended mode, we use the normal/non-checkpointed stack pointer.”…””}”(hjÓh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¨hj6h²hubhÌ)”}”(hŒ‰Any transaction initiated inside a sighandler and suspended on return from the sighandler to the kernel will get reclaimed and discarded.”h]”hŒ‰Any transaction initiated inside a sighandler and suspended on return from the sighandler to the kernel will get reclaimed and discarded.”…””}”(hjáh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K«hj6h²hubeh}”(h]”Œsignals”ah ]”h"]”Œsignals”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kbubh¶)”}”(hhh]”(h»)”}”(hŒ"Failure cause codes used by kernel”h]”hŒ"Failure cause codes used by kernel”…””}”(hjúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj÷h²hh³hÊh´K¯ubhÌ)”}”(hŒiThese are defined in , and distinguish different reasons why the kernel aborted a transaction:”h]”hŒiThese are defined in , and distinguish different reasons why the kernel aborted a transaction:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K±hj÷h²hubhŒ block_quote”“”)”}”(hXè====================== ================================ TM_CAUSE_RESCHED Thread was rescheduled. TM_CAUSE_TLBI Software TLB invalid. TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap. TM_CAUSE_SYSCALL Syscall from active transaction. TM_CAUSE_SIGNAL Signal delivered. TM_CAUSE_MISC Currently unused. TM_CAUSE_ALIGNMENT Alignment fault. TM_CAUSE_EMULATE Emulation that touched memory. ====================== ================================ ”h]”hŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1j&hj#ubj')”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K uh1j&hj#ubhŒtbody”“”)”}”(hhh]”(hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”hÌ)”}”(hŒTM_CAUSE_RESCHED”h]”hŒTM_CAUSE_RESCHED”…””}”(hjKh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KµhjHubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjCubjG)”}”(hhh]”hÌ)”}”(hŒThread was rescheduled.”h]”hŒThread was rescheduled.”…””}”(hjbh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kµhj_ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjCubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒ TM_CAUSE_TLBI”h]”hŒ TM_CAUSE_TLBI”…””}”(hj‚h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¶hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhj|ubjG)”}”(hhh]”hÌ)”}”(hŒSoftware TLB invalid.”h]”hŒSoftware TLB invalid.”…””}”(hj™h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¶hj–ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhj|ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒTM_CAUSE_FAC_UNAV”h]”hŒTM_CAUSE_FAC_UNAV”…””}”(hj¹h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K·hj¶ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhj³ubjG)”}”(hhh]”hÌ)”}”(hŒFP/VEC/VSX unavailable trap.”h]”hŒFP/VEC/VSX unavailable trap.”…””}”(hjÐh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K·hjÍubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhj³ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒTM_CAUSE_SYSCALL”h]”hŒTM_CAUSE_SYSCALL”…””}”(hjðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¸hjíubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjêubjG)”}”(hhh]”hÌ)”}”(hŒ Syscall from active transaction.”h]”hŒ Syscall from active transaction.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¸hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjêubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒTM_CAUSE_SIGNAL”h]”hŒTM_CAUSE_SIGNAL”…””}”(hj'h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¹hj$ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhj!ubjG)”}”(hhh]”hÌ)”}”(hŒSignal delivered.”h]”hŒSignal delivered.”…””}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¹hj;ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhj!ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒ TM_CAUSE_MISC”h]”hŒ TM_CAUSE_MISC”…””}”(hj^h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kºhj[ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjXubjG)”}”(hhh]”hÌ)”}”(hŒCurrently unused.”h]”hŒCurrently unused.”…””}”(hjuh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kºhjrubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjXubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒTM_CAUSE_ALIGNMENT”h]”hŒTM_CAUSE_ALIGNMENT”…””}”(hj•h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K»hj’ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjubjG)”}”(hhh]”hÌ)”}”(hŒAlignment fault.”h]”hŒAlignment fault.”…””}”(hj¬h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K»hj©ubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubjB)”}”(hhh]”(jG)”}”(hhh]”hÌ)”}”(hŒTM_CAUSE_EMULATE”h]”hŒTM_CAUSE_EMULATE”…””}”(hjÌh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¼hjÉubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjÆubjG)”}”(hhh]”hÌ)”}”(hŒEmulation that touched memory.”h]”hŒEmulation that touched memory.”…””}”(hjãh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¼hjàubah}”(h]”h ]”h"]”h$]”h&]”uh1jFhjÆubeh}”(h]”h ]”h"]”h$]”h&]”uh1jAhj>ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j<hj#ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1j!hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÊh´K´hj÷h²hubhÌ)”}”(hŒèThese can be checked by the user program's abort handler as TEXASR[0:7]. If bit 7 is set, it indicates that the error is considered persistent. For example a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.”h]”hŒêThese can be checked by the user program’s abort handler as TEXASR[0:7]. If bit 7 is set, it indicates that the error is considered persistent. For example a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¿hj÷h²hubeh}”(h]”Œ"failure-cause-codes-used-by-kernel”ah ]”h"]”Œ"failure cause codes used by kernel”ah$]”h&]”uh1hµhh·h²hh³hÊh´K¯ubh¶)”}”(hhh]”(h»)”}”(hŒGDB”h]”hŒGDB”…””}”(hj/h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj,h²hh³hÊh´KÄubhÌ)”}”(hX GDB and ptrace are not currently TM-aware. If one stops during a transaction, it looks like the transaction has just started (the checkpointed state is presented). The transaction cannot then be continued and will take the failure handler route. Furthermore, the transactional 2nd register state will be inaccessible. GDB can currently be used on programs using TM, but not sensibly in parts within transactions.”h]”hX GDB and ptrace are not currently TM-aware. If one stops during a transaction, it looks like the transaction has just started (the checkpointed state is presented). The transaction cannot then be continued and will take the failure handler route. Furthermore, the transactional 2nd register state will be inaccessible. GDB can currently be used on programs using TM, but not sensibly in parts within transactions.”…””}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÆhj,h²hubeh}”(h]”Œgdb”ah ]”h"]”Œgdb”ah$]”h&]”uh1hµhh·h²hh³hÊh´KÄubh¶)”}”(hhh]”(h»)”}”(hŒPOWER9”h]”hŒPOWER9”…””}”(hjVh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjSh²hh³hÊh´KÎubhÌ)”}”(hŒdTM on POWER9 has issues with storing the complete register state. This is described in this commit::”h]”hŒcTM on POWER9 has issues with storing the complete register state. This is described in this commit:”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÐhjSh²hubj)”}”(hŒÆcommit 4bb3c7a0208fc13ca70598efd109901a7cd45ae7 Author: Paul Mackerras Date: Wed Mar 21 21:32:01 2018 +1100 KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9”h]”hŒÆcommit 4bb3c7a0208fc13ca70598efd109901a7cd45ae7 Author: Paul Mackerras Date: Wed Mar 21 21:32:01 2018 +1100 KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9”…””}”hjrsbah}”(h]”h ]”h"]”h$]”h&]”j&j'uh1jh³hÊh´KÓhjSh²hubhÌ)”}”(hŒMTo account for this different POWER9 chips have TM enabled in different ways.”h]”hŒMTo account for this different POWER9 chips have TM enabled in different ways.”…””}”(hj€h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KØhjSh²hubhÌ)”}”(hŒTOn POWER9N DD2.01 and below, TM is disabled. ie HWCAP2[PPC_FEATURE2_HTM] is not set.”h]”hŒTOn POWER9N DD2.01 and below, TM is disabled. ie HWCAP2[PPC_FEATURE2_HTM] is not set.”…””}”(hjŽh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÛhjSh²hubhÌ)”}”(hXOn POWER9N DD2.1 TM is configured by firmware to always abort a transaction when tm suspend occurs. So tsuspend will cause a transaction to be aborted and rolled back. Kernel exceptions will also cause the transaction to be aborted and rolled back and the exception will not occur. If userspace constructs a sigcontext that enables TM suspend, the sigcontext will be rejected by the kernel. This mode is advertised to users with HWCAP2[PPC_FEATURE2_HTM_NO_SUSPEND] set. HWCAP2[PPC_FEATURE2_HTM] is not set in this mode.”h]”hXOn POWER9N DD2.1 TM is configured by firmware to always abort a transaction when tm suspend occurs. So tsuspend will cause a transaction to be aborted and rolled back. Kernel exceptions will also cause the transaction to be aborted and rolled back and the exception will not occur. If userspace constructs a sigcontext that enables TM suspend, the sigcontext will be rejected by the kernel. This mode is advertised to users with HWCAP2[PPC_FEATURE2_HTM_NO_SUSPEND] set. HWCAP2[PPC_FEATURE2_HTM] is not set in this mode.”…””}”(hjœh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÞhjSh²hubhÌ)”}”(hX#On POWER9N DD2.2 and above, KVM and POWERVM emulate TM for guests (as described in commit 4bb3c7a0208f), hence TM is enabled for guests ie. HWCAP2[PPC_FEATURE2_HTM] is set for guest userspace. Guests that makes heavy use of TM suspend (tsuspend or kernel suspend) will result in traps into the hypervisor and hence will suffer a performance degradation. Host userspace has TM disabled ie. HWCAP2[PPC_FEATURE2_HTM] is not set. (although we make enable it at some point in the future if we bring the emulation into host userspace context switching).”h]”hX#On POWER9N DD2.2 and above, KVM and POWERVM emulate TM for guests (as described in commit 4bb3c7a0208f), hence TM is enabled for guests ie. HWCAP2[PPC_FEATURE2_HTM] is set for guest userspace. Guests that makes heavy use of TM suspend (tsuspend or kernel suspend) will result in traps into the hypervisor and hence will suffer a performance degradation. Host userspace has TM disabled ie. HWCAP2[PPC_FEATURE2_HTM] is not set. (although we make enable it at some point in the future if we bring the emulation into host userspace context switching).”…””}”(hjªh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KçhjSh²hubhÌ)”}”(hŒ”POWER9C DD1.2 and above are only available with POWERVM and hence Linux only runs as a guest. On these systems TM is emulated like on POWER9N DD2.2.”h]”hŒ”POWER9C DD1.2 and above are only available with POWERVM and hence Linux only runs as a guest. On these systems TM is emulated like on POWER9N DD2.2.”…””}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KñhjSh²hubhÌ)”}”(hŒÉGuest migration from POWER8 to POWER9 will work with POWER9N DD2.2 and POWER9C DD1.2. Since earlier POWER9 processors don't support TM emulation, migration from POWER8 to POWER9 is not supported there.”h]”hŒËGuest migration from POWER8 to POWER9 will work with POWER9N DD2.2 and POWER9C DD1.2. Since earlier POWER9 processors don’t support TM emulation, migration from POWER8 to POWER9 is not supported there.”…””}”(hjÆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KõhjSh²hubeh}”(h]”Œpower9”ah ]”h"]”Œpower9”ah$]”h&]”uh1hµhh·h²hh³hÊh´KÎubh¶)”}”(hhh]”(h»)”}”(hŒKernel implementation”h]”hŒKernel implementation”…””}”(hjßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÜh²hh³hÊh´Kúubh¶)”}”(hhh]”(h»)”}”(hŒh/rfid mtmsrd quirk”h]”hŒh/rfid mtmsrd quirk”…””}”(hjðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjíh²hh³hÊh´KýubhÌ)”}”(hXˆAs defined in the ISA, rfid has a quirk which is useful in early exception handling. When in a userspace transaction and we enter the kernel via some exception, MSR will end up as TM=0 and TS=01 (ie. TM off but TM suspended). Regularly the kernel will want change bits in the MSR and will perform an rfid to do this. In this case rfid can have SRR0 TM = 0 and TS = 00 (ie. TM off and non transaction) and the resulting MSR will retain TM = 0 and TS=01 from before (ie. stay in suspend). This is a quirk in the architecture as this would normally be a transition from TS=01 to TS=00 (ie. suspend -> non transactional) which is an illegal transition.”h]”hXˆAs defined in the ISA, rfid has a quirk which is useful in early exception handling. When in a userspace transaction and we enter the kernel via some exception, MSR will end up as TM=0 and TS=01 (ie. TM off but TM suspended). Regularly the kernel will want change bits in the MSR and will perform an rfid to do this. In this case rfid can have SRR0 TM = 0 and TS = 00 (ie. TM off and non transaction) and the resulting MSR will retain TM = 0 and TS=01 from before (ie. stay in suspend). This is a quirk in the architecture as this would normally be a transition from TS=01 to TS=00 (ie. suspend -> non transactional) which is an illegal transition.”…””}”(hjþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kÿhjíh²hubhÌ)”}”(hŒTThis quirk is described the architecture in the definition of rfid with these lines:”h]”hŒTThis quirk is described the architecture in the definition of rfid with these lines:”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M hjíh²hubj)”}”(hŒRif (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then MSR 29:31 <- SRR1 29:31 ”h]”hŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒOif (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then MSR 29:31 <- SRR1 29:31 ”h]”(hŒterm”“”)”}”(hŒ6if (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then”h]”hŒ6if (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then”…””}”(hj+h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)h³hÊh´Mhj%ubhŒ definition”“”)”}”(hhh]”hÌ)”}”(hŒMSR 29:31 <- SRR1 29:31”h]”hŒMSR 29:31 <- SRR1 29:31”…””}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj;ubah}”(h]”h ]”h"]”h$]”h&]”uh1j9hj%ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j#h³hÊh´Mhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÊh´M hjíh²hubhÌ)”}”(hŒ%hrfid and mtmsrd have the same quirk.”h]”hŒ%hrfid and mtmsrd have the same quirk.”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhjíh²hubhÌ)”}”(hŒAThe Linux kernel uses this quirk in its early exception handling.”h]”hŒAThe Linux kernel uses this quirk in its early exception handling.”…””}”(hjrh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhjíh²hubeh}”(h]”Œh-rfid-mtmsrd-quirk”ah ]”h"]”Œh/rfid mtmsrd quirk”ah$]”h&]”uh1hµhjÜh²hh³hÊh´Kýubeh}”(h]”Œkernel-implementation”ah ]”h"]”Œkernel implementation”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kúubeh}”(h]”Œtransactional-memory-support”ah ]”h"]”Œtransactional memory support”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”jFŒfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jºŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j•j’jkjhjðjíj3j0jôjñj)j&jPjMjÙjÖjjŠj…j‚uŒ nametypes”}”(j•‰jk‰jð‰j3‰jô‰j)‰jP‰jÙ‰j‰j…‰uh}”(j’h·jhhéjíjnj0jójñj6j&j÷jMj,jÖjSjŠjÜj‚jíuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.