2sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget,/translations/zh_CN/arch/powerpc/papr_hcallsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/zh_TW/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/it_IT/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ja_JP/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ko_KR/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/sp_SP/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhF/var/lib/git/docbuild/linux/Documentation/arch/powerpc/papr_hcalls.rsthKubhsection)}(hhh](htitle)}(hHypercall Op-codes (hcalls)h]hHypercall Op-codes (hcalls)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXVirtualization on 64-bit Power Book3S Platforms is based on the PAPR specification [1]_ which describes the run-time environment for a guest operating system and how it should interact with the hypervisor for privileged operations. Currently there are two PAPR compliant hypervisors:h](hSVirtualization on 64-bit Power Book3S Platforms is based on the PAPR specification }(hhhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hhhhhNhNubah}(h]id1ah ]h"]h$]h&]refidid9docnamearch/powerpc/papr_hcallsuh1hhh܌resolvedKubh which describes the run-time environment for a guest operating system and how it should interact with the hypervisor for privileged operations. Currently there are two PAPR compliant hypervisors:}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh bullet_list)}(hhh](h list_item)}(h**IBM PowerVM (PHYP)**: IBM's proprietary hypervisor that supports AIX, IBM-i and Linux as supported guests (termed as Logical Partitions or LPARS). It supports the full PAPR specification. h]h)}(h**IBM PowerVM (PHYP)**: IBM's proprietary hypervisor that supports AIX, IBM-i and Linux as supported guests (termed as Logical Partitions or LPARS). It supports the full PAPR specification.h](hstrong)}(h**IBM PowerVM (PHYP)**h]hIBM PowerVM (PHYP)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: IBM’s proprietary hypervisor that supports AIX, IBM-i and Linux as supported guests (termed as Logical Partitions or LPARS). It supports the full PAPR specification.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j hjhhhhhNubj )}(h**Qemu/KVM**: Supports PPC64 linux guests running on a PPC64 linux host. Though it only implements a subset of PAPR specification called LoPAPR [2]_. h]h)}(h**Qemu/KVM**: Supports PPC64 linux guests running on a PPC64 linux host. Though it only implements a subset of PAPR specification called LoPAPR [2]_.h](j)}(h **Qemu/KVM**h]hQemu/KVM}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubh: Supports PPC64 linux guests running on a PPC64 linux host. Though it only implements a subset of PAPR specification called LoPAPR }(hj7hhhNhNubh)}(h[2]_h]h2}(hjMhhhNhNubah}(h]id2ah ]h"]h$]h&]hid10hhuh1hhj7hKubh.}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj3ubah}(h]h ]h"]h$]h&]uh1j hjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKhhhhubh)}(hX5On PPC64 arch a guest kernel running on top of a PAPR hypervisor is called a *pSeries guest*. A pseries guest runs in a supervisor mode (HV=0) and must issue hypercalls to the hypervisor whenever it needs to perform an action that is hypervisor privileged [3]_ or for other services managed by the hypervisor.h](hMOn PPC64 arch a guest kernel running on top of a PAPR hypervisor is called a }(hjuhhhNhNubhemphasis)}(h*pSeries guest*h]h pSeries guest}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjuubh. A pseries guest runs in a supervisor mode (HV=0) and must issue hypercalls to the hypervisor whenever it needs to perform an action that is hypervisor privileged }(hjuhhhNhNubh)}(h[3]_h]h3}(hjhhhNhNubah}(h]id3ah ]h"]h$]h&]hid11hhuh1hhjuhKubh1 or for other services managed by the hypervisor.}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX:Hence a Hypercall (hcall) is essentially a request by the pseries guest asking hypervisor to perform a privileged operation on behalf of the guest. The guest issues a with necessary input operands. The hypervisor after performing the privilege operation returns a status code and output operands back to the guest.h]hX:Hence a Hypercall (hcall) is essentially a request by the pseries guest asking hypervisor to perform a privileged operation on behalf of the guest. The guest issues a with necessary input operands. The hypervisor after performing the privilege operation returns a status code and output operands back to the guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h HCALL ABIh]h HCALL ABI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK#ubh)}(hXThe ABI specification for a hcall between a pseries guest and PAPR hypervisor is covered in section 14.5.3 of ref [2]_. Switch to the Hypervisor context is done via the instruction **HVCS** that expects the Opcode for hcall is set in *r3* and any in-arguments for the hcall are provided in registers *r4-r12*. If values have to be passed through a memory buffer, the data stored in that buffer should be in Big-endian byte order.h](hrThe ABI specification for a hcall between a pseries guest and PAPR hypervisor is covered in section 14.5.3 of ref }(hjhhhNhNubh)}(h[2]_h]h2}(hjhhhNhNubah}(h]id4ah ]h"]h$]h&]hj\hhuh1hhjhKubh@. Switch to the Hypervisor context is done via the instruction }(hjhhhNhNubj)}(h**HVCS**h]hHVCS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh- that expects the Opcode for hcall is set in }(hjhhhNhNubj~)}(h*r3*h]hr3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh> and any in-arguments for the hcall are provided in registers }(hjhhhNhNubj~)}(h*r4-r12*h]hr4-r12}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubhy. If values have to be passed through a memory buffer, the data stored in that buffer should be in Big-endian byte order.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK$hjhhubh)}(hX4Once control returns back to the guest after hypervisor has serviced the 'HVCS' instruction the return value of the hcall is available in *r3* and any out values are returned in registers *r4-r12*. Again like in case of in-arguments, any out values stored in a memory buffer will be in Big-endian byte order.h](hOnce control returns back to the guest after hypervisor has serviced the ‘HVCS’ instruction the return value of the hcall is available in }(hj)hhhNhNubj~)}(h*r3*h]hr3}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj)ubh. and any out values are returned in registers }(hj)hhhNhNubj~)}(h*r4-r12*h]hr4-r12}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj)ubhp. Again like in case of in-arguments, any out values stored in a memory buffer will be in Big-endian byte order.}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK+hjhhubh)}(hPowerpc arch code provides convenient wrappers named **plpar_hcall_xxx** defined in a arch specific header [4]_ to issue hcalls from the linux kernel running as pseries guest.h](h5Powerpc arch code provides convenient wrappers named }(hj[hhhNhNubj)}(h**plpar_hcall_xxx**h]hplpar_hcall_xxx}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubh# defined in a arch specific header }(hj[hhhNhNubh)}(h[4]_h]h4}(hjuhhhNhNubah}(h]id5ah ]h"]h$]h&]hid12hhuh1hhj[hKubh@ to issue hcalls from the linux kernel running as pseries guest.}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK0hjhhubeh}(h] hcall-abiah ]h"] hcall abiah$]h&]uh1hhhhhhhhK#ubh)}(hhh](h)}(hRegister Conventionsh]hRegister Conventions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK5ubh)}(hAny hcall should follow same register convention as described in section 2.2.1.1 of "64-Bit ELF V2 ABI Specification: Power Architecture"[5]_. Table below summarizes these conventions:h](hAny hcall should follow same register convention as described in section 2.2.1.1 of “64-Bit ELF V2 ABI Specification: Power Architecture”}(hjhhhNhNubh)}(h[5]_h]h5}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]hid13hhuh1hhjhKubh+. Table below summarizes these conventions:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK7hjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK+uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hRegister Rangeh]hRegister Range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK | | | User | +--+ DRC1 | | DRC | Space | | PAPR | Index +---------+ DR2 | Hypervisor | | | +--+ | | <-----> | Kernel | | | <----> | | Hcall | | +--+ DRC2 +------------+ +---------+h]hXDR1 Guest +--+ +------------+ +---------+ | | <----> | | | User | +--+ DRC1 | | DRC | Space | | PAPR | Index +---------+ DR2 | Hypervisor | | | +--+ | | <-----> | Kernel | | | <----> | | Hcall | | +--+ DRC2 +------------+ +---------+}hjHsbah}(h]h ]h"]h$]h&]hhuh1jFhhhKehj5hhubh)}(hXPAPR hypervisor terms shared hardware resources like PCI devices, NVDIMMs etc available for use by LPARs as Dynamic Resource (DR). When a DR is allocated to an LPAR, PHYP creates a data-structure called Dynamic Resource Connector (DRC) to manage LPAR access. An LPAR refers to a DRC via an opaque 32-bit number called DRC-Index. The DRC-index value is provided to the LPAR via device-tree where its present as an attribute in the device tree node associated with the DR.h]hXPAPR hypervisor terms shared hardware resources like PCI devices, NVDIMMs etc available for use by LPARs as Dynamic Resource (DR). When a DR is allocated to an LPAR, PHYP creates a data-structure called Dynamic Resource Connector (DRC) to manage LPAR access. An LPAR refers to a DRC via an opaque 32-bit number called DRC-Index. The DRC-index value is provided to the LPAR via device-tree where its present as an attribute in the device tree node associated with the DR.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohj5hhubeh}(h]drc-drc-indexesah ]h"]drc & drc indexesah$]h&]uh1hhhhhhhhKbubh)}(hhh](h)}(hHCALL Return-valuesh]hHCALL Return-values}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhhhhhKxubh)}(hAfter servicing the hcall, hypervisor sets the return-value in *r3* indicating success or failure of the hcall. In case of a failure an error code indicates the cause for error. These codes are defined and documented in arch specific header [4]_.h](h?After servicing the hcall, hypervisor sets the return-value in }(hj}hhhNhNubj~)}(h*r3*h]hr3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj}ubh indicating success or failure of the hcall. In case of a failure an error code indicates the cause for error. These codes are defined and documented in arch specific header }(hj}hhhNhNubh)}(h[4]_h]h4}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]hjhhuh1hhj}hKubh.}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhjlhhubh)}(hXHIn some cases a hcall can potentially take a long time and need to be issued multiple times in order to be completely serviced. These hcalls will usually accept an opaque value *continue-token* within there argument list and a return value of *H_CONTINUE* indicates that hypervisor hasn't still finished servicing the hcall yet.h](hIn some cases a hcall can potentially take a long time and need to be issued multiple times in order to be completely serviced. These hcalls will usually accept an opaque value }(hjhhhNhNubj~)}(h*continue-token*h]hcontinue-token}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh2 within there argument list and a return value of }(hjhhhNhNubj~)}(h *H_CONTINUE*h]h H_CONTINUE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubhK indicates that hypervisor hasn’t still finished servicing the hcall yet.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjlhhubh)}(hTo make such hcalls the guest need to set *continue-token == 0* for the initial call and use the hypervisor returned value of *continue-token* for each subsequent hcall until hypervisor returns a non *H_CONTINUE* return value.h](h*To make such hcalls the guest need to set }(hjhhhNhNubj~)}(h*continue-token == 0*h]hcontinue-token == 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh? for the initial call and use the hypervisor returned value of }(hjhhhNhNubj~)}(h*continue-token*h]hcontinue-token}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh: for each subsequent hcall until hypervisor returns a non }(hjhhhNhNubj~)}(h *H_CONTINUE*h]h H_CONTINUE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh return value.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjlhhubeh}(h]hcall-return-valuesah ]h"]hcall return-valuesah$]h&]uh1hhhhhhhhKxubh)}(hhh](h)}(hHCALL Op-codesh]hHCALL Op-codes}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. hhhhhKubh)}(hBelow is a partial list of HCALLs that are supported by PHYP. For the corresponding opcode values please look into the arch specific header [4]_:h](hBelow is a partial list of HCALLs that are supported by PHYP. For the corresponding opcode values please look into the arch specific header }(hj? hhhNhNubh)}(h[4]_h]h4}(hjG hhhNhNubah}(h]id8ah ]h"]h$]h&]hjhhuh1hhj? hKubh:}(hj? hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h**H_SCM_READ_METADATA**h]j)}(hjb h]hH_SCM_READ_METADATA}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj` ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh line_block)}(hhh](hh)}(h9Input: *drcIndex, offset, buffer-address, numBytesToRead*h](hInput: }(hj} hhhNhNubj~)}(h2*drcIndex, offset, buffer-address, numBytesToRead*h]h0drcIndex, offset, buffer-address, numBytesToRead}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj} ubeh}(h]h ]h"]h$]h&]uh1hindentKhjy hhhhhKubj| )}(hOut: *numBytesRead*h](hOut: }(hj hhhNhNubj~)}(h*numBytesRead*h]h numBytesRead}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khjy hhhhhKubj| )}(h>Return Value: *H_Success, H_Parameter, H_P2, H_P3, H_Hardware*h](hReturn Value: }(hj hhhNhNubj~)}(h0*H_Success, H_Parameter, H_P2, H_P3, H_Hardware*h]h.H_Success, H_Parameter, H_P2, H_P3, H_Hardware}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khjy hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(hXZGiven a DRC Index of an NVDIMM, read N-bytes from the metadata area associated with it, at a specified offset and copy it to provided buffer. The metadata area stores configuration information such as label information, bad-blocks etc. The metadata area is located out-of-band of NVDIMM storage area hence a separate access semantics is provided.h]hXZGiven a DRC Index of an NVDIMM, read N-bytes from the metadata area associated with it, at a specified offset and copy it to provided buffer. The metadata area stores configuration information such as label information, bad-blocks etc. The metadata area is located out-of-band of NVDIMM storage area hence a separate access semantics is provided.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h**H_SCM_WRITE_METADATA**h]j)}(hj h]hH_SCM_WRITE_METADATA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubjx )}(hhh](j| )}(h0Input: *drcIndex, offset, data, numBytesToWrite*h](hInput: }(hj hhhNhNubj~)}(h)*drcIndex, offset, data, numBytesToWrite*h]h'drcIndex, offset, data, numBytesToWrite}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h Out: *None*h](hOut: }(hj hhhNhNubj~)}(h*None*h]hNone}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h>Return Value: *H_Success, H_Parameter, H_P2, H_P4, H_Hardware*h](hReturn Value: }(hj8 hhhNhNubj~)}(h0*H_Success, H_Parameter, H_P2, H_P4, H_Hardware*h]h.H_Success, H_Parameter, H_P2, H_P4, H_Hardware}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj8 ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(hGiven a DRC Index of an NVDIMM, write N-bytes to the metadata area associated with it, at the specified offset and from the provided buffer.h]hGiven a DRC Index of an NVDIMM, write N-bytes to the metadata area associated with it, at the specified offset and from the provided buffer.}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h**H_SCM_BIND_MEM**h]j)}(hjj h]hH_SCM_BIND_MEM}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjh ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubjx )}(hhh](j| )}(h=Input: *drcIndex, startingScmBlockIndex, numScmBlocksToBind,*h](hInput: }(hj hhhNhNubj~)}(h6*drcIndex, startingScmBlockIndex, numScmBlocksToBind,*h]h4drcIndex, startingScmBlockIndex, numScmBlocksToBind,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h,*targetLogicalMemoryAddress, continue-token*h]j~)}(hj h]h*targetLogicalMemoryAddress, continue-token}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(hFOut: *continue-token, targetLogicalMemoryAddress, numScmBlocksToBound*h](hOut: }(hj hhhNhNubj~)}(hA*continue-token, targetLogicalMemoryAddress, numScmBlocksToBound*h]h?continue-token, targetLogicalMemoryAddress, numScmBlocksToBound}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(hDReturn Value: *H_Success, H_Parameter, H_P2, H_P3, H_P4, H_Overlap,*h](hReturn Value: }(hj hhhNhNubj~)}(h6*H_Success, H_Parameter, H_P2, H_P3, H_P4, H_Overlap,*h]h4H_Success, H_Parameter, H_P2, H_P3, H_P4, H_Overlap,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h*H_Too_Big, H_P5, H_Busy*h]j~)}(hj h]hH_Too_Big, H_P5, H_Busy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(hXGiven a DRC-Index of an NVDIMM, map a continuous SCM blocks range *(startingScmBlockIndex, startingScmBlockIndex+numScmBlocksToBind)* to the guest at *targetLogicalMemoryAddress* within guest physical address space. In case *targetLogicalMemoryAddress == 0xFFFFFFFF_FFFFFFFF* then hypervisor assigns a target address to the guest. The HCALL can fail if the Guest has an active PTE entry to the SCM block being bound.h](hBGiven a DRC-Index of an NVDIMM, map a continuous SCM blocks range }(hj hhhNhNubj~)}(hC*(startingScmBlockIndex, startingScmBlockIndex+numScmBlocksToBind)*h]hA(startingScmBlockIndex, startingScmBlockIndex+numScmBlocksToBind)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubh to the guest at }(hj hhhNhNubj~)}(h*targetLogicalMemoryAddress*h]htargetLogicalMemoryAddress}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubh. within guest physical address space. In case }(hj hhhNhNubj~)}(h3*targetLogicalMemoryAddress == 0xFFFFFFFF_FFFFFFFF*h]h1targetLogicalMemoryAddress == 0xFFFFFFFF_FFFFFFFF}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubh then hypervisor assigns a target address to the guest. The HCALL can fail if the Guest has an active PTE entry to the SCM block being bound.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h**H_SCM_UNBIND_MEM** | Input: drcIndex, startingScmLogicalMemoryAddress, numScmBlocksToUnbind | Out: numScmBlocksUnbound | Return Value: *H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Overlap,* | *H_Busy, H_LongBusyOrder1mSec, H_LongBusyOrder10mSec*h](j)}(h**H_SCM_UNBIND_MEM**h]hH_SCM_UNBIND_MEM}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN ubhu | Input: drcIndex, startingScmLogicalMemoryAddress, numScmBlocksToUnbind | Out: numScmBlocksUnbound | Return Value: }(hjN hhhNhNubj~)}(h:*H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Overlap,*h]h8H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Overlap,}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjN ubh | }(hjN hhhNhNubj~)}(h5*H_Busy, H_LongBusyOrder1mSec, H_LongBusyOrder10mSec*h]h3H_Busy, H_LongBusyOrder1mSec, H_LongBusyOrder10mSec}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjN ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(hGiven a DRC-Index of an NVDimm, unmap *numScmBlocksToUnbind* SCM blocks starting at *startingScmLogicalMemoryAddress* from guest physical address space. The HCALL can fail if the Guest has an active PTE entry to the SCM block being unbound.h](h&Given a DRC-Index of an NVDimm, unmap }(hj hhhNhNubj~)}(h*numScmBlocksToUnbind*h]hnumScmBlocksToUnbind}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubh SCM blocks starting at }(hj hhhNhNubj~)}(h!*startingScmLogicalMemoryAddress*h]hstartingScmLogicalMemoryAddress}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubh{ from guest physical address space. The HCALL can fail if the Guest has an active PTE entry to the SCM block being unbound.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h!**H_SCM_QUERY_BLOCK_MEM_BINDING**h]j)}(hj h]hH_SCM_QUERY_BLOCK_MEM_BINDING}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubjx )}(hhh](j| )}(h Input: *drcIndex, scmBlockIndex*h](hInput: }(hj hhhNhNubj~)}(h*drcIndex, scmBlockIndex*h]hdrcIndex, scmBlockIndex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(hOut: *Guest-Physical-Address*h](hOut: }(hj hhhNhNubj~)}(h*Guest-Physical-Address*h]hGuest-Physical-Address}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h8Return Value: *H_Success, H_Parameter, H_P2, H_NotFound*h](hReturn Value: }(hj hhhNhNubj~)}(h**H_Success, H_Parameter, H_P2, H_NotFound*h]h(H_Success, H_Parameter, H_P2, H_NotFound}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(hoGiven a DRC-Index and an SCM Block index return the guest physical address to which the SCM block is mapped to.h]hoGiven a DRC-Index and an SCM Block index return the guest physical address to which the SCM block is mapped to.}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h#**H_SCM_QUERY_LOGICAL_MEM_BINDING**h]j)}(hj@ h]hH_SCM_QUERY_LOGICAL_MEM_BINDING}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj> ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubjx )}(hhh](j| )}(hInput: *Guest-Physical-Address*h](hInput: }(hjX hhhNhNubj~)}(h*Guest-Physical-Address*h]hGuest-Physical-Address}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjX ubeh}(h]h ]h"]h$]h&]uh1hj KhjU hhhhhKubj| )}(hOut: *drcIndex, scmBlockIndex*h](hOut: }(hjt hhhNhNubj~)}(h*drcIndex, scmBlockIndex*h]hdrcIndex, scmBlockIndex}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjt ubeh}(h]h ]h"]h$]h&]uh1hj KhjU hhhhhKubj| )}(h8Return Value: *H_Success, H_Parameter, H_P2, H_NotFound*h](hReturn Value: }(hj hhhNhNubj~)}(h**H_Success, H_Parameter, H_P2, H_NotFound*h]h(H_Success, H_Parameter, H_P2, H_NotFound}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj KhjU hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(h^Given a guest physical address return which DRC Index and SCM block is mapped to that address.h]h^Given a guest physical address return which DRC Index and SCM block is mapped to that address.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h**H_SCM_UNBIND_ALL**h]j)}(hj h]hH_SCM_UNBIND_ALL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubjx )}(hhh](j| )}(h!Input: *scmTargetScope, drcIndex*h](hInput: }(hj hhhNhNubj~)}(h*scmTargetScope, drcIndex*h]hscmTargetScope, drcIndex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h Out: *None*h](hOut: }(hj hhhNhNubj~)}(h*None*h]hNone}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(hEReturn Value: *H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Busy,*h](hReturn Value: }(hj hhhNhNubj~)}(h7*H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Busy,*h]h5H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Busy,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj| )}(h-*H_LongBusyOrder1mSec, H_LongBusyOrder10mSec*h]j~)}(hj0 h]h+H_LongBusyOrder1mSec, H_LongBusyOrder10mSec}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj. ubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(hDepending on the Target scope unmap all SCM blocks belonging to all NVDIMMs or all SCM blocks belonging to a single NVDIMM identified by its drcIndex from the LPAR memory.h]hDepending on the Target scope unmap all SCM blocks belonging to all NVDIMMs or all SCM blocks belonging to a single NVDIMM identified by its drcIndex from the LPAR memory.}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(h**H_SCM_HEALTH**h]j)}(hj[ h]h H_SCM_HEALTH}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY ubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubjx )}(hhh](j| )}(hInput: drcIndexh]hInput: drcIndex}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hj Khjp hhhhhKubj| )}(h7Out: *health-bitmap (r4), health-bit-valid-bitmap (r5)*h](hOut: }(hj hhhNhNubj~)}(h2*health-bitmap (r4), health-bit-valid-bitmap (r5)*h]h0health-bitmap (r4), health-bit-valid-bitmap (r5)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khjp hhhhhKubj| )}(h2Return Value: *H_Success, H_Parameter, H_Hardware*h](hReturn Value: }(hj hhhNhNubj~)}(h$*H_Success, H_Parameter, H_Hardware*h]h"H_Success, H_Parameter, H_Hardware}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj ubeh}(h]h ]h"]h$]h&]uh1hj Khjp hhhhhKubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhKubh)}(hXGiven a DRC Index return the info on predictive failure and overall health of the PMEM device. The asserted bits in the health-bitmap indicate one or more states (described in table below) of the PMEM device and health-bit-valid-bitmap indicate which bits in health-bitmap are valid. The bits are reported in reverse bit ordering for example a value of 0xC400000000000000 indicates bits 0, 1, and 5 are valid.h]hXGiven a DRC Index return the info on predictive failure and overall health of the PMEM device. The asserted bits in the health-bitmap indicate one or more states (described in table below) of the PMEM device and health-bit-valid-bitmap indicate which bits in health-bitmap are valid. The bits are reported in reverse bit ordering for example a value of 0xC400000000000000 indicates bits 0, 1, and 5 are valid.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubh)}(hHealth Bitmap Flags:h]hHealth Bitmap Flags:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. hhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKGuh1jhj ubj)}(hhh]j)}(hhh](j)}(hhh]h)}(hBith]hBit}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Definitionh]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubjR)}(hhh](j)}(hhh](j)}(hhh]h)}(h00h]h00}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj;ubah}(h]h ]h"]h$]h&]uh1jhj8ubj)}(hhh]h)}(hgPMEM device is unable to persist memory contents. If the system is powered down, nothing will be saved.h]hgPMEM device is unable to persist memory contents. If the system is powered down, nothing will be saved.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h01h]h01}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh]h)}(hPMEM device failed to persist memory contents. Either contents were not saved successfully on power down or were not restored properly on power up.h]hPMEM device failed to persist memory contents. Either contents were not saved successfully on power down or were not restored properly on power up.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h02h]h02}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hmPMEM device contents are persisted from previous IPL. The data from the last boot were successfully restored.h]hmPMEM device contents are persisted from previous IPL. The data from the last boot were successfully restored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h03h]h03}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjPMEM device contents are not persisted from previous IPL. There was no data to restore from the last boot.h]hjPMEM device contents are not persisted from previous IPL. There was no data to restore from the last boot.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h04h]h04}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h3PMEM device memory life remaining is critically lowh]h3PMEM device memory life remaining is critically low}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h05h]h05}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1jhjKubj)}(hhh]h)}(h6PMEM device will be garded off next IPL due to failureh]h6PMEM device will be garded off next IPL due to failure}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h06h]h06}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMEM device contents cannot persist due to current platform health status. A hardware failure may prevent data from being saved or restored.h]hPMEM device contents cannot persist due to current platform health status. A hardware failure may prevent data from being saved or restored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h07h]h07}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFPMEM device is unable to persist memory contents in certain conditionsh]hFPMEM device is unable to persist memory contents in certain conditions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h08h]h08}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMEM device is encryptedh]hPMEM device is encrypted}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h09h]h09}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(hhh]h)}(hSPMEM device has successfully completed a requested erase or secure erase procedure.h]hSPMEM device has successfully completed a requested erase or secure erase procedure.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h10:63h]h10:63}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjaubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hhh]h)}(hReserved / Unusedh]hReserved / Unused}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjxubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jQhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj. hhhhhNubh)}(h**H_SCM_PERFORMANCE_STATS**h]j)}(hjh]hH_SCM_PERFORMANCE_STATS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM hj. hhubjx )}(hhh](j| )}(h"Input: drcIndex, resultBuffer Addrh]h"Input: drcIndex, resultBuffer Addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMubj| )}(h Out: Noneh]h Out: None}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMubj| )}(h\Return Value: *H_Success, H_Parameter, H_Unsupported, H_Hardware, H_Authority, H_Privilege*h](hReturn Value: }(hjhhhNhNubj~)}(hM*H_Success, H_Parameter, H_Unsupported, H_Hardware, H_Authority, H_Privilege*h]hKH_Success, H_Parameter, H_Unsupported, H_Hardware, H_Authority, H_Privilege}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhMubh)}(hbGiven a DRC Index collect the performance statistics for NVDIMM and copy them to the resultBuffer.h]hbGiven a DRC Index collect the performance statistics for NVDIMM and copy them to the resultBuffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj. hhubh)}(h**H_SCM_FLUSH**h]j)}(hjh]h H_SCM_FLUSH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhj. hhubjx )}(hhh](j| )}(h!Input: *drcIndex, continue-token*h](hInput: }(hj(hhhNhNubj~)}(h*drcIndex, continue-token*h]hdrcIndex, continue-token}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj(ubeh}(h]h ]h"]h$]h&]uh1hj Khj%hhhhhMubj| )}(hOut: *continue-token*h](hOut: }(hjDhhhNhNubj~)}(h*continue-token*h]hcontinue-token}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjDubeh}(h]h ]h"]h$]h&]uh1hj Khj%hhhhhMubj| )}(h4Return Value: *H_SUCCESS, H_Parameter, H_P2, H_BUSY*h](hReturn Value: }(hj`hhhNhNubj~)}(h&*H_SUCCESS, H_Parameter, H_P2, H_BUSY*h]h$H_SUCCESS, H_Parameter, H_P2, H_BUSY}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hj`ubeh}(h]h ]h"]h$]h&]uh1hj Khj%hhhhhMubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhMubh)}(h:Given a DRC Index Flush the data to backend NVDIMM device.h]h:Given a DRC Index Flush the data to backend NVDIMM device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj. hhubh)}(hXiThe hcall returns H_BUSY when the flush takes longer time and the hcall needs to be issued multiple times in order to be completely serviced. The *continue-token* from the output to be passed in the argument list of subsequent hcalls to the hypervisor until the hcall is completely serviced at which point H_SUCCESS or other error is returned by the hypervisor.h](hThe hcall returns H_BUSY when the flush takes longer time and the hcall needs to be issued multiple times in order to be completely serviced. The }(hjhhhNhNubj~)}(h*continue-token*h]hcontinue-token}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubh from the output to be passed in the argument list of subsequent hcalls to the hypervisor until the hcall is completely serviced at which point H_SUCCESS or other error is returned by the hypervisor.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj. hhubh)}(h **H_HTM**h]j)}(hjh]hH_HTM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM$hj. hhubjx )}(hhh](j| )}(hEInput: flags, target, operation (op), op-param1, op-param2, op-param3h]hEInput: flags, target, operation (op), op-param1, op-param2, op-param3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM&ubj| )}(hOut: *dumphtmbufferdata*h](hOut: }(hjhhhNhNubj~)}(h*dumphtmbufferdata*h]hdumphtmbufferdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM'ubj| )}(hReturn Value: *H_Success,H_Busy,H_LongBusyOrder,H_Partial,H_Parameter, H_P2,H_P3,H_P4,H_P5,H_P6,H_State,H_Not_Available,H_Authority*h](hReturn Value: }(hjhhhNhNubj~)}(hv*H_Success,H_Busy,H_LongBusyOrder,H_Partial,H_Parameter, H_P2,H_P3,H_P4,H_P5,H_P6,H_State,H_Not_Available,H_Authority*h]htH_Success,H_Busy,H_LongBusyOrder,H_Partial,H_Parameter, H_P2,H_P3,H_P4,H_P5,H_P6,H_State,H_Not_Available,H_Authority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j}hjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM)ubeh}(h]h ]h"]h$]h&]uh1jw hj. hhhhhM&ubh)}(hH_HTM supports setup, configuration, control and dumping of Hardware Trace Macro (HTM) function and its data. HTM buffer stores tracing data for functions like core instruction, core LLAT and nest.h]hH_HTM supports setup, configuration, control and dumping of Hardware Trace Macro (HTM) function and its data. HTM buffer stores tracing data for functions like core instruction, core LLAT and nest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj. hhubeh}(h]hcall-op-codesah ]h"]hcall op-codesah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Referencesh]h References}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhhhM0ubhfootnote)}(hk"Power Architecture Platform Reference" https://en.wikipedia.org/wiki/Power_Architecture_Platform_Referenceh](hlabel)}(h1h]h1}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jChj?ubh)}(hk"Power Architecture Platform Reference" https://en.wikipedia.org/wiki/Power_Architecture_Platform_Referenceh](h,“Power Architecture Platform Reference” }(hjShhhNhNubh reference)}(hChttps://en.wikipedia.org/wiki/Power_Architecture_Platform_Referenceh]hChttps://en.wikipedia.org/wiki/Power_Architecture_Platform_Reference}(hj]hhhNhNubah}(h]h ]h"]h$]h&]refurij_uh1j[hjSubeh}(h]h ]h"]h$]h&]uh1hhhhM1hj?ubeh}(h]hah ]h"]1ah$]h&]hahhuh1j=hhhM1hj,hhhKubj>)}(hh"Linux on Power Architecture Platform Reference" https://members.openpowerfoundation.org/document/dl/469h](jD)}(h2h]h2}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jChjyubh)}(hh"Linux on Power Architecture Platform Reference" https://members.openpowerfoundation.org/document/dl/469h](h5“Linux on Power Architecture Platform Reference” }(hjhhhNhNubj\)}(h7https://members.openpowerfoundation.org/document/dl/469h]h7https://members.openpowerfoundation.org/document/dl/469}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j[hjubeh}(h]h ]h"]h$]h&]uh1hhhhM3hjyubeh}(h]j\ah ]h"]2ah$]h&](jWjehhuh1j=hhhM3hj,hhhKubj>)}(hv"Definitions and Notation" Book III-Section 14.5.3 https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0h](jD)}(h3h]h3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh)}(hv"Definitions and Notation" Book III-Section 14.5.3 https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0h](h7“Definitions and Notation” Book III-Section 14.5.3 }(hjhhhNhNubj\)}(hChttps://openpowerfoundation.org/?resource_lib=power-isa-version-3-0h]hChttps://openpowerfoundation.org/?resource_lib=power-isa-version-3-0}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j[hjubeh}(h]h ]h"]h$]h&]uh1hhhhM5hjubeh}(h]jah ]h"]3ah$]h&]jahhuh1j=hhhM5hj,hhhKubj>)}(h!arch/powerpc/include/asm/hvcall.hh](jD)}(h4h]h4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh)}(hjh]h!arch/powerpc/include/asm/hvcall.h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjubeh}(h]jah ]h"]4ah$]h&](jjjQ ehhuh1j=hhhM7hj,hhhKubj>)}(h"64-Bit ELF V2 ABI Specification: Power Architecture" https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architectureh](jD)}(h5h]h5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChj ubh)}(h"64-Bit ELF V2 ABI Specification: Power Architecture" https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architectureh](h:“64-Bit ELF V2 ABI Specification: Power Architecture” }(hjhhhNhNubj\)}(h`https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architectureh]h`https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture}(hj%hhhNhNubah}(h]h ]h"]h$]h&]refurij'uh1j[hjubeh}(h]h ]h"]h$]h&]uh1hhhhM8hj ubeh}(h]jah ]h"]5ah$]h&]jahhuh1j=hhhM8hj,hhhKubeh}(h] referencesah ]h"] referencesah$]h&]uh1hhhhhhhhM0ubeh}(h]hypercall-op-codes-hcallsah ]h"]hypercall op-codes (hcalls)ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjserror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}(1]ha2](jMje3]ja4](jujjG e5]jaurefids}nameids}(jNjKjjjjj2j/jijfj+ j( j)j&jFjCjvhjj\jjjjj>ju nametypes}(jNjjj2jij+ j)jFjvjjjj>uh}(jKhjhhhjWjMjjjjjjjjuj/jjjjfj5j( jljjj&j. jQ jG jCj,hj?j\jyjjjjjj u footnote_refs}(j]haj](jMjej]jaj](jujjG ej]jau citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes](j?jyjjj e citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}jK sRparse_messages]transform_messages] transformerN include_log] decorationNhhub.