sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget,/translations/zh_CN/arch/powerpc/papr_hcallsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/zh_TW/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/it_IT/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ja_JP/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ko_KR/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/pt_BR/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/sp_SP/arch/powerpc/papr_hcallsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhF/var/lib/git/docbuild/linux/Documentation/arch/powerpc/papr_hcalls.rsthKubhsection)}(hhh](htitle)}(hHypercall Op-codes (hcalls)h]hHypercall Op-codes (hcalls)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXVirtualization on 64-bit Power Book3S Platforms is based on the PAPR specification [1]_ which describes the run-time environment for a guest operating system and how it should interact with the hypervisor for privileged operations. Currently there are two PAPR compliant hypervisors:h](hSVirtualization on 64-bit Power Book3S Platforms is based on the PAPR specification }(hhhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hhhhhNhNubah}(h]id1ah ]h"]h$]h&]refidid9docnamearch/powerpc/papr_hcallsuh1hhhresolvedKubh which describes the run-time environment for a guest operating system and how it should interact with the hypervisor for privileged operations. Currently there are two PAPR compliant hypervisors:}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh bullet_list)}(hhh](h list_item)}(h**IBM PowerVM (PHYP)**: IBM's proprietary hypervisor that supports AIX, IBM-i and Linux as supported guests (termed as Logical Partitions or LPARS). It supports the full PAPR specification. h]h)}(h**IBM PowerVM (PHYP)**: IBM's proprietary hypervisor that supports AIX, IBM-i and Linux as supported guests (termed as Logical Partitions or LPARS). It supports the full PAPR specification.h](hstrong)}(h**IBM PowerVM (PHYP)**h]hIBM PowerVM (PHYP)}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj#ubh: IBM’s proprietary hypervisor that supports AIX, IBM-i and Linux as supported guests (termed as Logical Partitions or LPARS). It supports the full PAPR specification.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h**Qemu/KVM**: Supports PPC64 linux guests running on a PPC64 linux host. Though it only implements a subset of PAPR specification called LoPAPR [2]_. h]h)}(h**Qemu/KVM**: Supports PPC64 linux guests running on a PPC64 linux host. Though it only implements a subset of PAPR specification called LoPAPR [2]_.h](j()}(h **Qemu/KVM**h]hQemu/KVM}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjKubh: Supports PPC64 linux guests running on a PPC64 linux host. Though it only implements a subset of PAPR specification called LoPAPR }(hjKhhhNhNubh)}(h[2]_h]h2}(hjahhhNhNubah}(h]id2ah ]h"]h$]h&]j id10j j uh1hhjKj Kubh.}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjGubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKhhhhubh)}(hX5On PPC64 arch a guest kernel running on top of a PAPR hypervisor is called a *pSeries guest*. A pseries guest runs in a supervisor mode (HV=0) and must issue hypercalls to the hypervisor whenever it needs to perform an action that is hypervisor privileged [3]_ or for other services managed by the hypervisor.h](hMOn PPC64 arch a guest kernel running on top of a PAPR hypervisor is called a }(hjhhhNhNubhemphasis)}(h*pSeries guest*h]h pSeries guest}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. A pseries guest runs in a supervisor mode (HV=0) and must issue hypercalls to the hypervisor whenever it needs to perform an action that is hypervisor privileged }(hjhhhNhNubh)}(h[3]_h]h3}(hjhhhNhNubah}(h]id3ah ]h"]h$]h&]j id11j j uh1hhjj Kubh1 or for other services managed by the hypervisor.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX:Hence a Hypercall (hcall) is essentially a request by the pseries guest asking hypervisor to perform a privileged operation on behalf of the guest. The guest issues a with necessary input operands. The hypervisor after performing the privilege operation returns a status code and output operands back to the guest.h]hX:Hence a Hypercall (hcall) is essentially a request by the pseries guest asking hypervisor to perform a privileged operation on behalf of the guest. The guest issues a with necessary input operands. The hypervisor after performing the privilege operation returns a status code and output operands back to the guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h HCALL ABIh]h HCALL ABI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK#ubh)}(hXThe ABI specification for a hcall between a pseries guest and PAPR hypervisor is covered in section 14.5.3 of ref [2]_. Switch to the Hypervisor context is done via the instruction **HVCS** that expects the Opcode for hcall is set in *r3* and any in-arguments for the hcall are provided in registers *r4-r12*. If values have to be passed through a memory buffer, the data stored in that buffer should be in Big-endian byte order.h](hrThe ABI specification for a hcall between a pseries guest and PAPR hypervisor is covered in section 14.5.3 of ref }(hjhhhNhNubh)}(h[2]_h]h2}(hjhhhNhNubah}(h]id4ah ]h"]h$]h&]j jpj j uh1hhjj Kubh@. Switch to the Hypervisor context is done via the instruction }(hjhhhNhNubj()}(h**HVCS**h]hHVCS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubh- that expects the Opcode for hcall is set in }(hjhhhNhNubj)}(h*r3*h]hr3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh> and any in-arguments for the hcall are provided in registers }(hjhhhNhNubj)}(h*r4-r12*h]hr4-r12}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhy. If values have to be passed through a memory buffer, the data stored in that buffer should be in Big-endian byte order.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK$hjhhubh)}(hX4Once control returns back to the guest after hypervisor has serviced the 'HVCS' instruction the return value of the hcall is available in *r3* and any out values are returned in registers *r4-r12*. Again like in case of in-arguments, any out values stored in a memory buffer will be in Big-endian byte order.h](hOnce control returns back to the guest after hypervisor has serviced the ‘HVCS’ instruction the return value of the hcall is available in }(hj=hhhNhNubj)}(h*r3*h]hr3}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh. and any out values are returned in registers }(hj=hhhNhNubj)}(h*r4-r12*h]hr4-r12}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubhp. Again like in case of in-arguments, any out values stored in a memory buffer will be in Big-endian byte order.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK+hjhhubh)}(hPowerpc arch code provides convenient wrappers named **plpar_hcall_xxx** defined in a arch specific header [4]_ to issue hcalls from the linux kernel running as pseries guest.h](h5Powerpc arch code provides convenient wrappers named }(hjohhhNhNubj()}(h**plpar_hcall_xxx**h]hplpar_hcall_xxx}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjoubh# defined in a arch specific header }(hjohhhNhNubh)}(h[4]_h]h4}(hjhhhNhNubah}(h]id5ah ]h"]h$]h&]j id12j j uh1hhjoj Kubh@ to issue hcalls from the linux kernel running as pseries guest.}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK0hjhhubeh}(h] hcall-abiah ]h"] hcall abiah$]h&]uh1hhhhhhhhK#ubh)}(hhh](h)}(hRegister Conventionsh]hRegister Conventions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK5ubh)}(hAny hcall should follow same register convention as described in section 2.2.1.1 of "64-Bit ELF V2 ABI Specification: Power Architecture"[5]_. Table below summarizes these conventions:h](hAny hcall should follow same register convention as described in section 2.2.1.1 of “64-Bit ELF V2 ABI Specification: Power Architecture”}(hjhhhNhNubh)}(h[5]_h]h5}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]j id13j j uh1hhjj Kubh+. Table below summarizes these conventions:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK7hjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK+uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hRegister Rangeh]hRegister Range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhj;ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h Link Registerh]h Link Register}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjQubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j hjgubj)}(hhh](j)}(hhh]h)}(hCTRh]hCTR}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjqubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(hjh]hY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(h Loop Counterh]h Loop Counter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1j hjgubj)}(hhh](j)}(hhh]h)}(hXERh]hXER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]hY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFixed-point exception register.h]hFixed-point exception register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjgubj)}(hhh](j)}(hhh]h)}(hCR0-1h]hCR0-1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]hY}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCondition register fields.h]hCondition register fields.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjgubj)}(hhh](j)}(hhh]h)}(hCR2-4h]hCR2-4}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(hjh]hN}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjoubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(hCondition register fields.h]hCondition register fields.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j hjgubj)}(hhh](j)}(hhh]h)}(hCR5-7h]hCR5-7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]hY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCondition register fields.h]hCondition register fields.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjgubj)}(hhh](j)}(hhh]h)}(hOthersh]hOthers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]hN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjgubeh}(h]h ]h"]h$]h&]uh1jehjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]register-conventionsah ]h"]register conventionsah$]h&]uh1hhhhhhhhK5ubh)}(hhh](h)}(hDRC & DRC Indexesh]hDRC & DRC Indexes}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhhhhhKbubh literal_block)}(hXDR1 Guest +--+ +------------+ +---------+ | | <----> | | | User | +--+ DRC1 | | DRC | Space | | PAPR | Index +---------+ DR2 | Hypervisor | | | +--+ | | <-----> | Kernel | | | <----> | | Hcall | | +--+ DRC2 +------------+ +---------+h]hXDR1 Guest +--+ +------------+ +---------+ | | <----> | | | User | +--+ DRC1 | | DRC | Space | | PAPR | Index +---------+ DR2 | Hypervisor | | | +--+ | | <-----> | Kernel | | | <----> | | Hcall | | +--+ DRC2 +------------+ +---------+}hj\sbah}(h]h ]h"]h$]h&]hhuh1jZhhhKehjIhhubh)}(hXPAPR hypervisor terms shared hardware resources like PCI devices, NVDIMMs etc available for use by LPARs as Dynamic Resource (DR). When a DR is allocated to an LPAR, PHYP creates a data-structure called Dynamic Resource Connector (DRC) to manage LPAR access. An LPAR refers to a DRC via an opaque 32-bit number called DRC-Index. The DRC-index value is provided to the LPAR via device-tree where its present as an attribute in the device tree node associated with the DR.h]hXPAPR hypervisor terms shared hardware resources like PCI devices, NVDIMMs etc available for use by LPARs as Dynamic Resource (DR). When a DR is allocated to an LPAR, PHYP creates a data-structure called Dynamic Resource Connector (DRC) to manage LPAR access. An LPAR refers to a DRC via an opaque 32-bit number called DRC-Index. The DRC-index value is provided to the LPAR via device-tree where its present as an attribute in the device tree node associated with the DR.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjIhhubeh}(h]drc-drc-indexesah ]h"]drc & drc indexesah$]h&]uh1hhhhhhhhKbubh)}(hhh](h)}(hHCALL Return-valuesh]hHCALL Return-values}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKxubh)}(hAfter servicing the hcall, hypervisor sets the return-value in *r3* indicating success or failure of the hcall. In case of a failure an error code indicates the cause for error. These codes are defined and documented in arch specific header [4]_.h](h?After servicing the hcall, hypervisor sets the return-value in }(hjhhhNhNubj)}(h*r3*h]hr3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh indicating success or failure of the hcall. In case of a failure an error code indicates the cause for error. These codes are defined and documented in arch specific header }(hjhhhNhNubh)}(h[4]_h]h4}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]j jj j uh1hhjj Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhjhhubh)}(hXHIn some cases a hcall can potentially take a long time and need to be issued multiple times in order to be completely serviced. These hcalls will usually accept an opaque value *continue-token* within there argument list and a return value of *H_CONTINUE* indicates that hypervisor hasn't still finished servicing the hcall yet.h](hIn some cases a hcall can potentially take a long time and need to be issued multiple times in order to be completely serviced. These hcalls will usually accept an opaque value }(hjhhhNhNubj)}(h*continue-token*h]hcontinue-token}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh2 within there argument list and a return value of }(hjhhhNhNubj)}(h *H_CONTINUE*h]h H_CONTINUE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhK indicates that hypervisor hasn’t still finished servicing the hcall yet.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hTo make such hcalls the guest need to set *continue-token == 0* for the initial call and use the hypervisor returned value of *continue-token* for each subsequent hcall until hypervisor returns a non *H_CONTINUE* return value.h](h*To make such hcalls the guest need to set }(hjhhhNhNubj)}(h*continue-token == 0*h]hcontinue-token == 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh? for the initial call and use the hypervisor returned value of }(hjhhhNhNubj)}(h*continue-token*h]hcontinue-token}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: for each subsequent hcall until hypervisor returns a non }(hjhhhNhNubj)}(h *H_CONTINUE*h]h H_CONTINUE}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh return value.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]hcall-return-valuesah ]h"]hcall return-valuesah$]h&]uh1hhhhhhhhKxubh)}(hhh](h)}(hHCALL Op-codesh]hHCALL Op-codes}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB hhhhhKubh)}(hBelow is a partial list of HCALLs that are supported by PHYP. For the corresponding opcode values please look into the arch specific header [4]_:h](hBelow is a partial list of HCALLs that are supported by PHYP. For the corresponding opcode values please look into the arch specific header }(hjS hhhNhNubh)}(h[4]_h]h4}(hj[ hhhNhNubah}(h]id8ah ]h"]h$]h&]j jj j uh1hhjS j Kubh:}(hjS hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h**H_SCM_READ_METADATA**h]j()}(hjv h]hH_SCM_READ_METADATA}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjt ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh line_block)}(hhh](hh)}(h9Input: *drcIndex, offset, buffer-address, numBytesToRead*h](hInput: }(hj hhhNhNubj)}(h2*drcIndex, offset, buffer-address, numBytesToRead*h]h0drcIndex, offset, buffer-address, numBytesToRead}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hindentKhj hhhhhKubj )}(hOut: *numBytesRead*h](hOut: }(hj hhhNhNubj)}(h*numBytesRead*h]h numBytesRead}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h>Return Value: *H_Success, H_Parameter, H_P2, H_P3, H_Hardware*h](hReturn Value: }(hj hhhNhNubj)}(h0*H_Success, H_Parameter, H_P2, H_P3, H_Hardware*h]h.H_Success, H_Parameter, H_P2, H_P3, H_Hardware}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(hXZGiven a DRC Index of an NVDIMM, read N-bytes from the metadata area associated with it, at a specified offset and copy it to provided buffer. The metadata area stores configuration information such as label information, bad-blocks etc. The metadata area is located out-of-band of NVDIMM storage area hence a separate access semantics is provided.h]hXZGiven a DRC Index of an NVDIMM, read N-bytes from the metadata area associated with it, at a specified offset and copy it to provided buffer. The metadata area stores configuration information such as label information, bad-blocks etc. The metadata area is located out-of-band of NVDIMM storage area hence a separate access semantics is provided.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h**H_SCM_WRITE_METADATA**h]j()}(hj h]hH_SCM_WRITE_METADATA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj )}(hhh](j )}(h0Input: *drcIndex, offset, data, numBytesToWrite*h](hInput: }(hj hhhNhNubj)}(h)*drcIndex, offset, data, numBytesToWrite*h]h'drcIndex, offset, data, numBytesToWrite}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h Out: *None*h](hOut: }(hj0 hhhNhNubj)}(h*None*h]hNone}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0 ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h>Return Value: *H_Success, H_Parameter, H_P2, H_P4, H_Hardware*h](hReturn Value: }(hjL hhhNhNubj)}(h0*H_Success, H_Parameter, H_P2, H_P4, H_Hardware*h]h.H_Success, H_Parameter, H_P2, H_P4, H_Hardware}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(hGiven a DRC Index of an NVDIMM, write N-bytes to the metadata area associated with it, at the specified offset and from the provided buffer.h]hGiven a DRC Index of an NVDIMM, write N-bytes to the metadata area associated with it, at the specified offset and from the provided buffer.}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h**H_SCM_BIND_MEM**h]j()}(hj~ h]hH_SCM_BIND_MEM}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj| ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj )}(hhh](j )}(h=Input: *drcIndex, startingScmBlockIndex, numScmBlocksToBind,*h](hInput: }(hj hhhNhNubj)}(h6*drcIndex, startingScmBlockIndex, numScmBlocksToBind,*h]h4drcIndex, startingScmBlockIndex, numScmBlocksToBind,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h,*targetLogicalMemoryAddress, continue-token*h]j)}(hj h]h*targetLogicalMemoryAddress, continue-token}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(hFOut: *continue-token, targetLogicalMemoryAddress, numScmBlocksToBound*h](hOut: }(hj hhhNhNubj)}(hA*continue-token, targetLogicalMemoryAddress, numScmBlocksToBound*h]h?continue-token, targetLogicalMemoryAddress, numScmBlocksToBound}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(hDReturn Value: *H_Success, H_Parameter, H_P2, H_P3, H_P4, H_Overlap,*h](hReturn Value: }(hj hhhNhNubj)}(h6*H_Success, H_Parameter, H_P2, H_P3, H_P4, H_Overlap,*h]h4H_Success, H_Parameter, H_P2, H_P3, H_P4, H_Overlap,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h*H_Too_Big, H_P5, H_Busy*h]j)}(hj h]hH_Too_Big, H_P5, H_Busy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(hXGiven a DRC-Index of an NVDIMM, map a continuous SCM blocks range *(startingScmBlockIndex, startingScmBlockIndex+numScmBlocksToBind)* to the guest at *targetLogicalMemoryAddress* within guest physical address space. In case *targetLogicalMemoryAddress == 0xFFFFFFFF_FFFFFFFF* then hypervisor assigns a target address to the guest. The HCALL can fail if the Guest has an active PTE entry to the SCM block being bound.h](hBGiven a DRC-Index of an NVDIMM, map a continuous SCM blocks range }(hj hhhNhNubj)}(hC*(startingScmBlockIndex, startingScmBlockIndex+numScmBlocksToBind)*h]hA(startingScmBlockIndex, startingScmBlockIndex+numScmBlocksToBind)}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh to the guest at }(hj hhhNhNubj)}(h*targetLogicalMemoryAddress*h]htargetLogicalMemoryAddress}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh. within guest physical address space. In case }(hj hhhNhNubj)}(h3*targetLogicalMemoryAddress == 0xFFFFFFFF_FFFFFFFF*h]h1targetLogicalMemoryAddress == 0xFFFFFFFF_FFFFFFFF}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh then hypervisor assigns a target address to the guest. The HCALL can fail if the Guest has an active PTE entry to the SCM block being bound.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h**H_SCM_UNBIND_MEM** | Input: drcIndex, startingScmLogicalMemoryAddress, numScmBlocksToUnbind | Out: numScmBlocksUnbound | Return Value: *H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Overlap,* | *H_Busy, H_LongBusyOrder1mSec, H_LongBusyOrder10mSec*h](j()}(h**H_SCM_UNBIND_MEM**h]hH_SCM_UNBIND_MEM}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjb ubhu | Input: drcIndex, startingScmLogicalMemoryAddress, numScmBlocksToUnbind | Out: numScmBlocksUnbound | Return Value: }(hjb hhhNhNubj)}(h:*H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Overlap,*h]h8H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Overlap,}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb ubh | }(hjb hhhNhNubj)}(h5*H_Busy, H_LongBusyOrder1mSec, H_LongBusyOrder10mSec*h]h3H_Busy, H_LongBusyOrder1mSec, H_LongBusyOrder10mSec}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(hGiven a DRC-Index of an NVDimm, unmap *numScmBlocksToUnbind* SCM blocks starting at *startingScmLogicalMemoryAddress* from guest physical address space. The HCALL can fail if the Guest has an active PTE entry to the SCM block being unbound.h](h&Given a DRC-Index of an NVDimm, unmap }(hj hhhNhNubj)}(h*numScmBlocksToUnbind*h]hnumScmBlocksToUnbind}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh SCM blocks starting at }(hj hhhNhNubj)}(h!*startingScmLogicalMemoryAddress*h]hstartingScmLogicalMemoryAddress}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh{ from guest physical address space. The HCALL can fail if the Guest has an active PTE entry to the SCM block being unbound.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h!**H_SCM_QUERY_BLOCK_MEM_BINDING**h]j()}(hj h]hH_SCM_QUERY_BLOCK_MEM_BINDING}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj )}(hhh](j )}(h Input: *drcIndex, scmBlockIndex*h](hInput: }(hj hhhNhNubj)}(h*drcIndex, scmBlockIndex*h]hdrcIndex, scmBlockIndex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(hOut: *Guest-Physical-Address*h](hOut: }(hj hhhNhNubj)}(h*Guest-Physical-Address*h]hGuest-Physical-Address}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h8Return Value: *H_Success, H_Parameter, H_P2, H_NotFound*h](hReturn Value: }(hj" hhhNhNubj)}(h**H_Success, H_Parameter, H_P2, H_NotFound*h]h(H_Success, H_Parameter, H_P2, H_NotFound}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj" ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(hoGiven a DRC-Index and an SCM Block index return the guest physical address to which the SCM block is mapped to.h]hoGiven a DRC-Index and an SCM Block index return the guest physical address to which the SCM block is mapped to.}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h#**H_SCM_QUERY_LOGICAL_MEM_BINDING**h]j()}(hjT h]hH_SCM_QUERY_LOGICAL_MEM_BINDING}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjR ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj )}(hhh](j )}(hInput: *Guest-Physical-Address*h](hInput: }(hjl hhhNhNubj)}(h*Guest-Physical-Address*h]hGuest-Physical-Address}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl ubeh}(h]h ]h"]h$]h&]uh1hj Khji hhhhhKubj )}(hOut: *drcIndex, scmBlockIndex*h](hOut: }(hj hhhNhNubj)}(h*drcIndex, scmBlockIndex*h]hdrcIndex, scmBlockIndex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khji hhhhhKubj )}(h8Return Value: *H_Success, H_Parameter, H_P2, H_NotFound*h](hReturn Value: }(hj hhhNhNubj)}(h**H_Success, H_Parameter, H_P2, H_NotFound*h]h(H_Success, H_Parameter, H_P2, H_NotFound}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khji hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(h^Given a guest physical address return which DRC Index and SCM block is mapped to that address.h]h^Given a guest physical address return which DRC Index and SCM block is mapped to that address.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h**H_SCM_UNBIND_ALL**h]j()}(hj h]hH_SCM_UNBIND_ALL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj )}(hhh](j )}(h!Input: *scmTargetScope, drcIndex*h](hInput: }(hj hhhNhNubj)}(h*scmTargetScope, drcIndex*h]hscmTargetScope, drcIndex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h Out: *None*h](hOut: }(hj hhhNhNubj)}(h*None*h]hNone}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(hEReturn Value: *H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Busy,*h](hReturn Value: }(hj& hhhNhNubj)}(h7*H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Busy,*h]h5H_Success, H_Parameter, H_P2, H_P3, H_In_Use, H_Busy,}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj& ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h-*H_LongBusyOrder1mSec, H_LongBusyOrder10mSec*h]j)}(hjD h]h+H_LongBusyOrder1mSec, H_LongBusyOrder10mSec}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB ubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(hDepending on the Target scope unmap all SCM blocks belonging to all NVDIMMs or all SCM blocks belonging to a single NVDIMM identified by its drcIndex from the LPAR memory.h]hDepending on the Target scope unmap all SCM blocks belonging to all NVDIMMs or all SCM blocks belonging to a single NVDIMM identified by its drcIndex from the LPAR memory.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(h**H_SCM_HEALTH**h]j()}(hjo h]h H_SCM_HEALTH}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjm ubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj )}(hhh](j )}(hInput: drcIndexh]hInput: drcIndex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h7Out: *health-bitmap (r4), health-bit-valid-bitmap (r5)*h](hOut: }(hj hhhNhNubj)}(h2*health-bitmap (r4), health-bit-valid-bitmap (r5)*h]h0health-bitmap (r4), health-bit-valid-bitmap (r5)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubj )}(h2Return Value: *H_Success, H_Parameter, H_Hardware*h](hReturn Value: }(hj hhhNhNubj)}(h$*H_Success, H_Parameter, H_Hardware*h]h"H_Success, H_Parameter, H_Hardware}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1hj Khj hhhhhKubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhKubh)}(hXGiven a DRC Index return the info on predictive failure and overall health of the PMEM device. The asserted bits in the health-bitmap indicate one or more states (described in table below) of the PMEM device and health-bit-valid-bitmap indicate which bits in health-bitmap are valid. The bits are reported in reverse bit ordering for example a value of 0xC400000000000000 indicates bits 0, 1, and 5 are valid.h]hXGiven a DRC Index return the info on predictive failure and overall health of the PMEM device. The asserted bits in the health-bitmap indicate one or more states (described in table below) of the PMEM device and health-bit-valid-bitmap indicate which bits in health-bitmap are valid. The bits are reported in reverse bit ordering for example a value of 0xC400000000000000 indicates bits 0, 1, and 5 are valid.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubh)}(hHealth Bitmap Flags:h]hHealth Bitmap Flags:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB hhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKGuh1jhj ubj )}(hhh]j)}(hhh](j)}(hhh]h)}(hBith]hBit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Definitionh]h Definition}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1jhj ubjf)}(hhh](j)}(hhh](j)}(hhh]h)}(h00h]h00}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjOubah}(h]h ]h"]h$]h&]uh1jhjLubj)}(hhh]h)}(hgPMEM device is unable to persist memory contents. If the system is powered down, nothing will be saved.h]hgPMEM device is unable to persist memory contents. If the system is powered down, nothing will be saved.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjfubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h01h]h01}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMEM device failed to persist memory contents. Either contents were not saved successfully on power down or were not restored properly on power up.h]hPMEM device failed to persist memory contents. Either contents were not saved successfully on power down or were not restored properly on power up.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h02h]h02}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hmPMEM device contents are persisted from previous IPL. The data from the last boot were successfully restored.h]hmPMEM device contents are persisted from previous IPL. The data from the last boot were successfully restored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h03h]h03}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjPMEM device contents are not persisted from previous IPL. There was no data to restore from the last boot.h]hjPMEM device contents are not persisted from previous IPL. There was no data to restore from the last boot.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h04h]h04}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]h)}(h3PMEM device memory life remaining is critically lowh]h3PMEM device memory life remaining is critically low}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjBubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h05h]h05}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjbubah}(h]h ]h"]h$]h&]uh1jhj_ubj)}(hhh]h)}(h6PMEM device will be garded off next IPL due to failureh]h6PMEM device will be garded off next IPL due to failure}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h06h]h06}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMEM device contents cannot persist due to current platform health status. A hardware failure may prevent data from being saved or restored.h]hPMEM device contents cannot persist due to current platform health status. A hardware failure may prevent data from being saved or restored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h07h]h07}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFPMEM device is unable to persist memory contents in certain conditionsh]hFPMEM device is unable to persist memory contents in certain conditions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h08h]h08}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMEM device is encryptedh]hPMEM device is encrypted}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h09h]h09}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(hSPMEM device has successfully completed a requested erase or secure erase procedure.h]hSPMEM device has successfully completed a requested erase or secure erase procedure.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j hjIubj)}(hhh](j)}(hhh]h)}(h10:63h]h10:63}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjuubah}(h]h ]h"]h$]h&]uh1jhjrubj)}(hhh]h)}(hReserved / Unusedh]hReserved / Unused}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1j hjIubeh}(h]h ]h"]h$]h&]uh1jehj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjB hhhhhNubh)}(h**H_SCM_PERFORMANCE_STATS**h]j()}(hjh]hH_SCM_PERFORMANCE_STATS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhhhM hjB hhubj )}(hhh](j )}(h"Input: drcIndex, resultBuffer Addrh]h"Input: drcIndex, resultBuffer Addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMubj )}(h Out: Noneh]h Out: None}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMubj )}(h\Return Value: *H_Success, H_Parameter, H_Unsupported, H_Hardware, H_Authority, H_Privilege*h](hReturn Value: }(hjhhhNhNubj)}(hM*H_Success, H_Parameter, H_Unsupported, H_Hardware, H_Authority, H_Privilege*h]hKH_Success, H_Parameter, H_Unsupported, H_Hardware, H_Authority, H_Privilege}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhMubh)}(hbGiven a DRC Index collect the performance statistics for NVDIMM and copy them to the resultBuffer.h]hbGiven a DRC Index collect the performance statistics for NVDIMM and copy them to the resultBuffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjB hhubh)}(h**H_SCM_FLUSH**h]j()}(hj$h]h H_SCM_FLUSH}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj"ubah}(h]h ]h"]h$]h&]uh1hhhhMhjB hhubj )}(hhh](j )}(h!Input: *drcIndex, continue-token*h](hInput: }(hj<hhhNhNubj)}(h*drcIndex, continue-token*h]hdrcIndex, continue-token}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1hj Khj9hhhhhMubj )}(hOut: *continue-token*h](hOut: }(hjXhhhNhNubj)}(h*continue-token*h]hcontinue-token}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1hj Khj9hhhhhMubj )}(h4Return Value: *H_SUCCESS, H_Parameter, H_P2, H_BUSY*h](hReturn Value: }(hjthhhNhNubj)}(h&*H_SUCCESS, H_Parameter, H_P2, H_BUSY*h]h$H_SUCCESS, H_Parameter, H_P2, H_BUSY}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1hj Khj9hhhhhMubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhMubh)}(h:Given a DRC Index Flush the data to backend NVDIMM device.h]h:Given a DRC Index Flush the data to backend NVDIMM device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjB hhubh)}(hXiThe hcall returns H_BUSY when the flush takes longer time and the hcall needs to be issued multiple times in order to be completely serviced. The *continue-token* from the output to be passed in the argument list of subsequent hcalls to the hypervisor until the hcall is completely serviced at which point H_SUCCESS or other error is returned by the hypervisor.h](hThe hcall returns H_BUSY when the flush takes longer time and the hcall needs to be issued multiple times in order to be completely serviced. The }(hjhhhNhNubj)}(h*continue-token*h]hcontinue-token}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh from the output to be passed in the argument list of subsequent hcalls to the hypervisor until the hcall is completely serviced at which point H_SUCCESS or other error is returned by the hypervisor.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjB hhubh)}(h **H_HTM**h]j()}(hjh]hH_HTM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhhhM$hjB hhubj )}(hhh](j )}(hEInput: flags, target, operation (op), op-param1, op-param2, op-param3h]hEInput: flags, target, operation (op), op-param1, op-param2, op-param3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM&ubj )}(hOut: *dumphtmbufferdata*h](hOut: }(hjhhhNhNubj)}(h*dumphtmbufferdata*h]hdumphtmbufferdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM'ubj )}(hReturn Value: *H_Success,H_Busy,H_LongBusyOrder,H_Partial,H_Parameter, H_P2,H_P3,H_P4,H_P5,H_P6,H_State,H_Not_Available,H_Authority*h](hReturn Value: }(hjhhhNhNubj)}(hv*H_Success,H_Busy,H_LongBusyOrder,H_Partial,H_Parameter, H_P2,H_P3,H_P4,H_P5,H_P6,H_State,H_Not_Available,H_Authority*h]htH_Success,H_Busy,H_LongBusyOrder,H_Partial,H_Parameter, H_P2,H_P3,H_P4,H_P5,H_P6,H_State,H_Not_Available,H_Authority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM)ubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhM&ubh)}(hH_HTM supports setup, configuration, control and dumping of Hardware Trace Macro (HTM) function and its data. HTM buffer stores tracing data for functions like core instruction, core LLAT and nest.h]hH_HTM supports setup, configuration, control and dumping of Hardware Trace Macro (HTM) function and its data. HTM buffer stores tracing data for functions like core instruction, core LLAT and nest.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjB hhubh)}(h**H_PKS_GEN_KEY**h]j()}(hj:h]h H_PKS_GEN_KEY}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj8ubah}(h]h ]h"]h$]h&]uh1hhhhM/hjB hhubj )}(hhh](j )}(hFInput: authorization, objectlabel, objectlabellen, policy, out, outlenh]hFInput: authorization, objectlabel, objectlabellen, policy, out, outlen}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjOhhhhhM1ubj )}(hLOut: *Hypervisor Generated Key, or None when the wrapping key policy is set*h](hOut: }(hj`hhhNhNubj)}(hG*Hypervisor Generated Key, or None when the wrapping key policy is set*h]hEHypervisor Generated Key, or None when the wrapping key policy is set}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1hj KhjOhhhhhM2ubj )}(hReturn Value: *H_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_Authority, H_Nomem, H_Busy, H_Resource, H_Aborted*h](hReturn Value: }(hj|hhhNhNubj)}(h*H_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_Authority, H_Nomem, H_Busy, H_Resource, H_Aborted*h]hH_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_Authority, H_Nomem, H_Busy, H_Resource, H_Aborted}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hj KhjOhhhhhM5ubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhM1ubh)}(hX{H_PKS_GEN_KEY is used to have the hypervisor generate a new random key. This key is stored as an object in the Power LPAR Platform KeyStore with the provided object label. With the wrapping key policy set the key is only visible to the hypervisor, while the key's label would still be visible to the user. Generation of wrapping keys is supported only for a key size of 32 bytes.h]hX}H_PKS_GEN_KEY is used to have the hypervisor generate a new random key. This key is stored as an object in the Power LPAR Platform KeyStore with the provided object label. With the wrapping key policy set the key is only visible to the hypervisor, while the key’s label would still be visible to the user. Generation of wrapping keys is supported only for a key size of 32 bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjB hhubh)}(h**H_PKS_WRAP_OBJECT**h]j()}(hjh]hH_PKS_WRAP_OBJECT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhhhM>hjB hhubj )}(hhh](j )}(hIInput: authorization, wrapkeylabel, wrapkeylabellen, objectwrapflags, in,h]hIInput: authorization, wrapkeylabel, wrapkeylabellen, objectwrapflags, in,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhM@ubj )}(hhh]j )}(h"inlen, out, outlen, continue-tokenh]h"inlen, out, outlen, continue-token}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMAubah}(h]h ]h"]h$]h&]uh1j hjhhhhhMEubj )}(hBOut: *continue-token, byte size of wrapped object, wrapped object*h](hOut: }(hjhhhNhNubj)}(h=*continue-token, byte size of wrapped object, wrapped object*h]h;continue-token, byte size of wrapped object, wrapped object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMBubj )}(hReturn Value: *H_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_P7, H_P8, H_P9, H_Authority, H_Invalid_Key, H_NOT_FOUND, H_Busy, H_LongBusy, H_Aborted*h](hReturn Value: }(hjhhhNhNubj)}(h*H_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_P7, H_P8, H_P9, H_Authority, H_Invalid_Key, H_NOT_FOUND, H_Busy, H_LongBusy, H_Aborted*h]hH_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_P7, H_P8, H_P9, H_Authority, H_Invalid_Key, H_NOT_FOUND, H_Busy, H_LongBusy, H_Aborted}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hj KhjhhhhhMEubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhM@ubh)}(hXH_PKS_WRAP_OBJECT is used to wrap an object using a wrapping key stored in the Power LPAR Platform KeyStore and return the wrapped object to the caller. The caller provides a label to a wrapping key with the 'wrapping key' policy set, which must have been previously created with H_PKS_GEN_KEY. The provided object is then encrypted with the wrapping key and additional metadata and the result is returned to the caller.h]hXH_PKS_WRAP_OBJECT is used to wrap an object using a wrapping key stored in the Power LPAR Platform KeyStore and return the wrapped object to the caller. The caller provides a label to a wrapping key with the ‘wrapping key’ policy set, which must have been previously created with H_PKS_GEN_KEY. The provided object is then encrypted with the wrapping key and additional metadata and the result is returned to the caller.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjB hhubh)}(h**H_PKS_UNWRAP_OBJECT**h]j()}(hj9h]hH_PKS_UNWRAP_OBJECT}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj7ubah}(h]h ]h"]h$]h&]uh1hhhhMOhjB hhubj )}(hhh](j )}(hMInput: authorization, objectwrapflags, in, inlen, out, outlen, continue-tokenh]hMInput: authorization, objectwrapflags, in, inlen, out, outlen, continue-token}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hj KhjNhhhhhMQubj )}(hFOut: *continue-token, byte size of unwrapped object, unwrapped object*h](hOut: }(hj_hhhNhNubj)}(hA*continue-token, byte size of unwrapped object, unwrapped object*h]h?continue-token, byte size of unwrapped object, unwrapped object}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1hj KhjNhhhhhMRubj )}(hReturn Value: *H_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_P7, H_Authority, H_Unsupported, H_Bad_Data, H_NOT_FOUND, H_Invalid_Key, H_Busy, H_LongBusy, H_Aborted*h](hReturn Value: }(hj{hhhNhNubj)}(h*H_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_P7, H_Authority, H_Unsupported, H_Bad_Data, H_NOT_FOUND, H_Invalid_Key, H_Busy, H_LongBusy, H_Aborted*h]hH_SUCCESS, H_Function, H_State, H_R_State, H_Parameter, H_P2, H_P3, H_P4, H_P5, H_P6, H_P7, H_Authority, H_Unsupported, H_Bad_Data, H_NOT_FOUND, H_Invalid_Key, H_Busy, H_LongBusy, H_Aborted}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1hj KhjNhhhhhMUubeh}(h]h ]h"]h$]h&]uh1j hjB hhhhhMQubh)}(hdH_PKS_UNWRAP_OBJECT is used to unwrap an object that was previously warapped with H_PKS_WRAP_OBJECT.h]hdH_PKS_UNWRAP_OBJECT is used to unwrap an object that was previously warapped with H_PKS_WRAP_OBJECT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjB hhubeh}(h]hcall-op-codesah ]h"]hcall op-codesah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Referencesh]h References}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM[ubhfootnote)}(hk"Power Architecture Platform Reference" https://en.wikipedia.org/wiki/Power_Architecture_Platform_Referenceh](hlabel)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hk"Power Architecture Platform Reference" https://en.wikipedia.org/wiki/Power_Architecture_Platform_Referenceh](h,“Power Architecture Platform Reference” }(hjhhhNhNubh reference)}(hChttps://en.wikipedia.org/wiki/Power_Architecture_Platform_Referenceh]hChttps://en.wikipedia.org/wiki/Power_Architecture_Platform_Reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhM\hjubeh}(h]j ah ]h"]1ah$]h&]jaj j uh1jhhhM\hjhhj Kubj)}(hh"Linux on Power Architecture Platform Reference" https://members.openpowerfoundation.org/document/dl/469h](j)}(h2h]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hh"Linux on Power Architecture Platform Reference" https://members.openpowerfoundation.org/document/dl/469h](h5“Linux on Power Architecture Platform Reference” }(hjhhhNhNubj)}(h7https://members.openpowerfoundation.org/document/dl/469h]h7https://members.openpowerfoundation.org/document/dl/469}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhM^hjubeh}(h]jpah ]h"]2ah$]h&](jkjej j uh1jhhhM^hjhhj Kubj)}(hv"Definitions and Notation" Book III-Section 14.5.3 https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0h](j)}(h3h]h3}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh)}(hv"Definitions and Notation" Book III-Section 14.5.3 https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0h](h7“Definitions and Notation” Book III-Section 14.5.3 }(hjHhhhNhNubj)}(hChttps://openpowerfoundation.org/?resource_lib=power-isa-version-3-0h]hChttps://openpowerfoundation.org/?resource_lib=power-isa-version-3-0}(hjPhhhNhNubah}(h]h ]h"]h$]h&]refurijRuh1jhjHubeh}(h]h ]h"]h$]h&]uh1hhhhM`hj6ubeh}(h]jah ]h"]3ah$]h&]jaj j uh1jhhhM`hjhhj Kubj)}(h!arch/powerpc/include/asm/hvcall.hh](j)}(h4h]h4}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubh)}(hjnh]h!arch/powerpc/include/asm/hvcall.h}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhjlubeh}(h]jah ]h"]4ah$]h&](jjje ej j uh1jhhhMbhjhhj Kubj)}(h"64-Bit ELF V2 ABI Specification: Power Architecture" https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architectureh](j)}(h5h]h5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h"64-Bit ELF V2 ABI Specification: Power Architecture" https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architectureh](h:“64-Bit ELF V2 ABI Specification: Power Architecture” }(hjhhhNhNubj)}(h`https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architectureh]h`https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhMchjubeh}(h]jah ]h"]5ah$]h&]jaj j uh1jhhhMchjhhj Kubeh}(h] referencesah ]h"] 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