>sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget+/translations/zh_CN/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/zh_TW/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/it_IT/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/ja_JP/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/ko_KR/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/pt_BR/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/sp_SP/arch/powerpc/elf_hwcapsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhtarget)}(h.. _elf_hwcaps_powerpc:h]h}(h]h ]h"]h$]h&]refidelf-hwcaps-powerpcuh1hhKhhhhhE/var/lib/git/docbuild/linux/Documentation/arch/powerpc/elf_hwcaps.rstubhsection)}(hhh](htitle)}(hPOWERPC ELF HWCAPsh]hPOWERPC ELF HWCAPs}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hJThis document describes the usage and semantics of the powerpc ELF HWCAPs.h]hJThis document describes the usage and semantics of the powerpc ELF HWCAPs.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h1. Introductionh]h1. Introduction}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hXFSome hardware or software features are only available on some CPU implementations, and/or with certain kernel configurations, but have no other discovery mechanism available to userspace code. The kernel exposes the presence of these features to userspace through a set of flags called HWCAPs, exposed in the auxiliary vector.h]hXFSome hardware or software features are only available on some CPU implementations, and/or with certain kernel configurations, but have no other discovery mechanism available to userspace code. The kernel exposes the presence of these features to userspace through a set of flags called HWCAPs, exposed in the auxiliary vector.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hUserspace software can test for features by acquiring the AT_HWCAP or AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant flags are set, e.g.::h]hUserspace software can test for features by acquiring the AT_HWCAP or AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant flags are set, e.g.:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh literal_block)}(hbool floating_point_is_present(void) { unsigned long HWCAPs = getauxval(AT_HWCAP); if (HWCAPs & PPC_FEATURE_HAS_FPU) return true; return false; }h]hbool floating_point_is_present(void) { unsigned long HWCAPs = getauxval(AT_HWCAP); if (HWCAPs & PPC_FEATURE_HAS_FPU) return true; return false; }}hjsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jhhhKhhhhubh)}(hWhere software relies on a feature described by a HWCAP, it should check the relevant HWCAP flag to verify that the feature is present before attempting to make use of the feature.h]hWhere software relies on a feature described by a HWCAP, it should check the relevant HWCAP flag to verify that the feature is present before attempting to make use of the feature.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hHWCAP is the preferred method to test for the presence of a feature rather than probing through other means, which may not be reliable or may cause unpredictable behaviour.h]hHWCAP is the preferred method to test for the presence of a feature rather than probing through other means, which may not be reliable or may cause unpredictable behaviour.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hhhhubh)}(hX'Software that targets a particular platform does not necessarily have to test for required or implied features. For example if the program requires FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be impossible to do so if the compiler generates code requiring those features.h]hX'Software that targets a particular platform does not necessarily have to test for required or implied features. For example if the program requires FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be impossible to do so if the compiler generates code requiring those features.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hhhhubeh}(h] introductionah ]h"]1. introductionah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h 2. Facilitiesh]h 2. Facilities}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhK.ubh)}(hXvThe Power ISA uses the term "facility" to describe a class of instructions, registers, interrupts, etc. The presence or absence of a facility indicates whether this class is available to be used, but the specifics depend on the ISA version. For example, if the VSX facility is available, the VSX instructions that can be used differ between the v3.0B and v3.1B ISA versions.h]hXzThe Power ISA uses the term “facility” to describe a class of instructions, registers, interrupts, etc. The presence or absence of a facility indicates whether this class is available to be used, but the specifics depend on the ISA version. For example, if the VSX facility is available, the VSX instructions that can be used differ between the v3.0B and v3.1B ISA versions.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjZhhubeh}(h] facilitiesah ]h"] 2. facilitiesah$]h&]uh1hhhhhhhhK.ubh)}(hhh](h)}(h 3. Categoriesh]h 3. Categories}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK8ubh)}(hX7The Power ISA before v3.0 uses the term "category" to describe certain classes of instructions and operating modes which may be optional or mutually exclusive, the exact meaning of the HWCAP flag may depend on context, e.g., the presence of the BOOKE feature implies that the server category is not implemented.h]hX;The Power ISA before v3.0 uses the term “category” to describe certain classes of instructions and operating modes which may be optional or mutually exclusive, the exact meaning of the HWCAP flag may depend on context, e.g., the presence of the BOOKE feature implies that the server category is not implemented.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjhhubeh}(h] categoriesah ]h"] 3. categoriesah$]h&]uh1hhhhhhhhK8ubh)}(hhh](h)}(h4. HWCAP allocationh]h4. HWCAP allocation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKAubh)}(hHWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI Specification (which will be reflected in the kernel's uapi headers).h]hHWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI Specification (which will be reflected in the kernel’s uapi headers).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjhhubeh}(h]hwcap-allocationah ]h"]4. hwcap allocationah$]h&]uh1hhhhhhhhKAubh)}(hhh](h)}(h!5. The HWCAPs exposed in AT_HWCAPh]h!5. The HWCAPs exposed in AT_HWCAP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKGubhdefinition_list)}(hhh](hdefinition_list_item)}(hPPC_FEATURE_32 32-bit CPU h](hterm)}(hPPC_FEATURE_32h]hPPC_FEATURE_32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKJhjubh definition)}(hhh]h)}(h 32-bit CPUh]h 32-bit CPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKJhjubj)}(hEPPC_FEATURE_64 64-bit CPU (userspace may be running in 32-bit mode). h](j)}(hPPC_FEATURE_64h]hPPC_FEATURE_64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKMhjubj)}(hhh]h)}(h564-bit CPU (userspace may be running in 32-bit mode).h]h564-bit CPU (userspace may be running in 32-bit mode).}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKMhjhhubj)}(h|PPC_FEATURE_601_INSTR The processor is PowerPC 601. Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601") h](j)}(hPPC_FEATURE_601_INSTRh]hPPC_FEATURE_601_INSTR}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKQhjIubj)}(hhh]h)}(heThe processor is PowerPC 601. Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")h]hiThe processor is PowerPC 601. Unused in the kernel since f0ed73f3fa2c (“powerpc: Remove PowerPC 601”)}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhj[ubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhhhKQhjhhubj)}(hIPPC_FEATURE_HAS_ALTIVEC Vector (aka Altivec, VMX) facility is available. h](j)}(hPPC_FEATURE_HAS_ALTIVECh]hPPC_FEATURE_HAS_ALTIVEC}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKThjxubj)}(hhh]h)}(h0Vector (aka Altivec, VMX) facility is available.h]h0Vector (aka Altivec, VMX) facility is available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhhhKThjhhubj)}(h:PPC_FEATURE_HAS_FPU Floating point facility is available. h](j)}(hPPC_FEATURE_HAS_FPUh]hPPC_FEATURE_HAS_FPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKWhjubj)}(hhh]h)}(h%Floating point facility is available.h]h%Floating point facility is available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKWhjhhubj)}(hCPPC_FEATURE_HAS_MMU Memory management unit is present and enabled. h](j)}(hPPC_FEATURE_HAS_MMUh]hPPC_FEATURE_HAS_MMU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKZhjubj)}(hhh]h)}(h.Memory management unit is present and enabled.h]h.Memory management unit is present and enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKZhjhhubj)}(hPPC_FEATURE_HAS_4xxMAC The processor is 40x or 44x family. Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x") h](j)}(hPPC_FEATURE_HAS_4xxMACh]hPPC_FEATURE_HAS_4xxMAC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK^hjubj)}(hhh]h)}(htThe processor is 40x or 44x family. Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x")h]hxThe processor is 40x or 44x family. Unused in the kernel since 732b32daef80 (“powerpc: Remove core support for 40x”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK^hjhhubj)}(hPPC_FEATURE_UNIFIED_CACHE The processor has a unified L1 cache for instructions and data, as found in NXP e200. Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)") h](j)}(hPPC_FEATURE_UNIFIED_CACHEh]hPPC_FEATURE_UNIFIED_CACHE}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKchj4ubj)}(hhh]h)}(hThe processor has a unified L1 cache for instructions and data, as found in NXP e200. Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")h]hThe processor has a unified L1 cache for instructions and data, as found in NXP e200. Unused in the kernel since 39c8bf2b3cc1 (“powerpc: Retire e200 core (mpc555x processor)”)}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjFubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhhhKchjhhubj)}(hDPPC_FEATURE_HAS_SPE Signal Processing Engine facility is available. h](j)}(hPPC_FEATURE_HAS_SPEh]hPPC_FEATURE_HAS_SPE}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKfhjcubj)}(hhh]h)}(h/Signal Processing Engine facility is available.h]h/Signal Processing Engine facility is available.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjuubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhhhKfhjhhubj)}(h^PPC_FEATURE_HAS_EFP_SINGLE Embedded Floating Point single precision operations are available. h](j)}(hPPC_FEATURE_HAS_EFP_SINGLEh]hPPC_FEATURE_HAS_EFP_SINGLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKihjubj)}(hhh]h)}(hBEmbedded Floating Point single precision operations are available.h]hBEmbedded Floating Point single precision operations are available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKihjhhubj)}(h^PPC_FEATURE_HAS_EFP_DOUBLE Embedded Floating Point double precision operations are available. h](j)}(hPPC_FEATURE_HAS_EFP_DOUBLEh]hPPC_FEATURE_HAS_EFP_DOUBLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKlhjubj)}(hhh]h)}(hBEmbedded Floating Point double precision operations are available.h]hBEmbedded Floating Point double precision operations are available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKlhjhhubj)}(hXNPPC_FEATURE_NO_TB The timebase facility (mftb instruction) is not available. This is a 601 specific HWCAP, so if it is known that the processor running is not a 601, via other HWCAPs or other means, it is not required to test this bit before using the timebase. Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601") h](j)}(hPPC_FEATURE_NO_TBh]hPPC_FEATURE_NO_TB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKshjubj)}(hhh]h)}(hX;The timebase facility (mftb instruction) is not available. This is a 601 specific HWCAP, so if it is known that the processor running is not a 601, via other HWCAPs or other means, it is not required to test this bit before using the timebase. Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")h]hX?The timebase facility (mftb instruction) is not available. This is a 601 specific HWCAP, so if it is known that the processor running is not a 601, via other HWCAPs or other means, it is not required to test this bit before using the timebase. Unused in the kernel since f0ed73f3fa2c (“powerpc: Remove PowerPC 601”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKshjhhubj)}(hPPC_FEATURE_POWER4 The processor is POWER4 or PPC970/FX/MP. POWER4 support dropped from the kernel since 471d7ff8b51b ("powerpc/64s: Remove POWER4 support") h](j)}(hPPC_FEATURE_POWER4h]hPPC_FEATURE_POWER4}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKwhjubj)}(hhh]h)}(hThe processor is POWER4 or PPC970/FX/MP. POWER4 support dropped from the kernel since 471d7ff8b51b ("powerpc/64s: Remove POWER4 support")h]hThe processor is POWER4 or PPC970/FX/MP. POWER4 support dropped from the kernel since 471d7ff8b51b (“powerpc/64s: Remove POWER4 support”)}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKwhjhhubj)}(h,PPC_FEATURE_POWER5 The processor is POWER5. h](j)}(hPPC_FEATURE_POWER5h]hPPC_FEATURE_POWER5}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKzhjNubj)}(hhh]h)}(hThe processor is POWER5.h]hThe processor is POWER5.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhj`ubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhhhKzhjhhubj)}(h2PPC_FEATURE_POWER5_PLUS The processor is POWER5+. h](j)}(hPPC_FEATURE_POWER5_PLUSh]hPPC_FEATURE_POWER5_PLUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK}hj}ubj)}(hhh]h)}(hThe processor is POWER5+.h]hThe processor is POWER5+.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhhhK}hjhhubj)}(h(PPC_FEATURE_CELL The processor is Cell. h](j)}(hPPC_FEATURE_CELLh]hPPC_FEATURE_CELL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hThe processor is Cell.h]hThe processor is Cell.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hYPPC_FEATURE_BOOKE The processor implements the embedded category ("BookE") architecture. h](j)}(hPPC_FEATURE_BOOKEh]hPPC_FEATURE_BOOKE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hFThe processor implements the embedded category ("BookE") architecture.h]hJThe processor implements the embedded category (“BookE”) architecture.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(h.PPC_FEATURE_SMT The processor implements SMT. h](j)}(hPPC_FEATURE_SMTh]hPPC_FEATURE_SMT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hhh]h)}(hThe processor implements SMT.h]hThe processor implements SMT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXcPPC_FEATURE_ICACHE_SNOOP The processor icache is coherent with the dcache, and instruction storage can be made consistent with data storage for the purpose of executing instructions with the sequence (as described in, e.g., POWER9 Processor User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)):: sync icbi (to any address) isync h](j)}(hPPC_FEATURE_ICACHE_SNOOPh]hPPC_FEATURE_ICACHE_SNOOP}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj9ubj)}(hhh](h)}(hXThe processor icache is coherent with the dcache, and instruction storage can be made consistent with data storage for the purpose of executing instructions with the sequence (as described in, e.g., POWER9 Processor User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi))::h]hXThe processor icache is coherent with the dcache, and instruction storage can be made consistent with data storage for the purpose of executing instructions with the sequence (as described in, e.g., POWER9 Processor User’s Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)):}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjKubj)}(h sync icbi (to any address) isynch]h sync icbi (to any address) isync}hj\sbah}(h]h ]h"]h$]h&]j&j'uh1jhhhKhjKubeh}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hPPC_FEATURE_ARCH_2_05 The processor supports the v2.05 userlevel architecture. Processors supporting later architectures DO NOT set this feature. h](j)}(hPPC_FEATURE_ARCH_2_05h]hPPC_FEATURE_ARCH_2_05}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjvubj)}(hhh]h)}(h{The processor supports the v2.05 userlevel architecture. Processors supporting later architectures DO NOT set this feature.h]h{The processor supports the v2.05 userlevel architecture. Processors supporting later architectures DO NOT set this feature.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(h(PPC_FEATURE_PA6T The processor is PA6T. h](j)}(hPPC_FEATURE_PA6Th]hPPC_FEATURE_PA6T}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hThe processor is PA6T.h]hThe processor is PA6T.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(h/PPC_FEATURE_HAS_DFP DFP facility is available. h](j)}(hPPC_FEATURE_HAS_DFPh]hPPC_FEATURE_HAS_DFP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hDFP facility is available.h]hDFP facility is available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(h0PPC_FEATURE_POWER6_EXT The processor is POWER6. h](j)}(hPPC_FEATURE_POWER6_EXTh]hPPC_FEATURE_POWER6_EXT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hThe processor is POWER6.h]hThe processor is POWER6.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hPPC_FEATURE_ARCH_2_06 The processor supports the v2.06 userlevel architecture. Processors supporting later architectures also set this feature. h](j)}(hPPC_FEATURE_ARCH_2_06h]hPPC_FEATURE_ARCH_2_06}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj2ubj)}(hhh]h)}(hyThe processor supports the v2.06 userlevel architecture. Processors supporting later architectures also set this feature.h]hyThe processor supports the v2.06 userlevel architecture. Processors supporting later architectures also set this feature.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjDubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(h/PPC_FEATURE_HAS_VSX VSX facility is available. h](j)}(hPPC_FEATURE_HAS_VSXh]hPPC_FEATURE_HAS_VSX}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjaubj)}(hhh]h)}(hVSX facility is available.h]hVSX facility is available.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjsubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hiPPC_FEATURE_PSERIES_PERFMON_COMPAT The processor supports architected PMU events in the range 0xE0-0xFF. h](j)}(h"PPC_FEATURE_PSERIES_PERFMON_COMPATh]h"PPC_FEATURE_PSERIES_PERFMON_COMPAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hEThe processor supports architected PMU events in the range 0xE0-0xFF.h]hEThe processor supports architected PMU events in the range 0xE0-0xFF.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hDPPC_FEATURE_TRUE_LE The processor supports true little-endian mode. h](j)}(hPPC_FEATURE_TRUE_LEh]hPPC_FEATURE_TRUE_LE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(h/The processor supports true little-endian mode.h]h/The processor supports true little-endian mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hX PPC_FEATURE_PPC_LE The processor supports "PowerPC Little-Endian", that uses address munging to make storage access appear to be little-endian, but the data is stored in a different format that is unsuitable to be accessed by other agents not running in this mode. h](j)}(hPPC_FEATURE_PPC_LEh]hPPC_FEATURE_PPC_LE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hThe processor supports "PowerPC Little-Endian", that uses address munging to make storage access appear to be little-endian, but the data is stored in a different format that is unsuitable to be accessed by other agents not running in this mode.h]hThe processor supports “PowerPC Little-Endian”, that uses address munging to make storage access appear to be little-endian, but the data is stored in a different format that is unsuitable to be accessed by other agents not running in this mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]the-hwcaps-exposed-in-at-hwcapah ]h"]!5. the hwcaps exposed in at_hwcapah$]h&]uh1hhhhhhhhKGubh)}(hhh](h)}(h"6. The HWCAPs exposed in AT_HWCAP2h]h"6. The HWCAPs exposed in AT_HWCAP2}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhKubj)}(hhh](j)}(hPPC_FEATURE2_ARCH_2_07 The processor supports the v2.07 userlevel architecture. Processors supporting later architectures also set this feature. h](j)}(hPPC_FEATURE2_ARCH_2_07h]hPPC_FEATURE2_ARCH_2_07}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj?ubj)}(hhh]h)}(hyThe processor supports the v2.07 userlevel architecture. Processors supporting later architectures also set this feature.h]hyThe processor supports the v2.07 userlevel architecture. Processors supporting later architectures also set this feature.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjQubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj<ubj)}(h error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehÌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}h]hasnameids}(j hj j jWjTj~j{jjjjj(j%j j u nametypes}(j j jWj~jjj(j uh}(hhj hjThj{jZjjjjj%jj j+u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages]hsystem_message)}(hhh]h)}(hhh]h8Hyperlink target "elf-hwcaps-powerpc" is not referenced.}hj sbah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehÌlineKuh1j uba transformerN include_log] decorationNhhub.