€•WU      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ%/translations/zh_CN/arch/powerpc/dscr”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/zh_TW/arch/powerpc/dscr”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/it_IT/arch/powerpc/dscr”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/ja_JP/arch/powerpc/dscr”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/ko_KR/arch/powerpc/dscr”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ%/translations/sp_SP/arch/powerpc/dscr”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ#DSCR (Data Stream Control Register)”h]”hŒ#DSCR (Data Stream Control Register)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒ?/var/lib/git/docbuild/linux/Documentation/arch/powerpc/dscr.rst”h KubhŒ	paragraph”“”)”}”(hX  DSCR register in powerpc allows user to have some control of prefetch of data
stream in the processor. Please refer to the ISA documents or related manual
for more detailed information regarding how to use this DSCR to attain this
control of the prefetches . This document here provides an overview of kernel
support for DSCR, related kernel objects, its functionalities and exported
user interface.”h]”hX  DSCR register in powerpc allows user to have some control of prefetch of data
stream in the processor. Please refer to the ISA documents or related manual
for more detailed information regarding how to use this DSCR to attain this
control of the prefetches . This document here provides an overview of kernel
support for DSCR, related kernel objects, its functionalities and exported
user interface.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒenumerated_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX?  Data Structures:

    (1) thread_struct::

            dscr            /* Thread DSCR value */
            dscr_inherit    /* Thread has changed default DSCR */

    (2) PACA::

            dscr_default    /* per-CPU DSCR default value */

    (3) sysfs.c::

            dscr_default    /* System DSCR default value */
”h]”(h¸)”}”(hŒData Structures:”h]”hŒData Structures:”…””}”(hhÒhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÎubhŒblock_quote”“”)”}”(hX  (1) thread_struct::

        dscr            /* Thread DSCR value */
        dscr_inherit    /* Thread has changed default DSCR */

(2) PACA::

        dscr_default    /* per-CPU DSCR default value */

(3) sysfs.c::

        dscr_default    /* System DSCR default value */
”h]”hÈ)”}”(hhh]”(hÍ)”}”(hŒwthread_struct::

    dscr            /* Thread DSCR value */
    dscr_inherit    /* Thread has changed default DSCR */
”h]”(h¸)”}”(hŒthread_struct::”h]”hŒthread_struct:”…””}”(hhíhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhéubhŒliteral_block”“”)”}”(hŒ]dscr            /* Thread DSCR value */
dscr_inherit    /* Thread has changed default DSCR */”h]”hŒ]dscr            /* Thread DSCR value */
dscr_inherit    /* Thread has changed default DSCR */”…””}”hhýsbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hûhŸh¶h Khhéubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhæubhÍ)”}”(hŒ=PACA::

    dscr_default    /* per-CPU DSCR default value */
”h]”(h¸)”}”(hŒPACA::”h]”hŒPACA:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  ubhü)”}”(hŒ0dscr_default    /* per-CPU DSCR default value */”h]”hŒ0dscr_default    /* per-CPU DSCR default value */”…””}”hj%  sbah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hûhŸh¶h Khj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhæubhÍ)”}”(hŒ?sysfs.c::

    dscr_default    /* System DSCR default value */
”h]”(h¸)”}”(hŒ	sysfs.c::”h]”hŒsysfs.c:”…””}”(hj=  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj9  ubhü)”}”(hŒ/dscr_default    /* System DSCR default value */”h]”hŒ/dscr_default    /* System DSCR default value */”…””}”hjK  sbah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hûhŸh¶h Khj9  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhæubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”Œ(”Œsuffix”Œ)”uh1hÇhhâubah}”(h]”h ]”h"]”h$]”h&]”uh1hàhŸh¶h KhhÎubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hX  Scheduler Changes:

    Scheduler will write the per-CPU DSCR default which is stored in the
    CPU's PACA value into the register if the thread has dscr_inherit value
    cleared which means that it has not changed the default DSCR till now.
    If the dscr_inherit value is set which means that it has changed the
    default DSCR value, scheduler will write the changed value which will
    now be contained in thread struct's dscr into the register instead of
    the per-CPU default PACA based DSCR value.

    NOTE: Please note here that the system wide global DSCR value never
    gets used directly in the scheduler process context switch at all.
”h]”(h¸)”}”(hŒScheduler Changes:”h]”hŒScheduler Changes:”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjw  ubhá)”}”(hXX  Scheduler will write the per-CPU DSCR default which is stored in the
CPU's PACA value into the register if the thread has dscr_inherit value
cleared which means that it has not changed the default DSCR till now.
If the dscr_inherit value is set which means that it has changed the
default DSCR value, scheduler will write the changed value which will
now be contained in thread struct's dscr into the register instead of
the per-CPU default PACA based DSCR value.

NOTE: Please note here that the system wide global DSCR value never
gets used directly in the scheduler process context switch at all.
”h]”(h¸)”}”(hXÏ  Scheduler will write the per-CPU DSCR default which is stored in the
CPU's PACA value into the register if the thread has dscr_inherit value
cleared which means that it has not changed the default DSCR till now.
If the dscr_inherit value is set which means that it has changed the
default DSCR value, scheduler will write the changed value which will
now be contained in thread struct's dscr into the register instead of
the per-CPU default PACA based DSCR value.”h]”hXÓ  Scheduler will write the per-CPU DSCR default which is stored in the
CPUâ€™s PACA value into the register if the thread has dscr_inherit value
cleared which means that it has not changed the default DSCR till now.
If the dscr_inherit value is set which means that it has changed the
default DSCR value, scheduler will write the changed value which will
now be contained in thread structâ€™s dscr into the register instead of
the per-CPU default PACA based DSCR value.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj‰  ubh¸)”}”(hŒ†NOTE: Please note here that the system wide global DSCR value never
gets used directly in the scheduler process context switch at all.”h]”hŒ†NOTE: Please note here that the system wide global DSCR value never
gets used directly in the scheduler process context switch at all.”…””}”(hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K%hj‰  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hàhŸh¶h Khjw  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hXÑ  SYSFS Interface:

    - Global DSCR default:          /sys/devices/system/cpu/dscr_default
    - CPU specific DSCR default:    /sys/devices/system/cpu/cpuN/dscr

    Changing the global DSCR default in the sysfs will change all the CPU
    specific DSCR defaults immediately in their PACA structures. Again if
    the current process has the dscr_inherit clear, it also writes the new
    value into every CPU's DSCR register right away and updates the current
    thread's DSCR value as well.

    Changing the CPU specific DSCR default value in the sysfs does exactly
    the same thing as above but unlike the global one above, it just changes
    stuff for that particular CPU instead for all the CPUs on the system.
”h]”(h¸)”}”(hŒSYSFS Interface:”h]”hŒSYSFS Interface:”…””}”(hj¹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K(hjµ  ubhá)”}”(hX—  - Global DSCR default:          /sys/devices/system/cpu/dscr_default
- CPU specific DSCR default:    /sys/devices/system/cpu/cpuN/dscr

Changing the global DSCR default in the sysfs will change all the CPU
specific DSCR defaults immediately in their PACA structures. Again if
the current process has the dscr_inherit clear, it also writes the new
value into every CPU's DSCR register right away and updates the current
thread's DSCR value as well.

Changing the CPU specific DSCR default value in the sysfs does exactly
the same thing as above but unlike the global one above, it just changes
stuff for that particular CPU instead for all the CPUs on the system.
”h]”(hŒbullet_list”“”)”}”(hhh]”(hÍ)”}”(hŒBGlobal DSCR default:          /sys/devices/system/cpu/dscr_default”h]”h¸)”}”(hjÒ  h]”hŒBGlobal DSCR default:          /sys/devices/system/cpu/dscr_default”…””}”(hjÔ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K*hjÐ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÍ  ubhÍ)”}”(hŒ@CPU specific DSCR default:    /sys/devices/system/cpu/cpuN/dscr
”h]”h¸)”}”(hŒ?CPU specific DSCR default:    /sys/devices/system/cpu/cpuN/dscr”h]”hŒ?CPU specific DSCR default:    /sys/devices/system/cpu/cpuN/dscr”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K+hjç  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÍ  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jË  hŸh¶h K*hjÇ  ubh¸)”}”(hX7  Changing the global DSCR default in the sysfs will change all the CPU
specific DSCR defaults immediately in their PACA structures. Again if
the current process has the dscr_inherit clear, it also writes the new
value into every CPU's DSCR register right away and updates the current
thread's DSCR value as well.”h]”hX;  Changing the global DSCR default in the sysfs will change all the CPU
specific DSCR defaults immediately in their PACA structures. Again if
the current process has the dscr_inherit clear, it also writes the new
value into every CPUâ€™s DSCR register right away and updates the current
threadâ€™s DSCR value as well.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K-hjÇ  ubh¸)”}”(hŒÕChanging the CPU specific DSCR default value in the sysfs does exactly
the same thing as above but unlike the global one above, it just changes
stuff for that particular CPU instead for all the CPUs on the system.”h]”hŒÕChanging the CPU specific DSCR default value in the sysfs does exactly
the same thing as above but unlike the global one above, it just changes
stuff for that particular CPU instead for all the CPUs on the system.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K3hjÇ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hàhŸh¶h K*hjµ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hX›  User Space Instructions:

    The DSCR register can be accessed in the user space using any of these
    two SPR numbers available for that purpose.

    (1) Problem state SPR:          0x03    (Un-privileged, POWER8 only)
    (2) Privileged state SPR:       0x11    (Privileged)

    Accessing DSCR through privileged SPR number (0x11) from user space
    works, as it is emulated following an illegal instruction exception
    inside the kernel. Both mfspr and mtspr instructions are emulated.

    Accessing DSCR through user level SPR (0x03) from user space will first
    create a facility unavailable exception. Inside this exception handler
    all mfspr instruction based read attempts will get emulated and returned
    where as the first mtspr instruction based write attempts will enable
    the DSCR facility for the next time around (both for read and write) by
    setting DSCR facility in the FSCR register.
”h]”(h¸)”}”(hŒUser Space Instructions:”h]”hŒUser Space Instructions:”…””}”(hj3  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K7hj/  ubhá)”}”(hXM  The DSCR register can be accessed in the user space using any of these
two SPR numbers available for that purpose.

(1) Problem state SPR:          0x03    (Un-privileged, POWER8 only)
(2) Privileged state SPR:       0x11    (Privileged)

Accessing DSCR through privileged SPR number (0x11) from user space
works, as it is emulated following an illegal instruction exception
inside the kernel. Both mfspr and mtspr instructions are emulated.

Accessing DSCR through user level SPR (0x03) from user space will first
create a facility unavailable exception. Inside this exception handler
all mfspr instruction based read attempts will get emulated and returned
where as the first mtspr instruction based write attempts will enable
the DSCR facility for the next time around (both for read and write) by
setting DSCR facility in the FSCR register.
”h]”(h¸)”}”(hŒrThe DSCR register can be accessed in the user space using any of these
two SPR numbers available for that purpose.”h]”hŒrThe DSCR register can be accessed in the user space using any of these
two SPR numbers available for that purpose.”…””}”(hjE  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K9hjA  ubhÈ)”}”(hhh]”(hÍ)”}”(hŒ@Problem state SPR:          0x03    (Un-privileged, POWER8 only)”h]”h¸)”}”(hjX  h]”hŒ@Problem state SPR:          0x03    (Un-privileged, POWER8 only)”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K<hjV  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjS  ubhÍ)”}”(hŒ1Privileged state SPR:       0x11    (Privileged)
”h]”h¸)”}”(hŒ0Privileged state SPR:       0x11    (Privileged)”h]”hŒ0Privileged state SPR:       0x11    (Privileged)”…””}”(hjq  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K=hjm  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjS  ubeh}”(h]”h ]”h"]”h$]”h&]”je  jf  jg  jh  ji  jj  uh1hÇhjA  ubh¸)”}”(hŒÊAccessing DSCR through privileged SPR number (0x11) from user space
works, as it is emulated following an illegal instruction exception
inside the kernel. Both mfspr and mtspr instructions are emulated.”h]”hŒÊAccessing DSCR through privileged SPR number (0x11) from user space
works, as it is emulated following an illegal instruction exception
inside the kernel. Both mfspr and mtspr instructions are emulated.”…””}”(hj‹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K?hjA  ubh¸)”}”(hX‘  Accessing DSCR through user level SPR (0x03) from user space will first
create a facility unavailable exception. Inside this exception handler
all mfspr instruction based read attempts will get emulated and returned
where as the first mtspr instruction based write attempts will enable
the DSCR facility for the next time around (both for read and write) by
setting DSCR facility in the FSCR register.”h]”hX‘  Accessing DSCR through user level SPR (0x03) from user space will first
create a facility unavailable exception. Inside this exception handler
all mfspr instruction based read attempts will get emulated and returned
where as the first mtspr instruction based write attempts will enable
the DSCR facility for the next time around (both for read and write) by
setting DSCR facility in the FSCR register.”…””}”(hj™  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KChjA  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hàhŸh¶h K9hj/  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hXv  Specifics about 'dscr_inherit':

    The thread struct element 'dscr_inherit' represents whether the thread
    in question has attempted and changed the DSCR itself using any of the
    following methods. This element signifies whether the thread wants to
    use the CPU default DSCR value or its own changed DSCR value in the
    kernel.

            (1) mtspr instruction   (SPR number 0x03)
            (2) mtspr instruction   (SPR number 0x11)
            (3) ptrace interface    (Explicitly set user DSCR value)

    Any child of the process created after this event in the process inherits
    this same behaviour as well.”h]”(h¸)”}”(hŒSpecifics about 'dscr_inherit':”h]”hŒ#Specifics about â€˜dscr_inheritâ€™:”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KJhj³  ubhá)”}”(hX-  The thread struct element 'dscr_inherit' represents whether the thread
in question has attempted and changed the DSCR itself using any of the
following methods. This element signifies whether the thread wants to
use the CPU default DSCR value or its own changed DSCR value in the
kernel.

        (1) mtspr instruction   (SPR number 0x03)
        (2) mtspr instruction   (SPR number 0x11)
        (3) ptrace interface    (Explicitly set user DSCR value)

Any child of the process created after this event in the process inherits
this same behaviour as well.”h]”(h¸)”}”(hX  The thread struct element 'dscr_inherit' represents whether the thread
in question has attempted and changed the DSCR itself using any of the
following methods. This element signifies whether the thread wants to
use the CPU default DSCR value or its own changed DSCR value in the
kernel.”h]”hX#  The thread struct element â€˜dscr_inheritâ€™ represents whether the thread
in question has attempted and changed the DSCR itself using any of the
following methods. This element signifies whether the thread wants to
use the CPU default DSCR value or its own changed DSCR value in the
kernel.”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KLhjÅ  ubhá)”}”(hŒ(1) mtspr instruction   (SPR number 0x03)
(2) mtspr instruction   (SPR number 0x11)
(3) ptrace interface    (Explicitly set user DSCR value)
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”h]”h¸)”}”(hŒ4ptrace interface    (Explicitly set user DSCR value)”h]”hŒ4ptrace interface    (Explicitly set user DSCR value)”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KThj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÛ  ubeh}”(h]”h ]”h"]”h$]”h&]”je  jf  jg  jh  ji  jj  uh1hÇhj×  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hàhŸh¶h KRhjÅ  ubh¸)”}”(hŒfAny child of the process created after this event in the process inherits
this same behaviour as well.”h]”hŒfAny child of the process created after this event in the process inherits
this same behaviour as well.”…””}”(hj0  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KVhjÅ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hàhŸh¶h KLhj³  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”je  Œ
upperalpha”jg  jh  ji  jj  uh1hÇhh£hžhhŸh¶h Kubeh}”(h]”Œ!dscr-data-stream-control-register”ah ]”h"]”Œ#dscr (data stream control register)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
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id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.