Yasphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget//translations/zh_CN/arch/openrisc/openrisc_portmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/zh_TW/arch/openrisc/openrisc_portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/it_IT/arch/openrisc/openrisc_portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ja_JP/arch/openrisc/openrisc_portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ko_KR/arch/openrisc/openrisc_portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/sp_SP/arch/openrisc/openrisc_portmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hOpenRISC Linuxh]hOpenRISC Linux}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhI/var/lib/git/docbuild/linux/Documentation/arch/openrisc/openrisc_port.rsthKubh paragraph)}(hThis is a port of Linux to the OpenRISC class of microprocessors; the initial target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).h]hThis is a port of Linux to the OpenRISC class of microprocessors; the initial target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hBFor information about OpenRISC processors and ongoing development:h]hBFor information about OpenRISC processors and ongoing development:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(h======= ============================== website https://openrisc.io email linux-openrisc@vger.kernel.org ======= ============================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1hhhubh)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1hhhubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hwebsiteh]hwebsite}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hhttps://openrisc.ioh]h reference)}(hj#h]hhttps://openrisc.io}(hj'hhhNhNubah}(h]h ]h"]h$]h&]refurij#uh1j%hj!ubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhubj)}(hhh](j)}(hhh]h)}(hemailh]hemail}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjJubah}(h]h ]h"]h$]h&]uh1jhjGubj)}(hhh]h)}(hlinux-openrisc@vger.kernel.orgh]j&)}(hjfh]hlinux-openrisc@vger.kernel.org}(hjhhhhNhNubah}(h]h ]h"]h$]h&]refuri%mailto:linux-openrisc@vger.kernel.orguh1j%hjdubah}(h]h ]h"]h$]h&]uh1hhhhK hjaubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]colsKuh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh transition)}(hE---------------------------------------------------------------------h]h}(h]h ]h"]h$]h&]uh1jhhhKhhhhubh)}(hhh](h)}(h3Build instructions for OpenRISC toolchain and Linuxh]h3Build instructions for OpenRISC toolchain and Linux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hIn order to build and run Linux for OpenRISC, you'll need at least a basic toolchain and, perhaps, the architectural simulator. Steps to get these bits in place are outlined here.h]hIn order to build and run Linux for OpenRISC, you’ll need at least a basic toolchain and, perhaps, the architectural simulator. Steps to get these bits in place are outlined here.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhenumerated_list)}(hhh]h list_item)}(h Toolchain h]h)}(h Toolchainh]h Toolchain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubah}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1jhjhhhhhKubh)}(hToolchain binaries can be obtained from openrisc.io or our github releases page. Instructions for building the different toolchains can be found on openrisc.io or Stafford's toolchain build and release scripts.h]hToolchain binaries can be obtained from openrisc.io or our github releases page. Instructions for building the different toolchains can be found on openrisc.io or Stafford’s toolchain build and release scripts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXP========== ========================================================== binaries https://github.com/stffrdhrn/or1k-toolchain-build/releases toolchains https://openrisc.io/software building https://github.com/stffrdhrn/or1k-toolchain-build ========== ========================================================== h]h)}(hhh]h)}(hhh](h)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1hhj ubh)}(hhh]h}(h]h ]h"]h$]h&]colwidthK:uh1hhj ubh)}(hhh](j)}(hhh](j)}(hhh]h)}(hbinariesh]hbinaries}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj)ubah}(h]h ]h"]h$]h&]uh1jhj&ubj)}(hhh]h)}(h:https://github.com/stffrdhrn/or1k-toolchain-build/releasesh]j&)}(hjEh]h:https://github.com/stffrdhrn/or1k-toolchain-build/releases}(hjGhhhNhNubah}(h]h ]h"]h$]h&]refurijEuh1j%hjCubah}(h]h ]h"]h$]h&]uh1hhhhKhj@ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh](j)}(hhh]h)}(h toolchainsh]h toolchains}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh]h)}(hhttps://openrisc.io/softwareh]j&)}(hjh]hhttps://openrisc.io/software}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j%hjubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh](j)}(hhh]h)}(hbuildingh]hbuilding}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h1https://github.com/stffrdhrn/or1k-toolchain-buildh]j&)}(hjh]h1https://github.com/stffrdhrn/or1k-toolchain-build}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j%hjubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]colsKuh1hhj ubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh]j)}(h Building h]h)}(hBuildingh]hBuilding}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubah}(h]h ]h"]h$]h&]jjjhjjstartKuh1jhjhhhhhK$ubh)}(h!Build the Linux kernel as usual::h]h Build the Linux kernel as usual:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh literal_block)}(hgmake ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig make ARCH=openrisc CROSS_COMPILE="or1k-linux-"h]hgmake ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig make ARCH=openrisc CROSS_COMPILE="or1k-linux-"}hj4sbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1j2hhhK(hjhhubj)}(hhh]j)}(hRunning on FPGA (optional) h]h)}(hRunning on FPGA (optional)h]hRunning on FPGA (optional)}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjGubah}(h]h ]h"]h$]h&]uh1jhjDhhhhhNubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jhjhhhhhK+ubh)}(hXmThe OpenRISC community typically uses FuseSoC to manage building and programming an SoC into an FPGA. The below is an example of programming a De0 Nano development board with the OpenRISC SoC. During the build FPGA RTL is code downloaded from the FuseSoC IP cores repository and built using the FPGA vendor tools. Binaries are loaded onto the board with openocd.h]hXmThe OpenRISC community typically uses FuseSoC to manage building and programming an SoC into an FPGA. The below is an example of programming a De0 Nano development board with the OpenRISC SoC. During the build FPGA RTL is code downloaded from the FuseSoC IP cores repository and built using the FPGA vendor tools. Binaries are loaded onto the board with openocd.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjhhubj3)}(hXgit clone https://github.com/olofk/fusesoc cd fusesoc sudo pip install -e . fusesoc init fusesoc build de0_nano fusesoc pgm de0_nano openocd -f interface/altera-usb-blaster.cfg \ -f board/or1k_generic.cfg telnet localhost 4444 > init > halt; load_image vmlinux ; reseth]hXgit clone https://github.com/olofk/fusesoc cd fusesoc sudo pip install -e . fusesoc init fusesoc build de0_nano fusesoc pgm de0_nano openocd -f interface/altera-usb-blaster.cfg \ -f board/or1k_generic.cfg telnet localhost 4444 > init > halt; load_image vmlinux ; reset}hjssbah}(h]h ]h"]h$]h&]jBjCuh1j2hhhK5hjhhubj)}(hhh]j)}(h"Running on a Simulator (optional) h]h)}(h!Running on a Simulator (optional)h]h!Running on a Simulator (optional)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jhjhhhhhKDubh)}(hXQEMU is a processor emulator which we recommend for simulating the OpenRISC platform. Please follow the OpenRISC instructions on the QEMU website to get Linux running on QEMU. You can build QEMU yourself, but your Linux distribution likely provides binary packages to support OpenRISC.h]hXQEMU is a processor emulator which we recommend for simulating the OpenRISC platform. Please follow the OpenRISC instructions on the QEMU website to get Linux running on QEMU. You can build QEMU yourself, but your Linux distribution likely provides binary packages to support OpenRISC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjhhubh)}(h============= ====================================================== qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC ============= ====================================================== h]h)}(hhh]h)}(hhh](h)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1hhjubh)}(hhh]h}(h]h ]h"]h$]h&]colwidthK6uh1hhjubh)}(hhh]j)}(hhh](j)}(hhh]h)}(h qemu openrisch]h qemu openrisc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6https://wiki.qemu.org/Documentation/Platforms/OpenRISCh]j&)}(hjh]h6https://wiki.qemu.org/Documentation/Platforms/OpenRISC}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j%hjubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]colsKuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKKhjhhubeh}(h]3build-instructions-for-openrisc-toolchain-and-linuxah ]h"]3build instructions for openrisc toolchain and linuxah$]h&]uh1hhhhhhhhKubj)}(hE---------------------------------------------------------------------h]h}(h]h ]h"]h$]h&]uh1jhhhKOhhhhubh)}(hhh](h)}(h Terminologyh]h Terminology}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhKRubh)}(hIn the code, the following particles are used on symbols to limit the scope to more or less specific processor implementations:h]hIn the code, the following particles are used on symbols to limit the scope to more or less specific processor implementations:}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThj=hhubh)}(hhh]h)}(hhh](h)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1hhj_ubh)}(hhh]h}(h]h ]h"]h$]h&]colwidthK'uh1hhj_ubh)}(hhh](j)}(hhh](j)}(hhh]h)}(h openrisc:h]h openrisc:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj|ubah}(h]h ]h"]h$]h&]uh1jhjyubj)}(hhh]h)}(h the OpenRISC class of processorsh]h the OpenRISC class of processors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh](j)}(hhh]h)}(hor1k:h]hor1k:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&the OpenRISC 1000 family of processorsh]h&the OpenRISC 1000 family of processors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh](j)}(hhh]h)}(hor1200:h]hor1200:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hthe OpenRISC 1200 processorh]hthe OpenRISC 1200 processor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1hhj_ubeh}(h]h ]h"]h$]h&]colsKuh1hhj\ubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhNubeh}(h] terminologyah ]h"] terminologyah$]h&]uh1hhhhhhhhKRubj)}(hE---------------------------------------------------------------------h]h}(h]h ]h"]h$]h&]uh1jhhhK]hhhhubh)}(hhh](h)}(hHistoryh]hHistory}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChhhhhK`ubhdefinition_list)}(hhh](hdefinition_list_item)}(h18-11-2003 Matjaz Breskvar (phoenix@bsemi.com) initial port of linux to OpenRISC/or32 architecture. all the core stuff is implemented and seams usable. h](hterm)}(h318-11-2003 Matjaz Breskvar (phoenix@bsemi.com)h](h!18-11-2003 Matjaz Breskvar (}(hjahhhNhNubj&)}(hphoenix@bsemi.comh]hphoenix@bsemi.com}(hjihhhNhNubah}(h]h ]h"]h$]h&]refurimailto:phoenix@bsemi.comuh1j%hjaubh)}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1j_hhhKdhj[ubh definition)}(hhh]h)}(hhinitial port of linux to OpenRISC/or32 architecture. all the core stuff is implemented and seams usable.h]hhinitial port of linux to OpenRISC/or32 architecture. all the core stuff is implemented and seams usable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchjubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jYhhhKdhjVubjZ)}(h08-12-2003 Matjaz Breskvar (phoenix@bsemi.com) complete change of TLB miss handling. rewrite of exceptions handling. fully functional sash-3.6 in default initrd. a much improved version with changes all around. h](j`)}(h308-12-2003 Matjaz Breskvar (phoenix@bsemi.com)h](h!08-12-2003 Matjaz Breskvar (}(hjhhhNhNubj&)}(hphoenix@bsemi.comh]hphoenix@bsemi.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:phoenix@bsemi.comuh1j%hjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j_hhhKjhjubj)}(hhh]h)}(hcomplete change of TLB miss handling. rewrite of exceptions handling. fully functional sash-3.6 in default initrd. a much improved version with changes all around.h]hcomplete change of TLB miss handling. rewrite of exceptions handling. fully functional sash-3.6 in default initrd. a much improved version with changes all around.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jYhhhKjhjVhhubjZ)}(h10-04-2004 Matjaz Breskvar (phoenix@bsemi.com) a lot of bugfixes all over. ethernet support, functional http and telnet servers. running many standard linux apps. h](j`)}(h310-04-2004 Matjaz Breskvar (phoenix@bsemi.com)h](h!10-04-2004 Matjaz Breskvar (}(hjhhhNhNubj&)}(hphoenix@bsemi.comh]hphoenix@bsemi.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:phoenix@bsemi.comuh1j%hjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j_hhhKohjubj)}(hhh]h)}(hsa lot of bugfixes all over. ethernet support, functional http and telnet servers. running many standard linux apps.h]hsa lot of bugfixes all over. ethernet support, functional http and telnet servers. running many standard linux apps.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jYhhhKohjVhhubjZ)}(hB26-06-2004 Matjaz Breskvar (phoenix@bsemi.com) port to 2.6.x h](j`)}(h326-06-2004 Matjaz Breskvar (phoenix@bsemi.com)h](h!26-06-2004 Matjaz Breskvar (}(hj,hhhNhNubj&)}(hphoenix@bsemi.comh]hphoenix@bsemi.com}(hj4hhhNhNubah}(h]h ]h"]h$]h&]refurimailto:phoenix@bsemi.comuh1j%hj,ubh)}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1j_hhhKrhj(ubj)}(hhh]h)}(h port to 2.6.xh]h port to 2.6.x}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjNubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jYhhhKrhjVhhubjZ)}(h{30-11-2004 Matjaz Breskvar (phoenix@bsemi.com) lots of bugfixes and enhancements. added opencores framebuffer driver. h](j`)}(h330-11-2004 Matjaz Breskvar (phoenix@bsemi.com)h](h!30-11-2004 Matjaz Breskvar (}(hjohhhNhNubj&)}(hphoenix@bsemi.comh]hphoenix@bsemi.com}(hjwhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:phoenix@bsemi.comuh1j%hjoubh)}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1j_hhhKvhjkubj)}(hhh]h)}(hFlots of bugfixes and enhancements. added opencores framebuffer driver.h]hFlots of bugfixes and enhancements. added opencores framebuffer driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jYhhhKvhjVhhubjZ)}(hi09-10-2010 Jonas Bonn (jonas@southpole.se) major rewrite to bring up to par with upstream Linux 2.6.36h](j`)}(h-09-10-2010 Jonas Bonn (jonas@southpole.se)h](h09-10-2010 Jonas Bonn (}(hjhhhNhNubj&)}(hjonas@southpole.seh]hjonas@southpole.se}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:jonas@southpole.seuh1j%hjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j_hhhKxhjubj)}(hhh]h)}(h;major rewrite to bring up to par with upstream Linux 2.6.36h]h;major rewrite to bring up to par with upstream Linux 2.6.36}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jYhhhKxhjVhhubeh}(h]h ]h"]h$]h&]uh1jThjChhhhhNubeh}(h]historyah ]h"]historyah$]h&]uh1hhhhhhhhK`ubeh}(h]openrisc-linuxah ]h"]openrisc linuxah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj)error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjj0j-j6j3jju nametypes}(jj0j6juh}(jhj-jj3j=jjCu footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages](hsystem_message)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "2" (ordinal 2)h]h>Enumerated list start value not ordinal-1: “2” (ordinal 2)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1jhjhhhhhK$ubj)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "3" (ordinal 3)h]h>Enumerated list start value not ordinal-1: “3” (ordinal 3)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypejsourcehlineKuh1jhjhhhhhK+ubj)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "4" (ordinal 4)h]h>Enumerated list start value not ordinal-1: “4” (ordinal 4)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypejsourcehlineKuh1jhjhhhhhKDubetransform_messages] transformerN include_log] decorationNhhub.