€•"MŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ)/translations/zh_CN/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ)/translations/zh_TW/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ)/translations/it_IT/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ)/translations/ja_JP/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ)/translations/ko_KR/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ)/translations/pt_BR/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ)/translations/sp_SP/arch/mips/ingenic-tcu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³ŒC/var/lib/git/docbuild/linux/Documentation/arch/mips/ingenic-tcu.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ/Ingenic JZ47xx SoCs Timer/Counter Unit hardware”h]”hŒ/Ingenic JZ47xx SoCs Timer/Counter Unit hardware”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hŒ§The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function hardware block. It features up to eight channels, that can be used as counters, timers, or PWM.”h]”hŒ§The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function hardware block. It features up to eight channels, that can be used as counters, timers, or PWM.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ\JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels. ”h]”hÞ)”}”(hŒ[JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels.”h]”hŒ[JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels.”…””}”(hhøh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hhôubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hŒ“JZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 64-bit. ”h]”hÞ)”}”(hŒ’JZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 64-bit.”h]”hŒ’JZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 64-bit.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hX€Each one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. - The watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space. - The TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. ”h]”(hÞ)”}”(hŒ¦Each one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.”h]”hŒ¦Each one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.”…””}”(hj(h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj$ubhŒ block_quote”“”)”}”(hŒÐ- The watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space. - The TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. ”h]”hî)”}”(hhh]”(hó)”}”(hŒoThe watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space.”h]”hÞ)”}”(hŒoThe watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space.”h]”hŒoThe watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space.”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj?ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj<ubhó)”}”(hŒXThe TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. ”h]”hÞ)”}”(hŒWThe TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks.”h]”hŒWThe TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks.”…””}”(hj[h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhjWubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj<ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1híh³hÇh´Khj8ubah}”(h]”h ]”h"]”h$]”h&]”uh1j6h³hÇh´Khj$ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hŒøEach TCU channel works in one of two modes: - mode TCU1: channels cannot work in sleep mode, but are easier to operate. - mode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. ”h]”(hÞ)”}”(hŒ+Each TCU channel works in one of two modes:”h]”hŒ+Each TCU channel works in one of two modes:”…””}”(hj‡h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjƒubj7)”}”(hŒÃ- mode TCU1: channels cannot work in sleep mode, but are easier to operate. - mode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. ”h]”hî)”}”(hhh]”(hó)”}”(hŒImode TCU1: channels cannot work in sleep mode, but are easier to operate.”h]”hÞ)”}”(hŒImode TCU1: channels cannot work in sleep mode, but are easier to operate.”h]”hŒImode TCU1: channels cannot work in sleep mode, but are easier to operate.”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjœubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj™ubhó)”}”(hŒqmode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. ”h]”hÞ)”}”(hŒpmode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels.”h]”hŒpmode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels.”…””}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj´ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj™ubeh}”(h]”h ]”h"]”h$]”h&]”jujvuh1híh³hÇh´Khj•ubah}”(h]”h ]”h"]”h$]”h&]”uh1j6h³hÇh´Khjƒubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hX?The mode of each TCU channel depends on the SoC used: - On the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode. - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. ”h]”(hÞ)”}”(hŒ5The mode of each TCU channel depends on the SoC used:”h]”hŒ5The mode of each TCU channel depends on the SoC used:”…””}”(hjâh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K!hjÞubj7)”}”(hŒþ- On the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode. - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. ”h]”hî)”}”(hhh]”(hó)”}”(hŒROn the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode.”h]”hÞ)”}”(hŒROn the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode.”h]”hŒROn the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode.”…””}”(hjûh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K#hj÷ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjôubhó)”}”(hŒCOn JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.”h]”hÞ)”}”(hjh]”hŒCOn JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K%hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjôubhó)”}”(hŒ]On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. ”h]”hÞ)”}”(hŒ\On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1.”h]”hŒ\On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1.”…””}”(hj*h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K&hj&ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjôubeh}”(h]”h ]”h"]”h$]”h&]”jujvuh1híh³hÇh´K#hjðubah}”(h]”h ]”h"]”h$]”h&]”uh1j6h³hÇh´K#hjÞubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hXNEach channel can generate an interrupt. Some channels share an interrupt line, some don't, and this changes between SoC versions: - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line. - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line. - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. ”h]”(hÞ)”}”(hŒEach channel can generate an interrupt. Some channels share an interrupt line, some don't, and this changes between SoC versions:”h]”hŒƒEach channel can generate an interrupt. Some channels share an interrupt line, some don’t, and this changes between SoC versions:”…””}”(hjTh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K)hjPubj7)”}”(hX½- on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line. - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line. - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. ”h]”hî)”}”(hhh]”(hó)”}”(hŒ„on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line.”h]”hÞ)”}”(hŒ„on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line.”h]”hŒ„on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line.”…””}”(hjmh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K,hjiubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjfubhó)”}”(hŒyOn JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line.”h]”hÞ)”}”(hŒyOn JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line.”h]”hŒyOn JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line.”…””}”(hj…h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K.hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjfubhó)”}”(hŒ°on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. ”h]”hÞ)”}”(hŒ¯on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line.”h]”hŒ¯on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K0hj™ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjfubeh}”(h]”h ]”h"]”h$]”h&]”jujvuh1híh³hÇh´K,hjbubah}”(h]”h ]”h"]”h$]”h&]”uh1j6h³hÇh´K,hjPubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jujvuh1híh³hÇh´K hhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒImplementation”h]”hŒImplementation”…””}”(hjÌh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÉh²hh³hÇh´K5ubhÞ)”}”(hŒKThe functionalities of the TCU hardware are spread across multiple drivers:”h]”hŒKThe functionalities of the TCU hardware are spread across multiple drivers:”…””}”(hjÚh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K7hjÉh²hubhŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K uh1jòhjïubjó)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K#uh1jòhjïubhŒtbody”“”)”}”(hhh]”(hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”hÞ)”}”(hŒclocks”h]”hŒclocks”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K:hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj)”}”(hhh]”hÞ)”}”(hŒdrivers/clk/ingenic/tcu.c”h]”hŒdrivers/clk/ingenic/tcu.c”…””}”(hj.h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K:hj+ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubeh}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubj)”}”(hhh]”(j)”}”(hhh]”hÞ)”}”(hŒ interrupts”h]”hŒ interrupts”…””}”(hjNh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K;hjKubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjHubj)”}”(hhh]”hÞ)”}”(hŒ!drivers/irqchip/irq-ingenic-tcu.c”h]”hŒ!drivers/irqchip/irq-ingenic-tcu.c”…””}”(hjeh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K;hjbubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjHubeh}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubj)”}”(hhh]”(j)”}”(hhh]”hÞ)”}”(hŒtimers”h]”hŒtimers”…””}”(hj…h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjðubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjíubj)”}”(hhh]”hÞ)”}”(hŒdrivers/pwm/pwm-jz4740.c”h]”hŒdrivers/pwm/pwm-jz4740.c”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K>hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjíubeh}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubj)”}”(hhh]”(j)”}”(hhh]”hÞ)”}”(hŒwatchdog”h]”hŒwatchdog”…””}”(hj*h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K?hj'ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj$ubj)”}”(hhh]”hÞ)”}”(hŒdrivers/watchdog/jz4740_wdt.c”h]”hŒdrivers/watchdog/jz4740_wdt.c”…””}”(hjAh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K?hj>ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj$ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhjïubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jíhjêubah}”(h]”h ]”h"]”h$]”h&]”uh1jèhjÉh²hh³hÇh´NubhÞ)”}”(hŒÊBecause various functionalities of the TCU that belong to different drivers and frameworks can be controlled from the same registers, all of these drivers access their registers through the same regmap.”h]”hŒÊBecause various functionalities of the TCU that belong to different drivers and frameworks can be controlled from the same registers, all of these drivers access their registers through the same regmap.”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KBhjÉh²hubhÞ)”}”(hŒ“For more information regarding the devicetree bindings of the TCU drivers, have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.”h]”hŒ“For more information regarding the devicetree bindings of the TCU drivers, have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KFhjÉh²hubeh}”(h]”Œimplementation”ah ]”h"]”Œimplementation”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K5ubeh}”(h]”Œ/ingenic-jz47xx-socs-timer-counter-unit-hardware”ah ]”h"]”Œ/ingenic jz47xx socs timer/counter unit hardware”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ 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