GLsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/arch/mips/ingenic-tcumodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/arch/mips/ingenic-tcumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/arch/mips/ingenic-tcumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/arch/mips/ingenic-tcumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/arch/mips/ingenic-tcumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/arch/mips/ingenic-tcumodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/arch/mips/ingenic-tcu.rsthKubhsection)}(hhh](htitle)}(h/Ingenic JZ47xx SoCs Timer/Counter Unit hardwareh]h/Ingenic JZ47xx SoCs Timer/Counter Unit hardware}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function hardware block. It features up to eight channels, that can be used as counters, timers, or PWM.h]hThe Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function hardware block. It features up to eight channels, that can be used as counters, timers, or PWM.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h\JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels. h]h)}(h[JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels.h]h[JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hJZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 64-bit. h]h)}(hJZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 64-bit.h]hJZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 64-bit.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hXEach one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. - The watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space. - The TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. h](h)}(hEach one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.h]hEach one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh block_quote)}(h- The watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space. - The TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. h]h)}(hhh](h)}(hoThe watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space.h]h)}(hoThe watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space.h]hoThe watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ubah}(h]h ]h"]h$]h&]uh1hhj(ubh)}(hXThe TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. h]h)}(hWThe TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks.h]hWThe TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubah}(h]h ]h"]h$]h&]uh1hhj(ubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhKhj$ubah}(h]h ]h"]h$]h&]uh1j"hhhKhjubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hEach TCU channel works in one of two modes: - mode TCU1: channels cannot work in sleep mode, but are easier to operate. - mode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. h](h)}(h+Each TCU channel works in one of two modes:h]h+Each TCU channel works in one of two modes:}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjoubj#)}(h- mode TCU1: channels cannot work in sleep mode, but are easier to operate. - mode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. h]h)}(hhh](h)}(hImode TCU1: channels cannot work in sleep mode, but are easier to operate.h]h)}(hImode TCU1: channels cannot work in sleep mode, but are easier to operate.h]hImode TCU1: channels cannot work in sleep mode, but are easier to operate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hqmode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. h]h)}(hpmode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels.h]hpmode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jajbuh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j"hhhKhjoubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hX?The mode of each TCU channel depends on the SoC used: - On the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode. - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. h](h)}(h5The mode of each TCU channel depends on the SoC used:h]h5The mode of each TCU channel depends on the SoC used:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubj#)}(h- On the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode. - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. h]h)}(hhh](h)}(hROn the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode.h]h)}(hROn the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode.h]hROn the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hCOn JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.h]h)}(hjh]hCOn JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h]On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. h]h)}(h\On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1.h]h\On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jajbuh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1j"hhhK#hjubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hXNEach channel can generate an interrupt. Some channels share an interrupt line, some don't, and this changes between SoC versions: - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line. - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line. - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. h](h)}(hEach channel can generate an interrupt. Some channels share an interrupt line, some don't, and this changes between SoC versions:h]hEach channel can generate an interrupt. Some channels share an interrupt line, some don’t, and this changes between SoC versions:}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hj<ubj#)}(hX- on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line. - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line. - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. h]h)}(hhh](h)}(hon older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line.h]h)}(hon older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line.h]hon older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjUubah}(h]h ]h"]h$]h&]uh1hhjRubh)}(hyOn JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line.h]h)}(hyOn JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line.h]hyOn JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjmubah}(h]h ]h"]h$]h&]uh1hhjRubh)}(hon newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. h]h)}(hon newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line.h]hon newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1hhjRubeh}(h]h ]h"]h$]h&]jajbuh1hhhhK,hjNubah}(h]h ]h"]h$]h&]uh1j"hhhK,hj<ubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]jajbuh1hhhhK hhhhubh)}(hhh](h)}(hImplementationh]hImplementation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK5ubh)}(hKThe functionalities of the TCU hardware are spread across multiple drivers:h]hKThe functionalities of the TCU hardware are spread across multiple drivers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK#uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hclocksh]hclocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hdrivers/clk/ingenic/tcu.ch]hdrivers/clk/ingenic/tcu.c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h interruptsh]h interrupts}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj7ubah}(h]h ]h"]h$]h&]uh1jhj4ubj)}(hhh]h)}(h!drivers/irqchip/irq-ingenic-tcu.ch]h!drivers/irqchip/irq-ingenic-tcu.c}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjNubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htimersh]htimers}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hdrivers/pwm/pwm-jz4740.ch]hdrivers/pwm/pwm-jz4740.c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hwatchdogh]hwatchdog}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hdrivers/watchdog/jz4740_wdt.ch]hdrivers/watchdog/jz4740_wdt.c}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(hBecause various functionalities of the TCU that belong to different drivers and frameworks can be controlled from the same registers, all of these drivers access their registers through the same regmap.h]hBecause various functionalities of the TCU that belong to different drivers and frameworks can be controlled from the same registers, all of these drivers access their registers through the same regmap.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjhhubh)}(hFor more information regarding the devicetree bindings of the TCU drivers, have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.h]hFor more information regarding the devicetree bindings of the TCU drivers, have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjhhubeh}(h]implementationah ]h"]implementationah$]h&]uh1hhhhhhhhK5ubeh}(h]/ingenic-jz47xx-socs-timer-counter-unit-hardwareah ]h"]/ingenic jz47xx socs timer/counter unit hardwareah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjj{jxu nametypes}(jj{uh}(jhjxju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.