2~sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget+/translations/zh_CN/arch/m68k/buddha-drivermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/zh_TW/arch/m68k/buddha-drivermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/it_IT/arch/m68k/buddha-drivermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/ja_JP/arch/m68k/buddha-drivermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/ko_KR/arch/m68k/buddha-drivermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget+/translations/sp_SP/arch/m68k/buddha-drivermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h%Amiga Buddha and Catweasel IDE Driverh]h%Amiga Buddha and Catweasel IDE Driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhE/var/lib/git/docbuild/linux/Documentation/arch/m68k/buddha-driver.rsthKubh paragraph)}(hThe Amiga Buddha and Catweasel IDE Driver (part of ide.c) was written by Geert Uytterhoeven based on the following specifications:h]hThe Amiga Buddha and Catweasel IDE Driver (part of ide.c) was written by Geert Uytterhoeven based on the following specifications:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh transition)}(hH------------------------------------------------------------------------h]h}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h_Register map of the Buddha IDE controller and the Buddha-part of the Catweasel Zorro-II versionh]h_Register map of the Buddha IDE controller and the Buddha-part of the Catweasel Zorro-II version}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXjThe Autoconfiguration has been implemented just as Commodore described in their manuals, no tricks have been used (for example leaving some address lines out of the equations...). If you want to configure the board yourself (for example let a Linux kernel configure the card), look at the Commodore Docs. Reading the nibbles should give this information::h]hXiThe Autoconfiguration has been implemented just as Commodore described in their manuals, no tricks have been used (for example leaving some address lines out of the equations...). If you want to configure the board yourself (for example let a Linux kernel configure the card), look at the Commodore Docs. Reading the nibbles should give this information:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh literal_block)}(hhVendor number: 4626 ($1212) product number: 0 (42 for Catweasel Z-II) Serial number: 0 Rom-vector: $1000h]hhVendor number: 4626 ($1212) product number: 0 (42 for Catweasel Z-II) Serial number: 0 Rom-vector: $1000}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhKhhhhubh)}(hThe card should be a Z-II board, size 64K, not for freemem list, Rom-Vektor is valid, no second Autoconfig-board on the same card, no space preference, supports "Shutup_forever".h]hThe card should be a Z-II board, size 64K, not for freemem list, Rom-Vektor is valid, no second Autoconfig-board on the same card, no space preference, supports “Shutup_forever”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXSetting the base address should be done in two steps, just as the Amiga Kickstart does: The lower nibble of the 8-Bit address is written to $4a, then the whole Byte is written to $48, while it doesn't matter how often you're writing to $4a as long as $48 is not touched. After $48 has been written, the whole card disappears from $e8 and is mapped to the new address just written. Make sure $4a is written before $48, otherwise your chance is only 1:16 to find the board :-).h]hXSetting the base address should be done in two steps, just as the Amiga Kickstart does: The lower nibble of the 8-Bit address is written to $4a, then the whole Byte is written to $48, while it doesn’t matter how often you’re writing to $4a as long as $48 is not touched. After $48 has been written, the whole card disappears from $e8 and is mapped to the new address just written. Make sure $4a is written before $48, otherwise your chance is only 1:16 to find the board :-).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h7The local memory-map is even active when mapped to $e8:h]h7The local memory-map is even active when mapped to $e8:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j5hj2ubj6)}(hhh]h}(h]h ]h"]h$]h&]colwidthK+uh1j5hj2ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h$0-$7eh]h$0-$7e}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjWubah}(h]h ]h"]h$]h&]uh1jUhjRubjV)}(hhh]h)}(h Autokonfig-space, see Z-II docs.h]h Autokonfig-space, see Z-II docs.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjnubah}(h]h ]h"]h$]h&]uh1jUhjRubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h$80-$7fdh]h$80-$7fd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hreservedh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h$7feh]h$7fe}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hBSpeed-select Register: Read & Write (description see further down)h]hBSpeed-select Register: Read & Write (description see further down)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $800-$8ffh]h $800-$8ff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(h%IDE-Select 0 (Port 0, Register set 0)h]h%IDE-Select 0 (Port 0, Register set 0)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $900-$9ffh]h $900-$9ff}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hj3ubah}(h]h ]h"]h$]h&]uh1jUhj0ubjV)}(hhh]h)}(h%IDE-Select 1 (Port 0, Register set 1)h]h%IDE-Select 1 (Port 0, Register set 1)}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjJubah}(h]h ]h"]h$]h&]uh1jUhj0ubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $a00-$affh]h $a00-$aff}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjjubah}(h]h ]h"]h$]h&]uh1jUhjgubjV)}(hhh]h)}(h%IDE-Select 2 (Port 1, Register set 0)h]h%IDE-Select 2 (Port 1, Register set 0)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1jUhjgubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $b00-$bffh]h $b00-$bff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(h%IDE-Select 3 (Port 1, Register set 1)h]h%IDE-Select 3 (Port 1, Register set 1)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $c00-$cffh]h $c00-$cff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(h6IDE-Select 4 (Port 2, Register set 0, Catweasel only!)h]h6IDE-Select 4 (Port 2, Register set 0, Catweasel only!)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $d00-$dffh]h $d00-$dff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjubah}(h]h ]h"]h$]h&]uh1jUhj ubjV)}(hhh]h)}(h6IDE-Select 5 (Port 3, Register set 1, Catweasel only!)h]h6IDE-Select 5 (Port 3, Register set 1, Catweasel only!)}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj&ubah}(h]h ]h"]h$]h&]uh1jUhj ubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $e00-$effh]h $e00-$eff}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjFubah}(h]h ]h"]h$]h&]uh1jUhjCubjV)}(hhh]h)}(hxlocal expansion port, on Catweasel Z-II the Catweasel registers are also mapped here. Never touch, use multidisk.device!h]hxlocal expansion port, on Catweasel Z-II the Catweasel registers are also mapped here. Never touch, use multidisk.device!}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj]ubah}(h]h ]h"]h$]h&]uh1jUhjCubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h$f00h]h$f00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhj}ubah}(h]h ]h"]h$]h&]uh1jUhjzubjV)}(hhh]h)}(hLread only, Byte-access: Bit 7 shows the level of the IRQ-line of IDE port 0.h]hLread only, Byte-access: Bit 7 shows the level of the IRQ-line of IDE port 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjubah}(h]h ]h"]h$]h&]uh1jUhjzubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $f01-$f3fh]h $f01-$f3f}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hmirror of $f00h]hmirror of $f00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h$f40h]h$f40}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hLread only, Byte-access: Bit 7 shows the level of the IRQ-line of IDE port 1.h]hLread only, Byte-access: Bit 7 shows the level of the IRQ-line of IDE port 1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $f41-$f7fh]h $f41-$f7f}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhj"ubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hmirror of $f40h]hmirror of $f40}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhj9ubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h$f80h]h$f80}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjYubah}(h]h ]h"]h$]h&]uh1jUhjVubjV)}(hhh]h)}(h^read only, Byte-access: Bit 7 shows the level of the IRQ-line of IDE port 2. (Catweasel only!)h]h^read only, Byte-access: Bit 7 shows the level of the IRQ-line of IDE port 2. (Catweasel only!)}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjpubah}(h]h ]h"]h$]h&]uh1jUhjVubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $f81-$fbfh]h $f81-$fbf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hmirror of $f80h]hmirror of $f80}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h$fc0h]h$fc0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hXwrite-only: Writing any value to this register enables IRQs to be passed from the IDE ports to the Zorro bus. This mechanism has been implemented to be compatible with harddisks that are either defective or have a buggy firmware and pull the IRQ line up while starting up. If interrupts would always be passed to the bus, the computer might not start up. Once enabled, this flag can not be disabled again. The level of the flag can not be determined by software (what for? Write to me if it's necessary!).h]hXwrite-only: Writing any value to this register enables IRQs to be passed from the IDE ports to the Zorro bus. This mechanism has been implemented to be compatible with harddisks that are either defective or have a buggy firmware and pull the IRQ line up while starting up. If interrupts would always be passed to the bus, the computer might not start up. Once enabled, this flag can not be disabled again. The level of the flag can not be determined by software (what for? Write to me if it’s necessary!).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $fc1-$fffh]h $fc1-$fff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjubah}(h]h ]h"]h$]h&]uh1jUhjubjV)}(hhh]h)}(hmirror of $fc0h]hmirror of $fc0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjubah}(h]h ]h"]h$]h&]uh1jUhjubeh}(h]h ]h"]h$]h&]uh1jPhjMubjQ)}(hhh](jV)}(hhh]h)}(h $1000-$ffffh]h $1000-$ffff}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahj5ubah}(h]h ]h"]h$]h&]uh1jUhj2ubjV)}(hhh]h)}(hBuddha-Rom with offset $1000 in the rom chip. The addresses $0 to $fff of the rom chip cannot be read. Rom is Byte-wide and mapped to even addresses.h]hBuddha-Rom with offset $1000 in the rom chip. The addresses $0 to $fff of the rom chip cannot be read. Rom is Byte-wide and mapped to even addresses.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjLubah}(h]h ]h"]h$]h&]uh1jUhj2ubeh}(h]h ]h"]h$]h&]uh1jPhjMubeh}(h]h ]h"]h$]h&]uh1jKhj2ubeh}(h]h ]h"]h$]h&]colsKuh1j0hj-ubah}(h]h ]h"]h$]h&]uh1j+hhhhhhhNubh)}(hXThe IDE ports issue an INT2. You can read the level of the IRQ-lines of the IDE-ports by reading from the three (two for Buddha-only) registers $f00, $f40 and $f80. This way more than one I/O request can be handled and you can easily determine what driver has to serve the INT2. Buddha and Catweasel expansion boards can issue an INT6. A separate memory map is available for the I/O module and the sysop's I/O module.h]hXThe IDE ports issue an INT2. You can read the level of the IRQ-lines of the IDE-ports by reading from the three (two for Buddha-only) registers $f00, $f40 and $f80. This way more than one I/O request can be handled and you can easily determine what driver has to serve the INT2. Buddha and Catweasel expansion boards can issue an INT6. A separate memory map is available for the I/O module and the sysop’s I/O module.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghhhhubh)}(hXThe IDE ports are fed by the address lines A2 to A4, just as the Amiga 1200 and Amiga 4000 IDE ports are. This way existing drivers can be easily ported to Buddha. A move.l polls two words out of the same address of IDE port since every word is mirrored once. movem is not possible, but it's not necessary either, because you can only speedup 68000 systems with this technique. A 68020 system with fastmem is faster with move.l.h]hXThe IDE ports are fed by the address lines A2 to A4, just as the Amiga 1200 and Amiga 4000 IDE ports are. This way existing drivers can be easily ported to Buddha. A move.l polls two words out of the same address of IDE port since every word is mirrored once. movem is not possible, but it’s not necessary either, because you can only speedup 68000 systems with this technique. A 68020 system with fastmem is faster with move.l.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphhhhubh)}(hXIf you're using the mirrored registers of the IDE-ports with A6=1, the Buddha doesn't care about the speed that you have selected in the speed register (see further down). With A6=1 (for example $840 for port 0, register set 0), a 780ns access is being made. These registers should be used for a command access to the harddisk/CD-Rom, since command accesses are Byte-wide and have to be made slower according to the ATA-X3T9 manual.h]hXIf you’re using the mirrored registers of the IDE-ports with A6=1, the Buddha doesn’t care about the speed that you have selected in the speed register (see further down). With A6=1 (for example $840 for port 0, register set 0), a 780ns access is being made. These registers should be used for a command access to the harddisk/CD-Rom, since command accesses are Byte-wide and have to be made slower according to the ATA-X3T9 manual.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhhhhubh)}(hXDNow for the speed-register: The register is byte-wide, and only the upper three bits are used (Bits 7 to 5). Bit 4 must always be set to 1 to be compatible with later Buddha versions (if I'll ever update this one). I presume that I'll never use the lower four bits, but they have to be set to 1 by definition.h]hXHNow for the speed-register: The register is byte-wide, and only the upper three bits are used (Bits 7 to 5). Bit 4 must always be set to 1 to be compatible with later Buddha versions (if I’ll ever update this one). I presume that I’ll never use the lower four bits, but they have to be set to 1 by definition.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hoThe values in this table have to be shifted 5 bits to the left and or'd with $1f (this sets the lower 5 bits).h]hqThe values in this table have to be shifted 5 bits to the left and or’d with $1f (this sets the lower 5 bits).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXAll the timings have in common: Select and IOR/IOW rise at the same time. IOR and IOW have a propagation delay of about 30ns to the clocks on the Zorro bus, that's why the values are no multiple of 71. One clock-cycle is 71ns long (exactly 70,5 at 14,18 Mhz on PAL systems).h]hX!All the timings have in common: Select and IOR/IOW rise at the same time. IOR and IOW have a propagation delay of about 30ns to the clocks on the Zorro bus, that’s why the values are no multiple of 71. One clock-cycle is 71ns long (exactly 70,5 at 14,18 Mhz on PAL systems).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hvalue 0 (Default after reset) 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles) (same timing as the Amiga 1200 does on it's IDE port without accelerator card) h](hterm)}(hvalue 0 (Default after reset)h]hvalue 0 (Default after reset)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubh definition)}(hhh]h)}(h497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles) (same timing as the Amiga 1200 does on it's IDE port without accelerator card)h]h497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles) (same timing as the Amiga 1200 does on it’s IDE port without accelerator card)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hLvalue 1 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles) h](j)}(hvalue 1h]hvalue 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hhh]h)}(hC639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)h]hC639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hMvalue 2 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles) h](j)}(hvalue 2h]hvalue 2}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj9ubj)}(hhh]h)}(hD781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)h]hD781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjKubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hKvalue 3 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle) h](j)}(hvalue 3h]hvalue 3}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhubj)}(hhh]h)}(hB355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)h]hB355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjzubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hLvalue 4 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles) h](j)}(hvalue 4h]hvalue 4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hC355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)h]hC355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hLvalue 5 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles) h](j)}(hvalue 5h]hvalue 5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hC355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)h]hC355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hNvalue 6 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles) h](j)}(hvalue 6h]hvalue 6}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hE1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)h]hE1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hLvalue 7 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle) h](j)}(hvalue 7h]hvalue 7}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj$ubj)}(hhh]h)}(hC355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)h]hC355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1jhhhhhhhNubh)}(hWhen accessing IDE registers with A6=1 (for example $84x), the timing will always be mode 0 8-bit compatible, no matter what you have selected in the speed register:h]hWhen accessing IDE registers with A6=1 (for example $84x), the timing will always be mode 0 8-bit compatible, no matter what you have selected in the speed register:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h;781ns select, IOR/IOW after 4 clock cycles (=314ns) active.h]h;781ns select, IOR/IOW after 4 clock cycles (=314ns) active.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXtAll the timings with a very short select-signal (the 355ns fast accesses) depend on the accelerator card used in the system: Sometimes two more clock cycles are inserted by the bus interface, making the whole access 497ns long. This doesn't affect the reliability of the controller nor the performance of the card, since this doesn't happen very often.h]hXxAll the timings with a very short select-signal (the 355ns fast accesses) depend on the accelerator card used in the system: Sometimes two more clock cycles are inserted by the bus interface, making the whole access 497ns long. This doesn’t affect the reliability of the controller nor the performance of the card, since this doesn’t happen very often.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX4All the timings are calculated and only confirmed by measurements that allowed me to count the clock cycles. If the system is clocked by an oscillator other than 28,37516 Mhz (for example the NTSC-frequency 28,63636 Mhz), each clock cycle is shortened to a bit less than 70ns (not worth mentioning). You could think of a small performance boost by overclocking the system, but you would either need a multisync monitor, or a graphics card, and your internal diskdrive would go crazy, that's why you shouldn't tune your Amiga this way.h]hX8All the timings are calculated and only confirmed by measurements that allowed me to count the clock cycles. If the system is clocked by an oscillator other than 28,37516 Mhz (for example the NTSC-frequency 28,63636 Mhz), each clock cycle is shortened to a bit less than 70ns (not worth mentioning). You could think of a small performance boost by overclocking the system, but you would either need a multisync monitor, or a graphics card, and your internal diskdrive would go crazy, that’s why you shouldn’t tune your Amiga this way.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXuGiving you the possibility to write software that is compatible with both the Buddha and the Catweasel Z-II, The Buddha acts just like a Catweasel Z-II with no device connected to the third IDE-port. The IRQ-register $f80 always shows a "no IRQ here" on the Buddha, and accesses to the third IDE port are going into data's Nirwana on the Buddha.h]hX{Giving you the possibility to write software that is compatible with both the Buddha and the Catweasel Z-II, The Buddha acts just like a Catweasel Z-II with no device connected to the third IDE-port. The IRQ-register $f80 always shows a “no IRQ here” on the Buddha, and accesses to the third IDE port are going into data’s Nirwana on the Buddha.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h#Jens Schönfeld february 19th, 1997h]h#Jens Schönfeld february 19th, 1997}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hupdated may 27th, 1997h]hupdated may 27th, 1997}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h!eMail: sysop@nostlgic.tng.oche.deh](heMail: }(hjhhhNhNubh reference)}(hsysop@nostlgic.tng.oche.deh]hsysop@nostlgic.tng.oche.de}(hjhhhNhNubah}(h]h ]h"]h$]h&]refuri!mailto:sysop@nostlgic.tng.oche.deuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]%amiga-buddha-and-catweasel-ide-driverah ]h"]%amiga buddha and catweasel ide driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjUfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}jjs nametypes}jsh}jhs footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.