€•!y      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ1/translations/zh_CN/arch/loongarch/irq-chip-model”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ1/translations/zh_TW/arch/loongarch/irq-chip-model”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ1/translations/it_IT/arch/loongarch/irq-chip-model”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ1/translations/ja_JP/arch/loongarch/irq-chip-model”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ1/translations/ko_KR/arch/loongarch/irq-chip-model”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ1/translations/sp_SP/arch/loongarch/irq-chip-model”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒK/var/lib/git/docbuild/linux/Documentation/arch/loongarch/irq-chip-model.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ'IRQ chip model (hierarchy) of LoongArch”h]”hŒ'IRQ chip model (hierarchy) of LoongArch”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ	paragraph”“”)”}”(hXÞ  Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).”h]”hXÞ  Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhÊ)”}”(hXI  CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
and there are two models of hierarchy (legacy model and extended model).”h]”hXI  CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
and there are two models of hierarchy (legacy model and extended model).”…””}”(hhÙhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒLegacy IRQ model”h]”hŒLegacy IRQ model”…””}”(hhêhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhçhžhhŸh³h KubhÊ)”}”(hX  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
to LIOINTC, and then CPUINTC::”h]”hX  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
to LIOINTC, and then CPUINTC:”…””}”(hhøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhhçhžhubhŒliteral_block”“”)”}”(hXÚ  +-----+     +---------+     +-------+
| IPI | --> | CPUINTC | <-- | Timer |
+-----+     +---------+     +-------+
                 ^
                 |
            +---------+     +-------+
            | LIOINTC | <-- | UARTs |
            +---------+     +-------+
                 ^
                 |
           +-----------+
           | HTVECINTC |
           +-----------+
            ^         ^
            |         |
      +---------+ +---------+
      | PCH-PIC | | PCH-MSI |
      +---------+ +---------+
        ^     ^           ^
        |     |           |
+---------+ +---------+ +---------+
| PCH-LPC | | Devices | | Devices |
+---------+ +---------+ +---------+
     ^
     |
+---------+
| Devices |
+---------+”h]”hXÚ  +-----+     +---------+     +-------+
| IPI | --> | CPUINTC | <-- | Timer |
+-----+     +---------+     +-------+
                 ^
                 |
            +---------+     +-------+
            | LIOINTC | <-- | UARTs |
            +---------+     +-------+
                 ^
                 |
           +-----------+
           | HTVECINTC |
           +-----------+
            ^         ^
            |         |
      +---------+ +---------+
      | PCH-PIC | | PCH-MSI |
      +---------+ +---------+
        ^     ^           ^
        |     |           |
+---------+ +---------+ +---------+
| PCH-LPC | | Devices | | Devices |
+---------+ +---------+ +---------+
     ^
     |
+---------+
| Devices |
+---------+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h Khhçhžhubeh}”(h]”Œlegacy-irq-model”ah ]”h"]”Œlegacy irq model”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒExtended IRQ model”h]”hŒExtended IRQ model”…””}”(hj!  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj  hžhhŸh³h K9ubhÊ)”}”(hX  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
to CPUINTC directly::”h]”hX  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
to CPUINTC directly:”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K;hj  hžhubj  )”}”(hX±        +-----+     +---------+     +-------+
      | IPI | --> | CPUINTC | <-- | Timer |
      +-----+     +---------+     +-------+
                   ^       ^
                   |       |
            +---------+ +---------+     +-------+
            | EIOINTC | | LIOINTC | <-- | UARTs |
            +---------+ +---------+     +-------+
             ^       ^
             |       |
      +---------+ +---------+
      | PCH-PIC | | PCH-MSI |
      +---------+ +---------+
        ^     ^           ^
        |     |           |
+---------+ +---------+ +---------+
| PCH-LPC | | Devices | | Devices |
+---------+ +---------+ +---------+
     ^
     |
+---------+
| Devices |
+---------+”h]”hX±        +-----+     +---------+     +-------+
      | IPI | --> | CPUINTC | <-- | Timer |
      +-----+     +---------+     +-------+
                   ^       ^
                   |       |
            +---------+ +---------+     +-------+
            | EIOINTC | | LIOINTC | <-- | UARTs |
            +---------+ +---------+     +-------+
             ^       ^
             |       |
      +---------+ +---------+
      | PCH-PIC | | PCH-MSI |
      +---------+ +---------+
        ^     ^           ^
        |     |           |
+---------+ +---------+ +---------+
| PCH-LPC | | Devices | | Devices |
+---------+ +---------+ +---------+
     ^
     |
+---------+
| Devices |
+---------+”…””}”hj=  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K@hj  hžhubeh}”(h]”Œextended-irq-model”ah ]”h"]”Œextended irq model”ah$]”h&]”uh1h´hh¶hžhhŸh³h K9ubhµ)”}”(hhh]”(hº)”}”(hŒVirtual Extended IRQ model”h]”hŒVirtual Extended IRQ model”…””}”(hjV  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjS  hžhhŸh³h KYubhÊ)”}”(hX*  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
Extended I/O Interrupt Controller), and then go to CPUINTC directly::”h]”hX)  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
Extended I/O Interrupt Controller), and then go to CPUINTC directly:”…””}”(hjd  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K[hjS  hžhubj  )”}”(hX_  +-----+    +-------------------+     +-------+
| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
+-----+    +-------------------+     +-------+
                     ^
                     |
               +-----------+
               | V-EIOINTC |
               +-----------+
                ^         ^
                |         |
         +---------+ +---------+
         | PCH-PIC | | PCH-MSI |
         +---------+ +---------+
           ^      ^          ^
           |      |          |
    +--------+ +---------+ +---------+
    | UARTs  | | Devices | | Devices |
    +--------+ +---------+ +---------+”h]”hX_  +-----+    +-------------------+     +-------+
| IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
+-----+    +-------------------+     +-------+
                     ^
                     |
               +-----------+
               | V-EIOINTC |
               +-----------+
                ^         ^
                |         |
         +---------+ +---------+
         | PCH-PIC | | PCH-MSI |
         +---------+ +---------+
           ^      ^          ^
           |      |          |
    +--------+ +---------+ +---------+
    | UARTs  | | Devices | | Devices |
    +--------+ +---------+ +---------+”…””}”hjr  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K`hjS  hžhubhµ)”}”(hhh]”(hº)”}”(hŒDescription”h]”hŒDescription”…””}”(hjƒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj€  hžhhŸh³h KuubhÊ)”}”(hX  V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
interrupts can be routed to up to 256 virtual cpus.”h]”hX  V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
interrupts can be routed to up to 256 virtual cpus.”…””}”(hj‘  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kvhj€  hžhubhÊ)”}”(hX…  With standard EIOINTC, interrupt routing setting includes two parts: eight
bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
For CPU selection there is four bits for EIOINTC node selection, four bits
for EIOINTC CPU selection. Bitmap method is used for CPU selection and
CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
one EIOINTC node.”h]”hX…  With standard EIOINTC, interrupt routing setting includes two parts: eight
bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
For CPU selection there is four bits for EIOINTC node selection, four bits
for EIOINTC CPU selection. Bitmap method is used for CPU selection and
CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
one EIOINTC node.”…””}”(hjŸ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K{hj€  hžhubhÊ)”}”(hŒ}With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
there are two newly added registers with V-EIOINTC.”h]”hŒ}With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
there are two newly added registers with V-EIOINTC.”…””}”(hj­  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K‚hj€  hžhubeh}”(h]”Œdescription”ah ]”h"]”Œdescription”ah$]”h&]”uh1h´hjS  hžhhŸh³h Kuubhµ)”}”(hhh]”(hº)”}”(hŒEXTIOI_VIRT_FEATURES”h]”hŒEXTIOI_VIRT_FEATURES”…””}”(hjÆ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjÃ  hžhhŸh³h K†ubhÊ)”}”(hŒ™This register is read-only register, which indicates supported features with
V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.”h]”hŒ™This register is read-only register, which indicates supported features with
V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.”…””}”(hjÔ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K‡hjÃ  hžhubhÊ)”}”(hŒÎFeature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
indicates that CPU Interrupt Pin selection can be normal method rather than
bitmap method, so interrupt can be routed to IP0 - IP15.”h]”hŒÎFeature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
indicates that CPU Interrupt Pin selection can be normal method rather than
bitmap method, so interrupt can be routed to IP0 - IP15.”…””}”(hjâ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KŠhjÃ  hžhubhÊ)”}”(hŒÁFeature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
indicates that CPU selection can be normal method rather than bitmap method,
so interrupt can be routed to CPU0 - CPU255.”h]”hŒÁFeature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
indicates that CPU selection can be normal method rather than bitmap method,
so interrupt can be routed to CPU0 - CPU255.”…””}”(hjð  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KŽhjÃ  hžhubeh}”(h]”Œextioi-virt-features”ah ]”h"]”Œextioi_virt_features”ah$]”h&]”uh1h´hjS  hžhhŸh³h K†ubhµ)”}”(hhh]”(hº)”}”(hŒEXTIOI_VIRT_CONFIG”h]”hŒEXTIOI_VIRT_CONFIG”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj  hžhhŸh³h K“ubhÊ)”}”(hŒãThis register is read-write register, for compatibility intterupt routed uses
the default method which is the same with standard EIOINTC. If the bit is set
with 1, it indicated HW to use normal method rather than bitmap method.”h]”hŒãThis register is read-write register, for compatibility intterupt routed uses
the default method which is the same with standard EIOINTC. If the bit is set
with 1, it indicated HW to use normal method rather than bitmap method.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K”hj  hžhubeh}”(h]”Œextioi-virt-config”ah ]”h"]”Œextioi_virt_config”ah$]”h&]”uh1h´hjS  hžhhŸh³h K“ubeh}”(h]”Œvirtual-extended-irq-model”ah ]”h"]”Œvirtual extended irq model”ah$]”h&]”uh1h´hh¶hžhhŸh³h KYubhµ)”}”(hhh]”(hº)”}”(hŒAdvanced Extended IRQ model”h]”hŒAdvanced Extended IRQ model”…””}”(hj8  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj5  hžhhŸh³h K™ubhÊ)”}”(hX@  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts
go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::”h]”hX?  In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts
go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:”…””}”(hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K›hj5  hžhubj  )”}”(hX3  +-----+     +-----------------------+     +-------+
| IPI | --> |        CPUINTC        | <-- | Timer |
+-----+     +-----------------------+     +-------+
             ^          ^          ^
             |          |          |
      +---------+ +----------+ +---------+     +-------+
      | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
      +---------+ +----------+ +---------+     +-------+
           ^            ^
           |            |
      +---------+  +---------+
      | PCH-PIC |  | PCH-MSI |
      +---------+  +---------+
        ^     ^           ^
        |     |           |
+---------+ +---------+ +---------+
| Devices | | PCH-LPC | | Devices |
+---------+ +---------+ +---------+
                 ^
                 |
            +---------+
            | Devices |
            +---------+”h]”hX3  +-----+     +-----------------------+     +-------+
| IPI | --> |        CPUINTC        | <-- | Timer |
+-----+     +-----------------------+     +-------+
             ^          ^          ^
             |          |          |
      +---------+ +----------+ +---------+     +-------+
      | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
      +---------+ +----------+ +---------+     +-------+
           ^            ^
           |            |
      +---------+  +---------+
      | PCH-PIC |  | PCH-MSI |
      +---------+  +---------+
        ^     ^           ^
        |     |           |
+---------+ +---------+ +---------+
| Devices | | PCH-LPC | | Devices |
+---------+ +---------+ +---------+
                 ^
                 |
            +---------+
            | Devices |
            +---------+”…””}”hjT  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K hj5  hžhubeh}”(h]”Œadvanced-extended-irq-model”ah ]”h"]”Œadvanced extended irq model”ah$]”h&]”uh1h´hh¶hžhhŸh³h K™ubhµ)”}”(hhh]”(hº)”}”(hŒACPI-related definitions”h]”hŒACPI-related definitions”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjj  hžhhŸh³h K¹ubhÊ)”}”(hŒ	CPUINTC::”h]”hŒCPUINTC:”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K»hjj  hžhubj  )”}”(hŒTACPI_MADT_TYPE_CORE_PIC;
struct acpi_madt_core_pic;
enum acpi_madt_core_pic_version;”h]”hŒTACPI_MADT_TYPE_CORE_PIC;
struct acpi_madt_core_pic;
enum acpi_madt_core_pic_version;”…””}”hj‰  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K½hjj  hžhubhÊ)”}”(hŒ	LIOINTC::”h]”hŒLIOINTC:”…””}”(hj—  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KÁhjj  hžhubj  )”}”(hŒQACPI_MADT_TYPE_LIO_PIC;
struct acpi_madt_lio_pic;
enum acpi_madt_lio_pic_version;”h]”hŒQACPI_MADT_TYPE_LIO_PIC;
struct acpi_madt_lio_pic;
enum acpi_madt_lio_pic_version;”…””}”hj¥  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KÃhjj  hžhubhÊ)”}”(hŒ	EIOINTC::”h]”hŒEIOINTC:”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KÇhjj  hžhubj  )”}”(hŒQACPI_MADT_TYPE_EIO_PIC;
struct acpi_madt_eio_pic;
enum acpi_madt_eio_pic_version;”h]”hŒQACPI_MADT_TYPE_EIO_PIC;
struct acpi_madt_eio_pic;
enum acpi_madt_eio_pic_version;”…””}”hjÁ  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KÉhjj  hžhubhÊ)”}”(hŒHTVECINTC::”h]”hŒ
HTVECINTC:”…””}”(hjÏ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KÍhjj  hžhubj  )”}”(hŒNACPI_MADT_TYPE_HT_PIC;
struct acpi_madt_ht_pic;
enum acpi_madt_ht_pic_version;”h]”hŒNACPI_MADT_TYPE_HT_PIC;
struct acpi_madt_ht_pic;
enum acpi_madt_ht_pic_version;”…””}”hjÝ  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KÏhjj  hžhubhÊ)”}”(hŒ	PCH-PIC::”h]”hŒPCH-PIC:”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KÓhjj  hžhubj  )”}”(hŒQACPI_MADT_TYPE_BIO_PIC;
struct acpi_madt_bio_pic;
enum acpi_madt_bio_pic_version;”h]”hŒQACPI_MADT_TYPE_BIO_PIC;
struct acpi_madt_bio_pic;
enum acpi_madt_bio_pic_version;”…””}”hjù  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KÕhjj  hžhubhÊ)”}”(hŒ	PCH-MSI::”h]”hŒPCH-MSI:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KÙhjj  hžhubj  )”}”(hŒQACPI_MADT_TYPE_MSI_PIC;
struct acpi_madt_msi_pic;
enum acpi_madt_msi_pic_version;”h]”hŒQACPI_MADT_TYPE_MSI_PIC;
struct acpi_madt_msi_pic;
enum acpi_madt_msi_pic_version;”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KÛhjj  hžhubhÊ)”}”(hŒ	PCH-LPC::”h]”hŒPCH-LPC:”…””}”(hj#  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kßhjj  hžhubj  )”}”(hŒQACPI_MADT_TYPE_LPC_PIC;
struct acpi_madt_lpc_pic;
enum acpi_madt_lpc_pic_version;”h]”hŒQACPI_MADT_TYPE_LPC_PIC;
struct acpi_madt_lpc_pic;
enum acpi_madt_lpc_pic_version;”…””}”hj1  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h Káhjj  hžhubeh}”(h]”Œacpi-related-definitions”ah ]”h"]”Œacpi-related definitions”ah$]”h&]”uh1h´hh¶hžhhŸh³h K¹ubhµ)”}”(hhh]”(hº)”}”(hŒ
References”h]”hŒ
References”…””}”(hjJ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjG  hžhhŸh³h KæubhÊ)”}”(hŒ!Documentation of Loongson-3A5000:”h]”hŒ!Documentation of Loongson-3A5000:”…””}”(hjX  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KèhjG  hžhubhŒblock_quote”“”)”}”(hX  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)

https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
”h]”(hÊ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)”h]”(hŒ	reference”“”)”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf”…””}”(hjr  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jt  uh1jp  hjl  ubhŒ (in Chinese)”…””}”(hjl  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kêhjh  ubhÊ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)”h]”(jq  )”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j‘  uh1jp  hj‹  ubhŒ (in English)”…””}”(hj‹  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kìhjh  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jf  hŸh³h KêhjG  hžhubhÊ)”}”(hŒ)Documentation of Loongson's LS7A chipset:”h]”hŒ+Documentation of Loongsonâ€™s LS7A chipset:”…””}”(hj®  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KîhjG  hžhubjg  )”}”(hX  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)

https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
”h]”(hÊ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)”h]”(jq  )”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf”…””}”(hjÄ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jÆ  uh1jp  hjÀ  ubhŒ (in Chinese)”…””}”(hjÀ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kðhj¼  ubhÊ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)”h]”(jq  )”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jã  uh1jp  hjÝ  ubhŒ (in English)”…””}”(hjÝ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kòhj¼  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jf  hŸh³h KðhjG  hžhubhŒnote”“”)”}”(hX­  - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
  in Section 7.4 of "LoongArch Reference Manual, Vol 1";
- LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
  "Loongson 3A5000 Processor Reference Manual";
- EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
  "Loongson 3A5000 Processor Reference Manual";
- HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
  "Loongson 3A5000 Processor Reference Manual";
- PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
  "Loongson 7A1000 Bridge User Manual";
- PCH-LPC is "LPC Interrupts" described in Section 24.3 of
  "Loongson 7A1000 Bridge User Manual".”h]”hŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ{CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
in Section 7.4 of "LoongArch Reference Manual, Vol 1";”h]”hÊ)”}”(hŒ{CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
in Section 7.4 of "LoongArch Reference Manual, Vol 1";”h]”hŒCPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
in Section 7.4 of â€œLoongArch Reference Manual, Vol 1â€;”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kõhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒlLIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
"Loongson 3A5000 Processor Reference Manual";”h]”hÊ)”}”(hŒlLIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
"Loongson 3A5000 Processor Reference Manual";”h]”hŒtLIOINTC is â€œLegacy I/OInterruptsâ€ described in Section 11.1 of
â€œLoongson 3A5000 Processor Reference Manualâ€;”…””}”(hj)  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K÷hj%  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒoEIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
"Loongson 3A5000 Processor Reference Manual";”h]”hÊ)”}”(hŒoEIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
"Loongson 3A5000 Processor Reference Manual";”h]”hŒwEIOINTC is â€œExtended I/O Interruptsâ€ described in Section 11.2 of
â€œLoongson 3A5000 Processor Reference Manualâ€;”…””}”(hjA  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kùhj=  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒsHTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
"Loongson 3A5000 Processor Reference Manual";”h]”hÊ)”}”(hŒsHTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
"Loongson 3A5000 Processor Reference Manual";”h]”hŒ{HTVECINTC is â€œHyperTransport Interruptsâ€ described in Section 14.3 of
â€œLoongson 3A5000 Processor Reference Manualâ€;”…””}”(hjY  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KûhjU  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒiPCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
"Loongson 7A1000 Bridge User Manual";”h]”hÊ)”}”(hŒiPCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
"Loongson 7A1000 Bridge User Manual";”h]”hŒqPCH-PIC/PCH-MSI is â€œInterrupt Controllerâ€ described in Section 5 of
â€œLoongson 7A1000 Bridge User Manualâ€;”…””}”(hjq  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kýhjm  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒ^PCH-LPC is "LPC Interrupts" described in Section 24.3 of
"Loongson 7A1000 Bridge User Manual".”h]”hÊ)”}”(hŒ^PCH-LPC is "LPC Interrupts" described in Section 24.3 of
"Loongson 7A1000 Bridge User Manual".”h]”hŒfPCH-LPC is â€œLPC Interruptsâ€ described in Section 24.3 of
â€œLoongson 7A1000 Bridge User Manualâ€.”…””}”(hj‰  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kÿhj…  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j  hŸh³h Kõhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j   hjG  hžhhŸNh Nubeh}”(h]”Œ
references”ah ]”h"]”Œ
references”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kæubeh}”(h]”Œ%irq-chip-model-hierarchy-of-loongarch”ah ]”h"]”Œ'irq chip model (hierarchy) of loongarch”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jÞ  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j¸  jµ  j  j  jP  jM  j2  j/  jÀ  j½  j  j   j*  j'  jg  jd  jD  jA  j°  j­  uŒ	nametypes”}”(j¸  ‰j  ‰jP  ‰j2  ‰jÀ  ‰j  ‰j*  ‰jg  ‰jD  ‰j°  ‰uh}”(jµ  h¶j  hçjM  j  j/  jS  j½  j€  j   jÃ  j'  j  jd  j5  jA  jj  j­  jG  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.