€•zŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ1/translations/zh_CN/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/zh_TW/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/it_IT/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ja_JP/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ko_KR/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/pt_BR/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/sp_SP/arch/loongarch/irq-chip-model”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³ŒK/var/lib/git/docbuild/linux/Documentation/arch/loongarch/irq-chip-model.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ'IRQ chip model (hierarchy) of LoongArch”h]”hŒ'IRQ chip model (hierarchy) of LoongArch”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hXÞCurrently, LoongArch based processors (e.g. Loongson-3A5000) can only work together with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).”h]”hXÞCurrently, LoongArch based processors (e.g. Loongson-3A5000) can only work together with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hXICPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, and there are two models of hierarchy (legacy model and extended model).”h]”hXICPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, and there are two models of hierarchy (legacy model and extended model).”…””}”(hhíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒLegacy IRQ model”h]”hŒLegacy IRQ model”…””}”(hhþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhûh²hh³hÇh´KubhÞ)”}”(hXIn this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC::”h]”hXIn this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC:”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhûh²hubhŒ literal_block”“”)”}”(hXÚ+-----+ +---------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +---------+ +-------+ ^ | +---------+ +-------+ | LIOINTC | <-- | UARTs | +---------+ +-------+ ^ | +-----------+ | HTVECINTC | +-----------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | PCH-LPC | | Devices | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+”h]”hXÚ+-----+ +---------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +---------+ +-------+ ^ | +---------+ +-------+ | LIOINTC | <-- | UARTs | +---------+ +-------+ ^ | +-----------+ | HTVECINTC | +-----------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | PCH-LPC | | Devices | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´Khhûh²hubeh}”(h]”Œlegacy-irq-model”ah ]”h"]”Œlegacy irq model”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒExtended IRQ model”h]”hŒExtended IRQ model”…””}”(hj5h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj2h²hh³hÇh´K9ubhÞ)”}”(hXIn this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to to CPUINTC directly::”h]”hXIn this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to to CPUINTC directly:”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K;hj2h²hubj)”}”(hX± +-----+ +---------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ +-------+ | EIOINTC | | LIOINTC | <-- | UARTs | +---------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | PCH-LPC | | Devices | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+”h]”hX± +-----+ +---------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ +-------+ | EIOINTC | | LIOINTC | <-- | UARTs | +---------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | PCH-LPC | | Devices | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+”…””}”hjQsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K@hj2h²hubeh}”(h]”Œextended-irq-model”ah ]”h"]”Œextended irq model”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K9ubhÉ)”}”(hhh]”(hÎ)”}”(hŒVirtual Extended IRQ model”h]”hŒVirtual Extended IRQ model”…””}”(hjjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjgh²hh³hÇh´KYubhÞ)”}”(hX*In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual Extended I/O Interrupt Controller), and then go to CPUINTC directly::”h]”hX)In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual Extended I/O Interrupt Controller), and then go to CPUINTC directly:”…””}”(hjxh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K[hjgh²hubj)”}”(hX_+-----+ +-------------------+ +-------+ | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer | +-----+ +-------------------+ +-------+ ^ | +-----------+ | V-EIOINTC | +-----------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +--------+ +---------+ +---------+ | UARTs | | Devices | | Devices | +--------+ +---------+ +---------+”h]”hX_+-----+ +-------------------+ +-------+ | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer | +-----+ +-------------------+ +-------+ ^ | +-----------+ | V-EIOINTC | +-----------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +--------+ +---------+ +---------+ | UARTs | | Devices | | Devices | +--------+ +---------+ +---------+”…””}”hj†sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K`hjgh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Description”h]”hŒ Description”…””}”(hj—h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj”h²hh³hÇh´KuubhÞ)”}”(hXV-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC interrupts can be routed to up to 256 virtual cpus.”h]”hXV-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC interrupts can be routed to up to 256 virtual cpus.”…””}”(hj¥h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kvhj”h²hubhÞ)”}”(hX…With standard EIOINTC, interrupt routing setting includes two parts: eight bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection. For CPU selection there is four bits for EIOINTC node selection, four bits for EIOINTC CPU selection. Bitmap method is used for CPU selection and CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in one EIOINTC node.”h]”hX…With standard EIOINTC, interrupt routing setting includes two parts: eight bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection. For CPU selection there is four bits for EIOINTC node selection, four bits for EIOINTC CPU selection. Bitmap method is used for CPU selection and CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in one EIOINTC node.”…””}”(hj³h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K{hj”h²hubhÞ)”}”(hŒ}With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin), there are two newly added registers with V-EIOINTC.”h]”hŒ}With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin), there are two newly added registers with V-EIOINTC.”…””}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‚hj”h²hubeh}”(h]”Œ description”ah ]”h"]”Œ description”ah$]”h&]”uh1hÈhjgh²hh³hÇh´KuubhÉ)”}”(hhh]”(hÎ)”}”(hŒEXTIOI_VIRT_FEATURES”h]”hŒEXTIOI_VIRT_FEATURES”…””}”(hjÚh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj×h²hh³hÇh´K†ubhÞ)”}”(hŒ™This register is read-only register, which indicates supported features with V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.”h]”hŒ™This register is read-only register, which indicates supported features with V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.”…””}”(hjèh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‡hj×h²hubhÞ)”}”(hŒÎFeature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it indicates that CPU Interrupt Pin selection can be normal method rather than bitmap method, so interrupt can be routed to IP0 - IP15.”h]”hŒÎFeature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it indicates that CPU Interrupt Pin selection can be normal method rather than bitmap method, so interrupt can be routed to IP0 - IP15.”…””}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KŠhj×h²hubhÞ)”}”(hŒÁFeature EXTIOI_HAS_CPU_ENCODE is extension of V-EIOINTC. If it is 1, it indicates that CPU selection can be normal method rather than bitmap method, so interrupt can be routed to CPU0 - CPU255.”h]”hŒÁFeature EXTIOI_HAS_CPU_ENCODE is extension of V-EIOINTC. If it is 1, it indicates that CPU selection can be normal method rather than bitmap method, so interrupt can be routed to CPU0 - CPU255.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KŽhj×h²hubeh}”(h]”Œextioi-virt-features”ah ]”h"]”Œextioi_virt_features”ah$]”h&]”uh1hÈhjgh²hh³hÇh´K†ubhÉ)”}”(hhh]”(hÎ)”}”(hŒEXTIOI_VIRT_CONFIG”h]”hŒEXTIOI_VIRT_CONFIG”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´K“ubhÞ)”}”(hŒãThis register is read-write register, for compatibility interrupt routed uses the default method which is the same with standard EIOINTC. If the bit is set with 1, it indicated HW to use normal method rather than bitmap method.”h]”hŒãThis register is read-write register, for compatibility interrupt routed uses the default method which is the same with standard EIOINTC. If the bit is set with 1, it indicated HW to use normal method rather than bitmap method.”…””}”(hj+h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K”hjh²hubeh}”(h]”Œextioi-virt-config”ah ]”h"]”Œextioi_virt_config”ah$]”h&]”uh1hÈhjgh²hh³hÇh´K“ubeh}”(h]”Œvirtual-extended-irq-model”ah ]”h"]”Œvirtual extended irq model”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KYubhÉ)”}”(hhh]”(hÎ)”}”(hŒAdvanced Extended IRQ model”h]”hŒAdvanced Extended IRQ model”…””}”(hjLh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjIh²hh³hÇh´K™ubhÞ)”}”(hX@In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::”h]”hX?In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:”…””}”(hjZh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K›hjIh²hubj)”}”(hX3+-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+”h]”hX3+-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+”…””}”hjhsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K hjIh²hubeh}”(h]”Œadvanced-extended-irq-model”ah ]”h"]”Œadvanced extended irq model”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K™ubhÉ)”}”(hhh]”(hÎ)”}”(hŒACPI-related definitions”h]”hŒACPI-related definitions”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj~h²hh³hÇh´K¹ubhÞ)”}”(hŒ CPUINTC::”h]”hŒCPUINTC:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K»hj~h²hubj)”}”(hŒTACPI_MADT_TYPE_CORE_PIC; struct acpi_madt_core_pic; enum acpi_madt_core_pic_version;”h]”hŒTACPI_MADT_TYPE_CORE_PIC; struct acpi_madt_core_pic; enum acpi_madt_core_pic_version;”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K½hj~h²hubhÞ)”}”(hŒ LIOINTC::”h]”hŒLIOINTC:”…””}”(hj«h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÁhj~h²hubj)”}”(hŒQACPI_MADT_TYPE_LIO_PIC; struct acpi_madt_lio_pic; enum acpi_madt_lio_pic_version;”h]”hŒQACPI_MADT_TYPE_LIO_PIC; struct acpi_madt_lio_pic; enum acpi_madt_lio_pic_version;”…””}”hj¹sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´KÃhj~h²hubhÞ)”}”(hŒ EIOINTC::”h]”hŒEIOINTC:”…””}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÇhj~h²hubj)”}”(hŒQACPI_MADT_TYPE_EIO_PIC; struct acpi_madt_eio_pic; enum acpi_madt_eio_pic_version;”h]”hŒQACPI_MADT_TYPE_EIO_PIC; struct acpi_madt_eio_pic; enum acpi_madt_eio_pic_version;”…””}”hjÕsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´KÉhj~h²hubhÞ)”}”(hŒ HTVECINTC::”h]”hŒ HTVECINTC:”…””}”(hjãh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÍhj~h²hubj)”}”(hŒNACPI_MADT_TYPE_HT_PIC; struct acpi_madt_ht_pic; enum acpi_madt_ht_pic_version;”h]”hŒNACPI_MADT_TYPE_HT_PIC; struct acpi_madt_ht_pic; enum acpi_madt_ht_pic_version;”…””}”hjñsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´KÏhj~h²hubhÞ)”}”(hŒ PCH-PIC::”h]”hŒPCH-PIC:”…””}”(hjÿh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÓhj~h²hubj)”}”(hŒQACPI_MADT_TYPE_BIO_PIC; struct acpi_madt_bio_pic; enum acpi_madt_bio_pic_version;”h]”hŒQACPI_MADT_TYPE_BIO_PIC; struct acpi_madt_bio_pic; enum acpi_madt_bio_pic_version;”…””}”hj sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´KÕhj~h²hubhÞ)”}”(hŒ PCH-MSI::”h]”hŒPCH-MSI:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÙhj~h²hubj)”}”(hŒQACPI_MADT_TYPE_MSI_PIC; struct acpi_madt_msi_pic; enum acpi_madt_msi_pic_version;”h]”hŒQACPI_MADT_TYPE_MSI_PIC; struct acpi_madt_msi_pic; enum acpi_madt_msi_pic_version;”…””}”hj)sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´KÛhj~h²hubhÞ)”}”(hŒ PCH-LPC::”h]”hŒPCH-LPC:”…””}”(hj7h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kßhj~h²hubj)”}”(hŒQACPI_MADT_TYPE_LPC_PIC; struct acpi_madt_lpc_pic; enum acpi_madt_lpc_pic_version;”h]”hŒQACPI_MADT_TYPE_LPC_PIC; struct acpi_madt_lpc_pic; enum acpi_madt_lpc_pic_version;”…””}”hjEsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´Káhj~h²hubeh}”(h]”Œacpi-related-definitions”ah ]”h"]”Œacpi-related definitions”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K¹ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ References”h]”hŒ References”…””}”(hj^h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj[h²hh³hÇh´KæubhÞ)”}”(hŒ!Documentation of Loongson-3A5000:”h]”hŒ!Documentation of Loongson-3A5000:”…””}”(hjlh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kèhj[h²hubhŒ block_quote”“”)”}”(hXhttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese) https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English) ”h]”(hÞ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)”h]”(hŒ reference”“”)”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf”…””}”(hj†h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jˆuh1j„hj€ubhŒ (in Chinese)”…””}”(hj€h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kêhj|ubhÞ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)”h]”(j…)”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf”…””}”(hj£h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j¥uh1j„hjŸubhŒ (in English)”…””}”(hjŸh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kìhj|ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jzh³hÇh´Kêhj[h²hubhÞ)”}”(hŒ)Documentation of Loongson's LS7A chipset:”h]”hŒ+Documentation of Loongson’s LS7A chipset:”…””}”(hjÂh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kîhj[h²hubj{)”}”(hXhttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese) https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English) ”h]”(hÞ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)”h]”(j…)”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf”…””}”(hjØh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jÚuh1j„hjÔubhŒ (in Chinese)”…””}”(hjÔh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KðhjÐubhÞ)”}”(hŒ€https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)”h]”(j…)”}”(hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf”h]”hŒshttps://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf”…””}”(hjõh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j÷uh1j„hjñubhŒ (in English)”…””}”(hjñh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KòhjÐubeh}”(h]”h ]”h"]”h$]”h&]”uh1jzh³hÇh´Kðhj[h²hubhŒnote”“”)”}”(hX­- CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described in Section 7.4 of "LoongArch Reference Manual, Vol 1"; - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference Manual"; - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of "Loongson 3A5000 Processor Reference Manual"; - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference Manual"; - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of "Loongson 7A1000 Bridge User Manual"; - PCH-LPC is "LPC Interrupts" described in Section 24.3 of "Loongson 7A1000 Bridge User Manual".”h]”hŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ{CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described in Section 7.4 of "LoongArch Reference Manual, Vol 1";”h]”hÞ)”}”(hŒ{CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described in Section 7.4 of "LoongArch Reference Manual, Vol 1";”h]”hŒCPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described in Section 7.4 of “LoongArch Reference Manual, Vol 1â€;”…””}”(hj%h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kõhj!ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj )”}”(hŒlLIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference Manual";”h]”hÞ)”}”(hŒlLIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference Manual";”h]”hŒtLIOINTC is “Legacy I/OInterrupts†described in Section 11.1 of “Loongson 3A5000 Processor Reference Manualâ€;”…””}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K÷hj9ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj )”}”(hŒoEIOINTC is "Extended I/O Interrupts" described in Section 11.2 of "Loongson 3A5000 Processor Reference Manual";”h]”hÞ)”}”(hŒoEIOINTC is "Extended I/O Interrupts" described in Section 11.2 of "Loongson 3A5000 Processor Reference Manual";”h]”hŒwEIOINTC is “Extended I/O Interrupts†described in Section 11.2 of “Loongson 3A5000 Processor Reference Manualâ€;”…””}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KùhjQubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj )”}”(hŒsHTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference Manual";”h]”hÞ)”}”(hŒsHTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference Manual";”h]”hŒ{HTVECINTC is “HyperTransport Interrupts†described in Section 14.3 of “Loongson 3A5000 Processor Reference Manualâ€;”…””}”(hjmh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kûhjiubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj )”}”(hŒiPCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of "Loongson 7A1000 Bridge User Manual";”h]”hÞ)”}”(hŒiPCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of "Loongson 7A1000 Bridge User Manual";”h]”hŒqPCH-PIC/PCH-MSI is “Interrupt Controller†described in Section 5 of “Loongson 7A1000 Bridge User Manualâ€;”…””}”(hj…h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kýhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj )”}”(hŒ^PCH-LPC is "LPC Interrupts" described in Section 24.3 of "Loongson 7A1000 Bridge User Manual".”h]”hÞ)”}”(hŒ^PCH-LPC is "LPC Interrupts" described in Section 24.3 of "Loongson 7A1000 Bridge User Manual".”h]”hŒfPCH-LPC is “LPC Interrupts†described in Section 24.3 of “Loongson 7A1000 Bridge User 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