€•      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ"/translations/zh_CN/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/zh_TW/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/it_IT/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ja_JP/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ko_KR/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/pt_BR/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/sp_SP/arch/arm64/sve”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ3Scalable Vector Extension support for AArch64 Linux”h]”hŒ3Scalable Vector Extension support for AArch64 Linux”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³Œ</var/lib/git/docbuild/linux/Documentation/arch/arm64/sve.rst”h´KubhŒ	paragraph”“”)”}”(hŒ)Author: Dave Martin <Dave.Martin@arm.com>”h]”(hŒAuthor: Dave Martin <”…””}”(hhÍh²hh³Nh´NubhŒ	reference”“”)”}”(hŒDave.Martin@arm.com”h]”hŒDave.Martin@arm.com”…””}”(hh×h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:Dave.Martin@arm.com”uh1hÕhhÍubhŒ>”…””}”(hhÍh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhÌ)”}”(hŒDate:   4 August 2017”h]”hŒDate:   4 August 2017”…””}”(hhñh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhÌ)”}”(hŒìThis document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Vector Extension (SVE), including
interactions with Streaming SVE mode added by the Scalable Matrix Extension
(SME).”h]”hŒìThis document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Vector Extension (SVE), including
interactions with Streaming SVE mode added by the Scalable Matrix Extension
(SME).”…””}”(hhÿh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K	hh·h²hubhÌ)”}”(hŒdThis is an outline of the most important features and issues only and not
intended to be exhaustive.”h]”hŒdThis is an outline of the most important features and issues only and not
intended to be exhaustive.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhÌ)”}”(hŒÊThis document does not aim to describe the SVE architecture or programmer's
model.  To aid understanding, a minimal description of relevant programmer's
model features for SVE is included in Appendix A.”h]”hŒÎThis document does not aim to describe the SVE architecture or programmerâ€™s
model.  To aid understanding, a minimal description of relevant programmerâ€™s
model features for SVE is included in Appendix A.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒ1.  General”h]”hŒ1.  General”…””}”(hj,  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj)  h²hh³hÊh´KubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒaSVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
tracked per-thread.
”h]”hÌ)”}”(hŒ`SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
tracked per-thread.”h]”hŒ`SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
tracked per-thread.”…””}”(hjE  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhjA  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hŒÊIn streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present
in the system, when it is not supported and these interfaces are used to
access streaming mode FFR is read and written as zero.
”h]”hÌ)”}”(hŒÉIn streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present
in the system, when it is not supported and these interfaces are used to
access streaming mode FFR is read and written as zero.”h]”hŒÉIn streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present
in the system, when it is not supported and these interfaces are used to
access streaming mode FFR is read and written as zero.”…””}”(hj]  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhjY  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hX!  The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
AT_HWCAP entry.  Presence of this flag implies the presence of the SVE
instructions and registers, and the Linux-specific system interfaces
described in this document.  SVE is reported in /proc/cpuinfo as "sve".
”h]”hÌ)”}”(hX   The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
AT_HWCAP entry.  Presence of this flag implies the presence of the SVE
instructions and registers, and the Linux-specific system interfaces
described in this document.  SVE is reported in /proc/cpuinfo as "sve".”h]”hX$  The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
AT_HWCAP entry.  Presence of this flag implies the presence of the SVE
instructions and registers, and the Linux-specific system interfaces
described in this document.  SVE is reported in /proc/cpuinfo as â€œsveâ€.”…””}”(hju  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K hjq  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hXš  Support for the execution of SVE instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
instruction, and checking that the value of the SVE field is nonzero. [3]

It does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP_SVE instead.
”h]”(hÌ)”}”(hŒÕSupport for the execution of SVE instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
instruction, and checking that the value of the SVE field is nonzero. [3]”h]”hŒÕSupport for the execution of SVE instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
instruction, and checking that the value of the SVE field is nonzero. [3]”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K%hj‰  ubhÌ)”}”(hŒÂIt does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP_SVE instead.”h]”hŒÂIt does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP_SVE instead.”…””}”(hj›  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K)hj‰  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hXa  On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
be reported in the AT_HWCAP2 aux vector entry.  In addition to this,
optional extensions to SVE2 may be reported by the presence of:

      HWCAP2_SVE2
      HWCAP2_SVEAES
      HWCAP2_SVEPMULL
      HWCAP2_SVEBITPERM
      HWCAP2_SVESHA3
      HWCAP2_SVESM4
      HWCAP2_SVE2P1

This list may be extended over time as the SVE architecture evolves.

These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
cpu-feature-registers.txt for details.
”h]”(hÌ)”}”(hŒÉOn hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
be reported in the AT_HWCAP2 aux vector entry.  In addition to this,
optional extensions to SVE2 may be reported by the presence of:”h]”hŒÉOn hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
be reported in the AT_HWCAP2 aux vector entry.  In addition to this,
optional extensions to SVE2 may be reported by the presence of:”…””}”(hj³  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K-hj¯  ubhŒblock_quote”“”)”}”(hŒgHWCAP2_SVE2
HWCAP2_SVEAES
HWCAP2_SVEPMULL
HWCAP2_SVEBITPERM
HWCAP2_SVESHA3
HWCAP2_SVESM4
HWCAP2_SVE2P1
”h]”hÌ)”}”(hŒfHWCAP2_SVE2
HWCAP2_SVEAES
HWCAP2_SVEPMULL
HWCAP2_SVEBITPERM
HWCAP2_SVESHA3
HWCAP2_SVESM4
HWCAP2_SVE2P1”h]”hŒfHWCAP2_SVE2
HWCAP2_SVEAES
HWCAP2_SVEPMULL
HWCAP2_SVEBITPERM
HWCAP2_SVESHA3
HWCAP2_SVESM4
HWCAP2_SVE2P1”…””}”(hjÇ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K1hjÃ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´K1hj¯  ubhÌ)”}”(hŒDThis list may be extended over time as the SVE architecture evolves.”h]”hŒDThis list may be extended over time as the SVE architecture evolves.”…””}”(hjÛ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K9hj¯  ubhÌ)”}”(hŒ½These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
cpu-feature-registers.txt for details.”h]”hŒ½These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
cpu-feature-registers.txt for details.”…””}”(hjé  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K;hj¯  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hX+  On hardware that supports the SME extensions, HWCAP2_SME will also be
reported in the AT_HWCAP2 aux vector entry.  Among other things SME adds
streaming mode which provides a subset of the SVE feature set using a
separate SME vector length and the same Z/V registers.  See sme.rst
for more details.
”h]”hÌ)”}”(hX*  On hardware that supports the SME extensions, HWCAP2_SME will also be
reported in the AT_HWCAP2 aux vector entry.  Among other things SME adds
streaming mode which provides a subset of the SVE feature set using a
separate SME vector length and the same Z/V registers.  See sme.rst
for more details.”h]”hX*  On hardware that supports the SME extensions, HWCAP2_SME will also be
reported in the AT_HWCAP2 aux vector entry.  Among other things SME adds
streaming mode which provides a subset of the SVE feature set using a
separate SME vector length and the same Z/V registers.  See sme.rst
for more details.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K?hjý  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hX¾  Debuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE regset.  The recommended way of detecting support for this regset
is to connect to a target process first and then attempt a
ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).  Note that when SME is
present and streaming SVE mode is in use the FPSIMD subset of registers
will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode
in the target.
”h]”hÌ)”}”(hX½  Debuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE regset.  The recommended way of detecting support for this regset
is to connect to a target process first and then attempt a
ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).  Note that when SME is
present and streaming SVE mode is in use the FPSIMD subset of registers
will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode
in the target.”h]”hX½  Debuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE regset.  The recommended way of detecting support for this regset
is to connect to a target process first and then attempt a
ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).  Note that when SME is
present and streaming SVE mode is in use the FPSIMD subset of registers
will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode
in the target.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KEhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubj@  )”}”(hXÏ  Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
between userspace and the kernel, the register value is encoded in memory in
an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
byte offset i from the start of the memory representation.  This affects for
example the signal frame (struct sve_context) and ptrace interface
(struct user_sve_header) and associated data.

Beware that on big-endian systems this results in a different byte order than
for the FPSIMD V-registers, which are stored as single host-endian 128-bit
values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
byte offset i.  (struct fpsimd_context, struct user_fpsimd_state).

”h]”(hÌ)”}”(hX£  Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
between userspace and the kernel, the register value is encoded in memory in
an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
byte offset i from the start of the memory representation.  This affects for
example the signal frame (struct sve_context) and ptrace interface
(struct user_sve_header) and associated data.”h]”hX£  Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
between userspace and the kernel, the register value is encoded in memory in
an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
byte offset i from the start of the memory representation.  This affects for
example the signal frame (struct sve_context) and ptrace interface
(struct user_sve_header) and associated data.”…””}”(hj1  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KMhj-  ubhÌ)”}”(hX(  Beware that on big-endian systems this results in a different byte order than
for the FPSIMD V-registers, which are stored as single host-endian 128-bit
values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
byte offset i.  (struct fpsimd_context, struct user_fpsimd_state).”h]”hX(  Beware that on big-endian systems this results in a different byte order than
for the FPSIMD V-registers, which are stored as single host-endian 128-bit
values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
byte offset i.  (struct fpsimd_context, struct user_fpsimd_state).”…””}”(hj?  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KThj-  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj<  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1j:  h³hÊh´Khj)  h²hubeh}”(h]”Œgeneral”ah ]”h"]”Œ
1. general”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒ2.  Vector length terminology”h]”hŒ2.  Vector length terminology”…””}”(hjf  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjc  h²hh³hÊh´K[ubhÌ)”}”(hŒMThe size of an SVE vector (Z) register is referred to as the "vector length".”h]”hŒQThe size of an SVE vector (Z) register is referred to as the â€œvector lengthâ€.”…””}”(hjt  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K]hjc  h²hubhÌ)”}”(hŒnTo avoid confusion about the units used to express vector length, the kernel
adopts the following conventions:”h]”hŒnTo avoid confusion about the units used to express vector length, the kernel
adopts the following conventions:”…””}”(hj‚  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K_hjc  h²hubj;  )”}”(hhh]”(j@  )”}”(hŒ3Vector length (VL) = size of a Z-register in bytes
”h]”hÌ)”}”(hŒ2Vector length (VL) = size of a Z-register in bytes”h]”hŒ2Vector length (VL) = size of a Z-register in bytes”…””}”(hj—  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kbhj“  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubj@  )”}”(hŒBVector quadwords (VQ) = size of a Z-register in units of 128 bits
”h]”hÌ)”}”(hŒAVector quadwords (VQ) = size of a Z-register in units of 128 bits”h]”hŒAVector quadwords (VQ) = size of a Z-register in units of 128 bits”…””}”(hj¯  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kdhj«  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´Kbhjc  h²hubhÌ)”}”(hŒ(So, VL = 16 * VQ.)”h]”hŒ(So, VL = 16 * VQ.)”…””}”(hjÉ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kfhjc  h²hubhÌ)”}”(hX  The VQ convention is used where the underlying granularity is important, such
as in data structure definitions.  In most other situations, the VL convention
is used.  This is consistent with the meaning of the "VL" pseudo-register in
the SVE instruction set architecture.”h]”hX  The VQ convention is used where the underlying granularity is important, such
as in data structure definitions.  In most other situations, the VL convention
is used.  This is consistent with the meaning of the â€œVLâ€ pseudo-register in
the SVE instruction set architecture.”…””}”(hj×  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khhjc  h²hubeh}”(h]”Œvector-length-terminology”ah ]”h"]”Œ2. vector length terminology”ah$]”h&]”uh1hµhh·h²hh³hÊh´K[ubh¶)”}”(hhh]”(h»)”}”(hŒ3.  System call behaviour”h]”hŒ3.  System call behaviour”…””}”(hjð  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjí  h²hh³hÊh´Koubj;  )”}”(hhh]”(j@  )”}”(hŒ¿On syscall, V0..V31 are preserved (as without SVE).  Thus, bits [127:0] of
Z0..Z31 are preserved.  All other bits of Z0..Z31, and all of P0..P15 and FFR
become zero on return from a syscall.
”h]”hÌ)”}”(hŒ¾On syscall, V0..V31 are preserved (as without SVE).  Thus, bits [127:0] of
Z0..Z31 are preserved.  All other bits of Z0..Z31, and all of P0..P15 and FFR
become zero on return from a syscall.”h]”hŒ¾On syscall, V0..V31 are preserved (as without SVE).  Thus, bits [127:0] of
Z0..Z31 are preserved.  All other bits of Z0..Z31, and all of P0..P15 and FFR
become zero on return from a syscall.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kqhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjþ  h²hh³hÊh´Nubj@  )”}”(hŒYThe SVE registers are not used to pass arguments to or receive results from
any syscall.
”h]”hÌ)”}”(hŒXThe SVE registers are not used to pass arguments to or receive results from
any syscall.”h]”hŒXThe SVE registers are not used to pass arguments to or receive results from
any syscall.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kuhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjþ  h²hh³hÊh´Nubj@  )”}”(hX¿  All other SVE state of a thread, including the currently configured vector
length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.

In particular, on return from a fork() or clone(), the parent and new child
process or thread share identical SVE configuration, matching that of the
parent before the call.

”h]”(hÌ)”}”(hX  All other SVE state of a thread, including the currently configured vector
length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.”h]”hX  All other SVE state of a thread, including the currently configured vector
length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.”…””}”(hj5  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kxhj1  ubhÌ)”}”(hŒ­In particular, on return from a fork() or clone(), the parent and new child
process or thread share identical SVE configuration, matching that of the
parent before the call.”h]”hŒ­In particular, on return from a fork() or clone(), the parent and new child
process or thread share identical SVE configuration, matching that of the
parent before the call.”…””}”(hjC  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K}hj1  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjþ  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´Kqhjí  h²hubeh}”(h]”Œsystem-call-behaviour”ah ]”h"]”Œ3. system call behaviour”ah$]”h&]”uh1hµhh·h²hh³hÊh´Koubh¶)”}”(hhh]”(h»)”}”(hŒ4.  Signal handling”h]”hŒ4.  Signal handling”…””}”(hjh  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhje  h²hh³hÊh´Kƒubj;  )”}”(hhh]”(j@  )”}”(hŒXA new signal frame record sve_context encodes the SVE registers on signal
delivery. [1]
”h]”hÌ)”}”(hŒWA new signal frame record sve_context encodes the SVE registers on signal
delivery. [1]”h]”hŒWA new signal frame record sve_context encodes the SVE registers on signal
delivery. [1]”…””}”(hj}  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K…hjy  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hŒÐThis record is supplementary to fpsimd_context.  The FPSR and FPCR registers
are only present in fpsimd_context.  For convenience, the content of V0..V31
is duplicated between sve_context and fpsimd_context.
”h]”hÌ)”}”(hŒÏThis record is supplementary to fpsimd_context.  The FPSR and FPCR registers
are only present in fpsimd_context.  For convenience, the content of V0..V31
is duplicated between sve_context and fpsimd_context.”h]”hŒÏThis record is supplementary to fpsimd_context.  The FPSR and FPCR registers
are only present in fpsimd_context.  For convenience, the content of V0..V31
is duplicated between sve_context and fpsimd_context.”…””}”(hj•  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kˆhj‘  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hŒëThe record contains a flag field which includes a flag SVE_SIG_FLAG_SM which
if set indicates that the thread is in streaming mode and the vector length
and register data (if present) describe the streaming SVE data and vector
length.
”h]”hÌ)”}”(hŒêThe record contains a flag field which includes a flag SVE_SIG_FLAG_SM which
if set indicates that the thread is in streaming mode and the vector length
and register data (if present) describe the streaming SVE data and vector
length.”h]”hŒêThe record contains a flag field which includes a flag SVE_SIG_FLAG_SM which
if set indicates that the thread is in streaming mode and the vector length
and register data (if present) describe the streaming SVE data and vector
length.”…””}”(hj­  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KŒhj©  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hŒ~The signal frame record for SVE always contains basic metadata, in particular
the thread's vector length (in sve_context.vl).
”h]”hÌ)”}”(hŒ}The signal frame record for SVE always contains basic metadata, in particular
the thread's vector length (in sve_context.vl).”h]”hŒThe signal frame record for SVE always contains basic metadata, in particular
the threadâ€™s vector length (in sve_context.vl).”…””}”(hjÅ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K‘hjÁ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hŒòThe SVE registers may or may not be included in the record, depending on
whether the registers are live for the thread.  The registers are present if
and only if:
sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).
”h]”hÌ)”}”(hŒñThe SVE registers may or may not be included in the record, depending on
whether the registers are live for the thread.  The registers are present if
and only if:
sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).”h]”hŒñThe SVE registers may or may not be included in the record, depending on
whether the registers are live for the thread.  The registers are present if
and only if:
sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).”…””}”(hjÝ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K”hjÙ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hŒ¥If the registers are present, the remainder of the record has a vl-dependent
size and layout.  Macros SVE_SIG_* are defined [1] to facilitate access to
the members.
”h]”hÌ)”}”(hŒ¤If the registers are present, the remainder of the record has a vl-dependent
size and layout.  Macros SVE_SIG_* are defined [1] to facilitate access to
the members.”h]”hŒ¤If the registers are present, the remainder of the record has a vl-dependent
size and layout.  Macros SVE_SIG_* are defined [1] to facilitate access to
the members.”…””}”(hjõ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K™hjñ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hŒÇEach scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
start of the register's representation in memory.
”h]”hÌ)”}”(hŒÆEach scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
start of the register's representation in memory.”h]”hŒÈEach scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
start of the registerâ€™s representation in memory.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubj@  )”}”(hX"  If the SVE context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space.  sve_context is then written in the
extra space.  Refer to [1] for further details about this mechanism.

”h]”hÌ)”}”(hX   If the SVE context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space.  sve_context is then written in the
extra space.  Refer to [1] for further details about this mechanism.”h]”hX   If the SVE context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space.  sve_context is then written in the
extra space.  Refer to [1] for further details about this mechanism.”…””}”(hj%  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¡hj!  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjv  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´K…hje  h²hubeh}”(h]”Œsignal-handling”ah ]”h"]”Œ4. signal handling”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kƒubh¶)”}”(hhh]”(h»)”}”(hŒ5.  Signal return”h]”hŒ5.  Signal return”…””}”(hjJ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjG  h²hh³hÊh´K¨ubhÌ)”}”(hŒ%When returning from a signal handler:”h]”hŒ%When returning from a signal handler:”…””}”(hjX  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KªhjG  h²hubj;  )”}”(hhh]”(j@  )”}”(hŒàIf there is no sve_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then the SVE registers/bits become non-live and take unspecified values.
”h]”hÌ)”}”(hŒßIf there is no sve_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then the SVE registers/bits become non-live and take unspecified values.”h]”hŒßIf there is no sve_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then the SVE registers/bits become non-live and take unspecified values.”…””}”(hjm  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¬hji  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjf  h²hh³hÊh´Nubj@  )”}”(hXx  If sve_context is present in the signal frame and contains full register
data, the SVE registers become live and are populated with the specified
data.  However, for backward compatibility reasons, bits [127:0] of Z0..Z31
are always restored from the corresponding members of fpsimd_context.vregs[]
and not from sve_context.  The remaining bits are restored from sve_context.
”h]”hÌ)”}”(hXw  If sve_context is present in the signal frame and contains full register
data, the SVE registers become live and are populated with the specified
data.  However, for backward compatibility reasons, bits [127:0] of Z0..Z31
are always restored from the corresponding members of fpsimd_context.vregs[]
and not from sve_context.  The remaining bits are restored from sve_context.”h]”hXw  If sve_context is present in the signal frame and contains full register
data, the SVE registers become live and are populated with the specified
data.  However, for backward compatibility reasons, bits [127:0] of Z0..Z31
are always restored from the corresponding members of fpsimd_context.vregs[]
and not from sve_context.  The remaining bits are restored from sve_context.”…””}”(hj…  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K°hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjf  h²hh³hÊh´Nubj@  )”}”(hŒzInclusion of fpsimd_context in the signal frame remains mandatory,
irrespective of whether sve_context is present or not.
”h]”hÌ)”}”(hŒyInclusion of fpsimd_context in the signal frame remains mandatory,
irrespective of whether sve_context is present or not.”h]”hŒyInclusion of fpsimd_context in the signal frame remains mandatory,
irrespective of whether sve_context is present or not.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¶hj™  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjf  h²hh³hÊh´Nubj@  )”}”(hŒØThe vector length cannot be changed via signal return.  If sve_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.
”h]”hÌ)”}”(hŒ×The vector length cannot be changed via signal return.  If sve_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.”h]”hŒ×The vector length cannot be changed via signal return.  If sve_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.”…””}”(hjµ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¹hj±  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjf  h²hh³hÊh´Nubj@  )”}”(hŒýIt is permitted to enter or leave streaming mode by setting or clearing
the SVE_SIG_FLAG_SM flag but applications should take care to ensure that
when doing so sve_context.vl and any register data are appropriate for the
vector length in the new mode.

”h]”hÌ)”}”(hŒûIt is permitted to enter or leave streaming mode by setting or clearing
the SVE_SIG_FLAG_SM flag but applications should take care to ensure that
when doing so sve_context.vl and any register data are appropriate for the
vector length in the new mode.”h]”hŒûIt is permitted to enter or leave streaming mode by setting or clearing
the SVE_SIG_FLAG_SM flag but applications should take care to ensure that
when doing so sve_context.vl and any register data are appropriate for the
vector length in the new mode.”…””}”(hjÍ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K½hjÉ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjf  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´K¬hjG  h²hubeh}”(h]”Œsignal-return”ah ]”h"]”Œ5. signal return”ah$]”h&]”uh1hµhh·h²hh³hÊh´K¨ubh¶)”}”(hhh]”(h»)”}”(hŒ6.  prctl extensions”h]”hŒ6.  prctl extensions”…””}”(hjò  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjï  h²hh³hÊh´KÄubhÌ)”}”(hŒSSome new prctl() calls are added to allow programs to manage the SVE vector
length:”h]”hŒSSome new prctl() calls are added to allow programs to manage the SVE vector
length:”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÆhjï  h²hubhÌ)”}”(hŒ'prctl(PR_SVE_SET_VL, unsigned long arg)”h]”hŒ'prctl(PR_SVE_SET_VL, unsigned long arg)”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÉhjï  h²hubjÂ  )”}”(hXD	  Sets the vector length of the calling thread and related flags, where
arg == vl | flags.  Other threads of the calling process are unaffected.

vl is the desired vector length, where sve_vl_valid(vl) must be true.

flags:

    PR_SVE_VL_INHERIT

        Inherit the current vector length across execve().  Otherwise, the
        vector length is reset to the system default at execve().  (See
        Section 9.)

    PR_SVE_SET_VL_ONEXEC

        Defer the requested vector length change until the next execve()
        performed by this thread.

        The effect is equivalent to implicit execution of the following
        call immediately after the next execve() (if any) by the thread:

            prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)

        This allows launching of a new program with a different vector
        length, while avoiding runtime side effects in the caller.


        Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
        immediately.


Return value: a nonnegative on success, or a negative value on error:
    EINVAL: SVE not supported, invalid vector length requested, or
        invalid flags.


On success:

* Either the calling thread's vector length or the deferred vector length
  to be applied at the next execve() by the thread (dependent on whether
  PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
  supported by the system that is less than or equal to vl.  If vl ==
  SVE_VL_MAX, the value set will be the largest value supported by the
  system.

* Any previously outstanding deferred vector length change in the calling
  thread is cancelled.

* The returned value describes the resulting configuration, encoded as for
  PR_SVE_GET_VL.  The vector length reported in this value is the new
  current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
  present in arg; otherwise, the reported vector length is the deferred
  vector length that will be applied at the next execve() by the calling
  thread.

* Changing the vector length causes all of P0..P15, FFR and all bits of
  Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
  unspecified.  Calling PR_SVE_SET_VL with vl equal to the thread's current
  vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
  flag, does not constitute a change to the vector length for this purpose.

”h]”(hÌ)”}”(hŒŽSets the vector length of the calling thread and related flags, where
arg == vl | flags.  Other threads of the calling process are unaffected.”h]”hŒŽSets the vector length of the calling thread and related flags, where
arg == vl | flags.  Other threads of the calling process are unaffected.”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KËhj  ubhÌ)”}”(hŒEvl is the desired vector length, where sve_vl_valid(vl) must be true.”h]”hŒEvl is the desired vector length, where sve_vl_valid(vl) must be true.”…””}”(hj.  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÎhj  ubhÌ)”}”(hŒflags:”h]”hŒflags:”…””}”(hj<  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÐhj  ubjÂ  )”}”(hXÈ  PR_SVE_VL_INHERIT

    Inherit the current vector length across execve().  Otherwise, the
    vector length is reset to the system default at execve().  (See
    Section 9.)

PR_SVE_SET_VL_ONEXEC

    Defer the requested vector length change until the next execve()
    performed by this thread.

    The effect is equivalent to implicit execution of the following
    call immediately after the next execve() (if any) by the thread:

        prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)

    This allows launching of a new program with a different vector
    length, while avoiding runtime side effects in the caller.


    Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
    immediately.

”h]”(hÌ)”}”(hŒPR_SVE_VL_INHERIT”h]”hŒPR_SVE_VL_INHERIT”…””}”(hjN  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÒhjJ  ubjÂ  )”}”(hŒInherit the current vector length across execve().  Otherwise, the
vector length is reset to the system default at execve().  (See
Section 9.)
”h]”hÌ)”}”(hŒŽInherit the current vector length across execve().  Otherwise, the
vector length is reset to the system default at execve().  (See
Section 9.)”h]”hŒŽInherit the current vector length across execve().  Otherwise, the
vector length is reset to the system default at execve().  (See
Section 9.)”…””}”(hj`  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÔhj\  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´KÔhjJ  ubhÌ)”}”(hŒPR_SVE_SET_VL_ONEXEC”h]”hŒPR_SVE_SET_VL_ONEXEC”…””}”(hjt  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KØhjJ  ubjÂ  )”}”(hXß  Defer the requested vector length change until the next execve()
performed by this thread.

The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:

    prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)

This allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.


Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
immediately.

”h]”(hÌ)”}”(hŒZDefer the requested vector length change until the next execve()
performed by this thread.”h]”hŒZDefer the requested vector length change until the next execve()
performed by this thread.”…””}”(hj†  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÚhj‚  ubhÌ)”}”(hŒ€The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:”h]”hŒ€The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:”…””}”(hj”  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÝhj‚  ubjÂ  )”}”(hŒ2prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
”h]”hÌ)”}”(hŒ1prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)”h]”hŒ1prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)”…””}”(hj¦  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kàhj¢  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´Kàhj‚  ubhÌ)”}”(hŒyThis allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.”h]”hŒyThis allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kâhj‚  ubhÌ)”}”(hŒLWithout PR_SVE_SET_VL_ONEXEC, the requested change takes effect
immediately.”h]”hŒLWithout PR_SVE_SET_VL_ONEXEC, the requested change takes effect
immediately.”…””}”(hjÈ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kæhj‚  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´KÚhjJ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´KÒhj  ubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒ™Return value: a nonnegative on success, or a negative value on error:
EINVAL: SVE not supported, invalid vector length requested, or
    invalid flags.

”h]”(hŒterm”“”)”}”(hŒEReturn value: a nonnegative on success, or a negative value on error:”h]”hŒEReturn value: a nonnegative on success, or a negative value on error:”…””}”(hjï  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´Kíhjé  ubhŒ
definition”“”)”}”(hhh]”jã  )”}”(hhh]”jè  )”}”(hŒOEINVAL: SVE not supported, invalid vector length requested, or
invalid flags.

”h]”(jî  )”}”(hŒ>EINVAL: SVE not supported, invalid vector length requested, or”h]”hŒ>EINVAL: SVE not supported, invalid vector length requested, or”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´Kíhj  ubjþ  )”}”(hhh]”hÌ)”}”(hŒinvalid flags.”h]”hŒinvalid flags.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kìhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´Kíhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hjÿ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hjé  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´Kíhjä  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hj  ubhÌ)”}”(hŒOn success:”h]”hŒOn success:”…””}”(hjL  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kïhj  ubj;  )”}”(hhh]”(j@  )”}”(hXe  Either the calling thread's vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl.  If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.
”h]”hÌ)”}”(hXd  Either the calling thread's vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl.  If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.”h]”hXf  Either the calling threadâ€™s vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl.  If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.”…””}”(hja  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kñhj]  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjZ  ubj@  )”}”(hŒ]Any previously outstanding deferred vector length change in the calling
thread is cancelled.
”h]”hÌ)”}”(hŒ\Any previously outstanding deferred vector length change in the calling
thread is cancelled.”h]”hŒ\Any previously outstanding deferred vector length change in the calling
thread is cancelled.”…””}”(hjy  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Køhju  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjZ  ubj@  )”}”(hXh  The returned value describes the resulting configuration, encoded as for
PR_SVE_GET_VL.  The vector length reported in this value is the new
current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.
”h]”hÌ)”}”(hXg  The returned value describes the resulting configuration, encoded as for
PR_SVE_GET_VL.  The vector length reported in this value is the new
current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.”h]”hXg  The returned value describes the resulting configuration, encoded as for
PR_SVE_GET_VL.  The vector length reported in this value is the new
current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.”…””}”(hj‘  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kûhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjZ  ubj@  )”}”(hXb  Changing the vector length causes all of P0..P15, FFR and all bits of
Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified.  Calling PR_SVE_SET_VL with vl equal to the thread's current
vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
flag, does not constitute a change to the vector length for this purpose.

”h]”hÌ)”}”(hX`  Changing the vector length causes all of P0..P15, FFR and all bits of
Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified.  Calling PR_SVE_SET_VL with vl equal to the thread's current
vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
flag, does not constitute a change to the vector length for this purpose.”h]”hXb  Changing the vector length causes all of P0..P15, FFR and all bits of
Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified.  Calling PR_SVE_SET_VL with vl equal to the threadâ€™s current
vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
flag, does not constitute a change to the vector length for this purpose.”…””}”(hj©  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj¥  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjZ  ubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´Kñhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´KËhjï  h²hubhÌ)”}”(hŒprctl(PR_SVE_GET_VL)”h]”hŒprctl(PR_SVE_GET_VL)”…””}”(hjÉ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M	hjï  h²hubjÂ  )”}”(hXD  Gets the vector length of the calling thread.

The following flag may be OR-ed into the result:

    PR_SVE_VL_INHERIT

        Vector length will be inherited across execve().

There is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).

To extract the vector length from the result, bitwise and it with
PR_SVE_VL_LEN_MASK.

Return value: a nonnegative value on success, or a negative value on error:
    EINVAL: SVE not supported.

”h]”(hÌ)”}”(hŒ-Gets the vector length of the calling thread.”h]”hŒ-Gets the vector length of the calling thread.”…””}”(hjÛ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj×  ubhÌ)”}”(hŒ0The following flag may be OR-ed into the result:”h]”hŒ0The following flag may be OR-ed into the result:”…””}”(hjé  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj×  ubjÂ  )”}”(hŒHPR_SVE_VL_INHERIT

    Vector length will be inherited across execve().
”h]”(hÌ)”}”(hŒPR_SVE_VL_INHERIT”h]”hŒPR_SVE_VL_INHERIT”…””}”(hjû  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj÷  ubjÂ  )”}”(hŒ1Vector length will be inherited across execve().
”h]”hÌ)”}”(hŒ0Vector length will be inherited across execve().”h]”hŒ0Vector length will be inherited across execve().”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´Mhj÷  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´Mhj×  ubhÌ)”}”(hŒÍThere is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).”h]”hŒÍThere is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).”…””}”(hj'  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj×  ubhÌ)”}”(hŒUTo extract the vector length from the result, bitwise and it with
PR_SVE_VL_LEN_MASK.”h]”hŒUTo extract the vector length from the result, bitwise and it with
PR_SVE_VL_LEN_MASK.”…””}”(hj5  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj×  ubjã  )”}”(hhh]”jè  )”}”(hŒhReturn value: a nonnegative value on success, or a negative value on error:
EINVAL: SVE not supported.

”h]”(jî  )”}”(hŒKReturn value: a nonnegative value on success, or a negative value on error:”h]”hŒKReturn value: a nonnegative value on success, or a negative value on error:”…””}”(hjJ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´MhjF  ubjþ  )”}”(hhh]”hÌ)”}”(hŒEINVAL: SVE not supported.”h]”hŒEINVAL: SVE not supported.”…””}”(hj[  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MhjX  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hjF  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´MhjC  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hj×  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´Mhjï  h²hubeh}”(h]”Œprctl-extensions”ah ]”h"]”Œ6. prctl extensions”ah$]”h&]”uh1hµhh·h²hh³hÊh´KÄubh¶)”}”(hhh]”(h»)”}”(hŒ7.  ptrace extensions”h]”hŒ7.  ptrace extensions”…””}”(hjŒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj‰  h²hh³hÊh´Mubj;  )”}”(hhh]”j@  )”}”(hXÎ  New regsets NT_ARM_SVE and NT_ARM_SSVE are defined for use with
PTRACE_GETREGSET and PTRACE_SETREGSET. NT_ARM_SSVE describes the
streaming mode SVE registers and NT_ARM_SVE describes the
non-streaming mode SVE registers.

In this description a register set is referred to as being "live" when
the target is in the appropriate streaming or non-streaming mode and is
using data beyond the subset shared with the FPSIMD Vn registers.

Refer to [2] for definitions.
”h]”(hÌ)”}”(hŒÜNew regsets NT_ARM_SVE and NT_ARM_SSVE are defined for use with
PTRACE_GETREGSET and PTRACE_SETREGSET. NT_ARM_SSVE describes the
streaming mode SVE registers and NT_ARM_SVE describes the
non-streaming mode SVE registers.”h]”hŒÜNew regsets NT_ARM_SVE and NT_ARM_SSVE are defined for use with
PTRACE_GETREGSET and PTRACE_SETREGSET. NT_ARM_SSVE describes the
streaming mode SVE registers and NT_ARM_SVE describes the
non-streaming mode SVE registers.”…””}”(hj¡  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M!hj  ubhÌ)”}”(hŒÐIn this description a register set is referred to as being "live" when
the target is in the appropriate streaming or non-streaming mode and is
using data beyond the subset shared with the FPSIMD Vn registers.”h]”hŒÔIn this description a register set is referred to as being â€œliveâ€ when
the target is in the appropriate streaming or non-streaming mode and is
using data beyond the subset shared with the FPSIMD Vn registers.”…””}”(hj¯  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M&hj  ubhÌ)”}”(hŒRefer to [2] for definitions.”h]”hŒRefer to [2] for definitions.”…””}”(hj½  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M*hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjš  h²hh³hÊh´Nubah}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´M!hj‰  h²hubhÌ)”}”(hŒ?The regset data starts with struct user_sve_header, containing:”h]”hŒ?The regset data starts with struct user_sve_header, containing:”…””}”(hj×  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M,hj‰  h²hubjÂ  )”}”(hXJ  size

    Size of the complete regset, in bytes.
    This depends on vl and possibly on other things in the future.

    If a call to PTRACE_GETREGSET requests less data than the value of
    size, the caller can allocate a larger buffer and retry in order to
    read the complete regset.

max_size

    Maximum size in bytes that the regset can grow to for the target
    thread.  The regset won't grow bigger than this even if the target
    thread changes its vector length etc.

vl

    Target thread's current vector length, in bytes.

max_vl

    Maximum possible vector length for the target thread.

flags

    at most one of

        SVE_PT_REGS_FPSIMD

            SVE registers are not live (GETREGSET) or are to be made
            non-live (SETREGSET).

            The payload is of type struct user_fpsimd_state, with the same
            meaning as for NT_PRFPREG, starting at offset
            SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.

            Extra data might be appended in the future: the size of the
            payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).

            vq should be obtained using sve_vq_from_vl(vl).

            or

        SVE_PT_REGS_SVE

            SVE registers are live (GETREGSET) or are to be made live
            (SETREGSET).

            The payload contains the SVE register data, starting at offset
            SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
            size SVE_PT_SVE_SIZE(vq, flags);

    ... OR-ed with zero or more of the following flags, which have the same
    meaning and behaviour as the corresponding PR_SET_VL_* flags:

        SVE_PT_VL_INHERIT

        SVE_PT_VL_ONEXEC (SETREGSET only).

    If neither FPSIMD nor SVE flags are provided then no register
    payload is available, this is only possible when SME is implemented.

”h]”(hÌ)”}”(hŒsize”h]”hŒsize”…””}”(hjé  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M.hjå  ubjÂ  )”}”(hX  Size of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.

If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.
”h]”(hÌ)”}”(hŒeSize of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.”h]”hŒeSize of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.”…””}”(hjû  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M0hj÷  ubhÌ)”}”(hŒ If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.”h]”hŒ If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M3hj÷  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´M0hjå  ubhÌ)”}”(hŒmax_size”h]”hŒmax_size”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M7hjå  ubjÂ  )”}”(hŒªMaximum size in bytes that the regset can grow to for the target
thread.  The regset won't grow bigger than this even if the target
thread changes its vector length etc.
”h]”hÌ)”}”(hŒ©Maximum size in bytes that the regset can grow to for the target
thread.  The regset won't grow bigger than this even if the target
thread changes its vector length etc.”h]”hŒ«Maximum size in bytes that the regset can grow to for the target
thread.  The regset wonâ€™t grow bigger than this even if the target
thread changes its vector length etc.”…””}”(hj/  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M9hj+  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´M9hjå  ubhÌ)”}”(hŒvl”h]”hŒvl”…””}”(hjC  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M=hjå  ubjÂ  )”}”(hŒ1Target thread's current vector length, in bytes.
”h]”hÌ)”}”(hŒ0Target thread's current vector length, in bytes.”h]”hŒ2Target threadâ€™s current vector length, in bytes.”…””}”(hjU  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M?hjQ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´M?hjå  ubhÌ)”}”(hŒmax_vl”h]”hŒmax_vl”…””}”(hji  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MAhjå  ubjÂ  )”}”(hŒ6Maximum possible vector length for the target thread.
”h]”hÌ)”}”(hŒ5Maximum possible vector length for the target thread.”h]”hŒ5Maximum possible vector length for the target thread.”…””}”(hj{  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MChjw  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´MChjå  ubhÌ)”}”(hŒflags”h]”hŒflags”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MEhjå  ubjÂ  )”}”(hX†  at most one of

    SVE_PT_REGS_FPSIMD

        SVE registers are not live (GETREGSET) or are to be made
        non-live (SETREGSET).

        The payload is of type struct user_fpsimd_state, with the same
        meaning as for NT_PRFPREG, starting at offset
        SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.

        Extra data might be appended in the future: the size of the
        payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).

        vq should be obtained using sve_vq_from_vl(vl).

        or

    SVE_PT_REGS_SVE

        SVE registers are live (GETREGSET) or are to be made live
        (SETREGSET).

        The payload contains the SVE register data, starting at offset
        SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
        size SVE_PT_SVE_SIZE(vq, flags);

... OR-ed with zero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:

    SVE_PT_VL_INHERIT

    SVE_PT_VL_ONEXEC (SETREGSET only).

If neither FPSIMD nor SVE flags are provided then no register
payload is available, this is only possible when SME is implemented.

”h]”(hÌ)”}”(hŒat most one of”h]”hŒat most one of”…””}”(hj¡  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MGhj  ubjÂ  )”}”(hXë  SVE_PT_REGS_FPSIMD

    SVE registers are not live (GETREGSET) or are to be made
    non-live (SETREGSET).

    The payload is of type struct user_fpsimd_state, with the same
    meaning as for NT_PRFPREG, starting at offset
    SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.

    Extra data might be appended in the future: the size of the
    payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).

    vq should be obtained using sve_vq_from_vl(vl).

    or

SVE_PT_REGS_SVE

    SVE registers are live (GETREGSET) or are to be made live
    (SETREGSET).

    The payload contains the SVE register data, starting at offset
    SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
    size SVE_PT_SVE_SIZE(vq, flags);
”h]”(hÌ)”}”(hŒSVE_PT_REGS_FPSIMD”h]”hŒSVE_PT_REGS_FPSIMD”…””}”(hj³  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MIhj¯  ubjÂ  )”}”(hX§  SVE registers are not live (GETREGSET) or are to be made
non-live (SETREGSET).

The payload is of type struct user_fpsimd_state, with the same
meaning as for NT_PRFPREG, starting at offset
SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.

Extra data might be appended in the future: the size of the
payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).

vq should be obtained using sve_vq_from_vl(vl).

or
”h]”(hÌ)”}”(hŒNSVE registers are not live (GETREGSET) or are to be made
non-live (SETREGSET).”h]”hŒNSVE registers are not live (GETREGSET) or are to be made
non-live (SETREGSET).”…””}”(hjÅ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MKhjÁ  ubhÌ)”}”(hŒ¤The payload is of type struct user_fpsimd_state, with the same
meaning as for NT_PRFPREG, starting at offset
SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.”h]”hŒ¤The payload is of type struct user_fpsimd_state, with the same
meaning as for NT_PRFPREG, starting at offset
SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.”…””}”(hjÓ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MNhjÁ  ubhÌ)”}”(hŒ{Extra data might be appended in the future: the size of the
payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).”h]”hŒ{Extra data might be appended in the future: the size of the
payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).”…””}”(hjá  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MRhjÁ  ubhÌ)”}”(hŒ/vq should be obtained using sve_vq_from_vl(vl).”h]”hŒ/vq should be obtained using sve_vq_from_vl(vl).”…””}”(hjï  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MUhjÁ  ubhÌ)”}”(hŒor”h]”hŒor”…””}”(hjý  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MWhjÁ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´MKhj¯  ubhÌ)”}”(hŒSVE_PT_REGS_SVE”h]”hŒSVE_PT_REGS_SVE”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MYhj¯  ubjÂ  )”}”(hŒæSVE registers are live (GETREGSET) or are to be made live
(SETREGSET).

The payload contains the SVE register data, starting at offset
SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
size SVE_PT_SVE_SIZE(vq, flags);
”h]”(hÌ)”}”(hŒFSVE registers are live (GETREGSET) or are to be made live
(SETREGSET).”h]”hŒFSVE registers are live (GETREGSET) or are to be made live
(SETREGSET).”…””}”(hj#	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M[hj	  ubhÌ)”}”(hŒThe payload contains the SVE register data, starting at offset
SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
size SVE_PT_SVE_SIZE(vq, flags);”h]”hŒThe payload contains the SVE register data, starting at offset
SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
size SVE_PT_SVE_SIZE(vq, flags);”…””}”(hj1	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M^hj	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´M[hj¯  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´MIhj  ubhÌ)”}”(hŒ…... OR-ed with zero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:”h]”hŒ…... OR-ed with zero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:”…””}”(hjK	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mbhj  ubjÂ  )”}”(hŒ6SVE_PT_VL_INHERIT

SVE_PT_VL_ONEXEC (SETREGSET only).
”h]”(hÌ)”}”(hŒSVE_PT_VL_INHERIT”h]”hŒSVE_PT_VL_INHERIT”…””}”(hj]	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MehjY	  ubhÌ)”}”(hŒ"SVE_PT_VL_ONEXEC (SETREGSET only).”h]”hŒ"SVE_PT_VL_ONEXEC (SETREGSET only).”…””}”(hjk	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MghjY	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´Mehj  ubhÌ)”}”(hŒ‚If neither FPSIMD nor SVE flags are provided then no register
payload is available, this is only possible when SME is implemented.”h]”hŒ‚If neither FPSIMD nor SVE flags are provided then no register
payload is available, this is only possible when SME is implemented.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mihj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´MGhjå  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´M.hj‰  h²hubj;  )”}”(hhh]”(j@  )”}”(hX  The effects of changing the vector length and/or flags are equivalent to
those documented for PR_SVE_SET_VL.

The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.
”h]”(hÌ)”}”(hŒlThe effects of changing the vector length and/or flags are equivalent to
those documented for PR_SVE_SET_VL.”h]”hŒlThe effects of changing the vector length and/or flags are equivalent to
those documented for PR_SVE_SET_VL.”…””}”(hj 	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mmhjœ	  ubhÌ)”}”(hŒ©The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.”h]”hŒ©The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.”…””}”(hj®	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mphjœ	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒ«In the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
the header fields.  The SVE_PT_SVE_*() macros are provided to facilitate
access to the members.
”h]”hÌ)”}”(hŒªIn the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
the header fields.  The SVE_PT_SVE_*() macros are provided to facilitate
access to the members.”h]”hŒªIn the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
the header fields.  The SVE_PT_SVE_*() macros are provided to facilitate
access to the members.”…””}”(hjÆ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MthjÂ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒ°In either case, for SETREGSET it is permissible to omit the payload, in which
case only the vector length and flags are changed (along with any
consequences of those changes).
”h]”hÌ)”}”(hŒ¯In either case, for SETREGSET it is permissible to omit the payload, in which
case only the vector length and flags are changed (along with any
consequences of those changes).”h]”hŒ¯In either case, for SETREGSET it is permissible to omit the payload, in which
case only the vector length and flags are changed (along with any
consequences of those changes).”…””}”(hjÞ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MxhjÚ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒìIn systems supporting SME when in streaming mode a GETREGSET for
NT_REG_SVE will return only the user_sve_header with no register data,
similarly a GETREGSET for NT_REG_SSVE will not return any register data
when not in streaming mode.
”h]”hÌ)”}”(hŒëIn systems supporting SME when in streaming mode a GETREGSET for
NT_REG_SVE will return only the user_sve_header with no register data,
similarly a GETREGSET for NT_REG_SSVE will not return any register data
when not in streaming mode.”h]”hŒëIn systems supporting SME when in streaming mode a GETREGSET for
NT_REG_SVE will return only the user_sve_header with no register data,
similarly a GETREGSET for NT_REG_SSVE will not return any register data
when not in streaming mode.”…””}”(hjö	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M|hjò	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒBA GETREGSET for NT_ARM_SSVE will never return SVE_PT_REGS_FPSIMD.
”•—      h]”hÌ)”}”(hŒAA GETREGSET for NT_ARM_SSVE will never return SVE_PT_REGS_FPSIMD.”h]”hŒAA GETREGSET for NT_ARM_SSVE will never return SVE_PT_REGS_FPSIMD.”…””}”(hj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj

  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hXë  For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
requested VL is not supported, the effect will be the same as if the
payload were omitted, except that an EIO error is reported.  No
attempt is made to translate the payload data to the correct layout
for the vector length actually set.  The thread's FPSIMD state is
preserved, but the remaining bits of the SVE registers become
unspecified.  It is up to the caller to translate the payload layout
for the actual VL and retry.
”h]”hÌ)”}”(hXê  For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
requested VL is not supported, the effect will be the same as if the
payload were omitted, except that an EIO error is reported.  No
attempt is made to translate the payload data to the correct layout
for the vector length actually set.  The thread's FPSIMD state is
preserved, but the remaining bits of the SVE registers become
unspecified.  It is up to the caller to translate the payload layout
for the actual VL and retry.”h]”hXì  For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
requested VL is not supported, the effect will be the same as if the
payload were omitted, except that an EIO error is reported.  No
attempt is made to translate the payload data to the correct layout
for the vector length actually set.  The threadâ€™s FPSIMD state is
preserved, but the remaining bits of the SVE registers become
unspecified.  It is up to the caller to translate the payload layout
for the actual VL and retry.”…””}”(hj&
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mƒhj"
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hX  Where SME is implemented it is not possible to GETREGSET the register
state for normal SVE when in streaming mode, nor the streaming mode
register state when in normal mode, regardless of the implementation defined
behaviour of the hardware for sharing data between the two modes.
”h]”hÌ)”}”(hX  Where SME is implemented it is not possible to GETREGSET the register
state for normal SVE when in streaming mode, nor the streaming mode
register state when in normal mode, regardless of the implementation defined
behaviour of the hardware for sharing data between the two modes.”h]”hX  Where SME is implemented it is not possible to GETREGSET the register
state for normal SVE when in streaming mode, nor the streaming mode
register state when in normal mode, regardless of the implementation defined
behaviour of the hardware for sharing data between the two modes.”…””}”(hj>
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MŒhj:
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒ½Any SETREGSET of NT_ARM_SVE will exit streaming mode if the target was in
streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode
if the target was not in streaming mode.
”h]”hÌ)”}”(hŒ¼Any SETREGSET of NT_ARM_SVE will exit streaming mode if the target was in
streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode
if the target was not in streaming mode.”h]”hŒ¼Any SETREGSET of NT_ARM_SVE will exit streaming mode if the target was in
streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode
if the target was not in streaming mode.”…””}”(hjV
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M‘hjR
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hX  On systems that do not support SVE it is permitted to use SETREGSET to
write SVE_PT_REGS_FPSIMD formatted data via NT_ARM_SVE, in this case the
vector length should be specified as 0. This allows streaming mode to be
disabled on systems with SME but not SVE.
”h]”hÌ)”}”(hX  On systems that do not support SVE it is permitted to use SETREGSET to
write SVE_PT_REGS_FPSIMD formatted data via NT_ARM_SVE, in this case the
vector length should be specified as 0. This allows streaming mode to be
disabled on systems with SME but not SVE.”h]”hX  On systems that do not support SVE it is permitted to use SETREGSET to
write SVE_PT_REGS_FPSIMD formatted data via NT_ARM_SVE, in this case the
vector length should be specified as 0. This allows streaming mode to be
disabled on systems with SME but not SVE.”…””}”(hjn
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M•hjj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒ»If any register data is provided along with SVE_PT_VL_ONEXEC then the
registers data will be interpreted with the current vector length, not
the vector length configured for use on exec.
”h]”hÌ)”}”(hŒºIf any register data is provided along with SVE_PT_VL_ONEXEC then the
registers data will be interpreted with the current vector length, not
the vector length configured for use on exec.”h]”hŒºIf any register data is provided along with SVE_PT_VL_ONEXEC then the
registers data will be interpreted with the current vector length, not
the vector length configured for use on exec.”…””}”(hj†
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mšhj‚
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubj@  )”}”(hŒEThe effect of writing a partial, incomplete payload is unspecified.

”h]”hÌ)”}”(hŒCThe effect of writing a partial, incomplete payload is unspecified.”h]”hŒCThe effect of writing a partial, incomplete payload is unspecified.”…””}”(hjž
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mžhjš
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj™	  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´Mmhj‰  h²hubeh}”(h]”Œptrace-extensions”ah ]”h"]”Œ7. ptrace extensions”ah$]”h&]”uh1hµhh·h²hh³hÊh´Mubh¶)”}”(hhh]”(h»)”}”(hŒ8.  ELF coredump extensions”h]”hŒ8.  ELF coredump extensions”…””}”(hjÃ
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÀ
  h²hh³hÊh´M¢ubj;  )”}”(hhh]”j@  )”}”(hX  NT_ARM_SVE and NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process.  The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.
”h]”hÌ)”}”(hX  NT_ARM_SVE and NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process.  The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.”h]”hX  NT_ARM_SVE and NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process.  The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.”…””}”(hjØ
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¤hjÔ
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjÑ
  h²hh³hÊh´Nubah}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´M¤hjÀ
  h²hubeh}”(h]”Œelf-coredump-extensions”ah ]”h"]”Œ8. elf coredump extensions”ah$]”h&]”uh1hµhh·h²hh³hÊh´M¢ubh¶)”}”(hhh]”(h»)”}”(hŒ 9.  System runtime configuration”h]”hŒ 9.  System runtime configuration”…””}”(hjý
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjú
  h²hh³hÊh´Mªubj;  )”}”(hhh]”j@  )”}”(hŒÌTo mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:
”h]”hÌ)”}”(hŒËTo mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:”h]”hŒËTo mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¬hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubah}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´M¬hjú
  h²hubhÌ)”}”(hŒ'/proc/sys/abi/sve_default_vector_length”h]”hŒ'/proc/sys/abi/sve_default_vector_length”…””}”(hj,  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M°hjú
  h²hubjÂ  )”}”(hX.  Writing the text representation of an integer to this file sets the system
default vector length to the specified value rounded to a supported value
using the same rules as for setting vector length via PR_SVE_SET_VL.

The result can be determined by reopening the file and reading its
contents.

At boot, the default vector length is initially set to 64 or the maximum
supported vector length, whichever is smaller.  This determines the initial
vector length of the init process (PID 1).

Reading this file returns the current system default vector length.
”h]”(hÌ)”}”(hŒÙWriting the text representation of an integer to this file sets the system
default vector length to the specified value rounded to a supported value
using the same rules as for setting vector length via PR_SVE_SET_VL.”h]”hŒÙWriting the text representation of an integer to this file sets the system
default vector length to the specified value rounded to a supported value
using the same rules as for setting vector length via PR_SVE_SET_VL.”…””}”(hj>  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M²hj:  ubhÌ)”}”(hŒLThe result can be determined by reopening the file and reading its
contents.”h]”hŒLThe result can be determined by reopening the file and reading its
contents.”…””}”(hjL  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¶hj:  ubhÌ)”}”(hŒ¿At boot, the default vector length is initially set to 64 or the maximum
supported vector length, whichever is smaller.  This determines the initial
vector length of the init process (PID 1).”h]”hŒ¿At boot, the default vector length is initially set to 64 or the maximum
supported vector length, whichever is smaller.  This determines the initial
vector length of the init process (PID 1).”…””}”(hjZ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¹hj:  ubhÌ)”}”(hŒCReading this file returns the current system default vector length.”h]”hŒCReading this file returns the current system default vector length.”…””}”(hjh  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M½hj:  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´M²hjú
  h²hubj;  )”}”(hhh]”(j@  )”}”(hXO  At every execve() call, the new vector length of the new process is set to
the system default vector length, unless

  * PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
    calling thread, or

  * a deferred vector length change is pending, established via the
    PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
”h]”(hÌ)”}”(hŒsAt every execve() call, the new vector length of the new process is set to
the system default vector length, unless”h]”hŒsAt every execve() call, the new vector length of the new process is set to
the system default vector length, unless”…””}”(hjƒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¿hj  ubjÂ  )”}”(hŒÒ* PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
  calling thread, or

* a deferred vector length change is pending, established via the
  PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
”h]”j;  )”}”(hhh]”(j@  )”}”(hŒXPR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
calling thread, or
”h]”hÌ)”}”(hŒWPR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
calling thread, or”h]”hŒWPR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
calling thread, or”…””}”(hjœ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÂhj˜  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj•  ubj@  )”}”(hŒqa deferred vector length change is pending, established via the
PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
”h]”hÌ)”}”(hŒpa deferred vector length change is pending, established via the
PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).”h]”hŒpa deferred vector length change is pending, established via the
PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).”…””}”(hj´  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÅhj°  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj•  ubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´MÂhj‘  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  h³hÊh´MÂhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj|  h²hh³hÊh´Nubj@  )”}”(hŒ”Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.
”h]”hÌ)”}”(hŒ“Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.”h]”hŒ“Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.”…””}”(hjÞ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÈhjÚ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj|  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´M¿hjú
  h²hubeh}”(h]”Œsystem-runtime-configuration”ah ]”h"]”Œ9. system runtime configuration”ah$]”h&]”uh1hµhh·h²hh³hÊh´Mªubh¶)”}”(hhh]”(h»)”}”(hŒ10.  Perf extensions”h]”hŒ10.  Perf extensions”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj   h²hh³hÊh´MÌubj;  )”}”(hhh]”(j@  )”}”(hŒÂThe arm64 specific DWARF standard [5] added the VG (Vector Granule) register
at index 46. This register is used for DWARF unwinding when variable length
SVE registers are pushed onto the stack.
”h]”hÌ)”}”(hŒÁThe arm64 specific DWARF standard [5] added the VG (Vector Granule) register
at index 46. This register is used for DWARF unwinding when variable length
SVE registers are pushed onto the stack.”h]”hŒÁThe arm64 specific DWARF standard [5] added the VG (Vector Granule) register
at index 46. This register is used for DWARF unwinding when variable length
SVE registers are pushed onto the stack.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÎhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubj@  )”}”(hŒUIts value is equivalent to the current SVE vector length (VL) in bits divided
by 64.
”h]”hÌ)”}”(hŒTIts value is equivalent to the current SVE vector length (VL) in bits divided
by 64.”h]”hŒTIts value is equivalent to the current SVE vector length (VL) in bits divided
by 64.”…””}”(hj0  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÒhj,  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubj@  )”}”(hŒŠThe value is included in Perf samples in the regs[46] field if
PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.
”h]”hÌ)”}”(hŒ‰The value is included in Perf samples in the regs[46] field if
PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.”h]”hŒ‰The value is included in Perf samples in the regs[46] field if
PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.”…””}”(hjH  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÕhjD  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubj@  )”}”(hŒ^The value is the current value at the time the sample was taken, and it can
change over time.
”h]”hÌ)”}”(hŒ]The value is the current value at the time the sample was taken, and it can
change over time.”h]”hŒ]The value is the current value at the time the sample was taken, and it can
change over time.”…””}”(hj`  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MØhj\  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubj@  )”}”(hŒsIf the system doesn't support SVE when perf_event_open is called with these
settings, the event will fail to open.
”h]”hÌ)”}”(hŒrIf the system doesn't support SVE when perf_event_open is called with these
settings, the event will fail to open.”h]”hŒtIf the system doesnâ€™t support SVE when perf_event_open is called with these
settings, the event will fail to open.”…””}”(hjx  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÛhjt  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´MÎhj   h²hubh¶)”}”(hhh]”(h»)”}”(hŒ1Appendix A.  SVE programmer's model (informative)”h]”hŒ3Appendix A.  SVE programmerâ€™s model (informative)”…””}”(hj•  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj’  h²hh³hÊh´MßubhÌ)”}”(hŒŽThis section provides a minimal description of the additions made by SVE to the
ARMv8-A programmer's model that are relevant to this document.”h]”hŒThis section provides a minimal description of the additions made by SVE to the
ARMv8-A programmerâ€™s model that are relevant to this document.”…””}”(hj£  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Máhj’  h²hubhÌ)”}”(hŒyNote: This section is for information only and not intended to be complete or
to replace any architectural specification.”h]”hŒyNote: This section is for information only and not intended to be complete or
to replace any architectural specification.”…””}”(hj±  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mähj’  h²hubeh}”(h]”Œ-appendix-a-sve-programmer-s-model-informative”ah ]”h"]”Œ0appendix a. sve programmer's model (informative)”ah$]”h&]”uh1hµhj   h²hh³hÊh´Mßubeh}”(h]”Œperf-extensions”ah ]”h"]”Œ10. perf extensions”ah$]”h&]”uh1hµhh·h²hh³hÊh´MÌubh¶)”}”(hhh]”(h»)”}”(hŒA.1.  Registers”h]”hŒA.1.  Registers”…””}”(hjÒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÏ  h²hh³hÊh´MèubhÌ)”}”(hŒ%In A64 state, SVE adds the following:”h]”hŒ%In A64 state, SVE adds the following:”…””}”(hjà  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MêhjÏ  h²hubj;  )”}”(hhh]”(j@  )”}”(hŒÒ32 8VL-bit vector registers Z0..Z31
For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.

A register write using a Vn register name zeros all bits of the corresponding
Zn except for bits [127:0].
”h]”(hÌ)”}”(hŒf32 8VL-bit vector registers Z0..Z31
For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.”h]”hŒf32 8VL-bit vector registers Z0..Z31
For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.”…””}”(hjõ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mìhjñ  ubhÌ)”}”(hŒiA register write using a Vn register name zeros all bits of the corresponding
Zn except for bits [127:0].”h]”hŒiA register write using a Vn register name zeros all bits of the corresponding
Zn except for bits [127:0].”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mïhjñ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubj@  )”}”(hŒ&16 VL-bit predicate registers P0..P15
”h]”hÌ)”}”(hŒ%16 VL-bit predicate registers P0..P15”h]”hŒ%16 VL-bit predicate registers P0..P15”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mòhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubj@  )”}”(hŒM1 VL-bit special-purpose predicate register FFR (the "first-fault register")
”h]”hÌ)”}”(hŒL1 VL-bit special-purpose predicate register FFR (the "first-fault register")”h]”hŒP1 VL-bit special-purpose predicate register FFR (the â€œfirst-fault registerâ€)”…””}”(hj3  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Môhj/  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubj@  )”}”(hŒða VL "pseudo-register" that determines the size of each vector register

The SVE instruction set architecture provides no way to write VL directly.
Instead, it can be modified only by EL1 and above, by writing appropriate
system registers.
”h]”(hÌ)”}”(hŒGa VL "pseudo-register" that determines the size of each vector register”h]”hŒKa VL â€œpseudo-registerâ€ that determines the size of each vector register”…””}”(hjK  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MöhjG  ubhÌ)”}”(hŒ¦The SVE instruction set architecture provides no way to write VL directly.
Instead, it can be modified only by EL1 and above, by writing appropriate
system registers.”h]”hŒ¦The SVE instruction set architecture provides no way to write VL directly.
Instead, it can be modified only by EL1 and above, by writing appropriate
system registers.”…””}”(hjY  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MøhjG  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubj@  )”}”(hŒuThe value of VL can be configured at runtime by EL1 and above:
16 <= VL <= VLmax, where VL must be a multiple of 16.
”h]”hÌ)”}”(hŒtThe value of VL can be configured at runtime by EL1 and above:
16 <= VL <= VLmax, where VL must be a multiple of 16.”h]”hŒtThe value of VL can be configured at runtime by EL1 and above:
16 <= VL <= VLmax, where VL must be a multiple of 16.”…””}”(hjq  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mühjm  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubj@  )”}”(hŒ³The maximum vector length is determined by the hardware:
16 <= VLmax <= 256.

(The SVE architecture specifies 256, but permits future architecture
revisions to raise this limit.)
”h]”(hÌ)”}”(hŒLThe maximum vector length is determined by the hardware:
16 <= VLmax <= 256.”h]”hŒLThe maximum vector length is determined by the hardware:
16 <= VLmax <= 256.”…””}”(hj‰  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mÿhj…  ubhÌ)”}”(hŒd(The SVE architecture specifies 256, but permits future architecture
revisions to raise this limit.)”h]”hŒd(The SVE architecture specifies 256, but permits future architecture
revisions to raise this limit.)”…””}”(hj—  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj…  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubj@  )”}”(hXZ  FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
operations in a similar way to the way in which they interact with ARMv8
floating-point operations::

       8VL-1                       128               0  bit index
      +----          ////            -----------------+
   Z0 |                               :       V0      |
    :                                          :
   Z7 |                               :       V7      |
   Z8 |                               :     * V8      |
    :                                       :  :
  Z15 |                               :     *V15      |
  Z16 |                               :      V16      |
    :                                          :
  Z31 |                               :      V31      |
      +----          ////            -----------------+
                                               31    0
       VL-1                  0                +-------+
      +----       ////      --+          FPSR |       |
   P0 |                       |               +-------+
    : |                       |         *FPCR |       |
  P15 |                       |               +-------+
      +----       ////      --+
  FFR |                       |               +-----+
      +----       ////      --+            VL |     |
                                              +-----+
”h]”(hÌ)”}”(hŒ²FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
operations in a similar way to the way in which they interact with ARMv8
floating-point operations::”h]”hŒ±FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
operations in a similar way to the way in which they interact with ARMv8
floating-point operations:”…””}”(hj¯  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj«  ubhŒliteral_block”“”)”}”(hXy       8VL-1                       128               0  bit index
    +----          ////            -----------------+
 Z0 |                               :       V0      |
  :                                          :
 Z7 |                               :       V7      |
 Z8 |                               :     * V8      |
  :                                       :  :
Z15 |                               :     *V15      |
Z16 |                               :      V16      |
  :                                          :
Z31 |                               :      V31      |
    +----          ////            -----------------+
                                             31    0
     VL-1                  0                +-------+
    +----       ////      --+          FPSR |       |
 P0 |                       |               +-------+
  : |                       |         *FPCR |       |
P15 |                       |               +-------+
    +----       ////      --+
FFR |                       |               +-----+
    +----       ////      --+            VL |     |
                                            +-----+”h]”hXy       8VL-1                       128               0  bit index
    +----          ////            -----------------+
 Z0 |                               :       V0      |
  :                                          :
 Z7 |                               :       V7      |
 Z8 |                               :     * V8      |
  :                                       :  :
Z15 |                               :     *V15      |
Z16 |                               :      V16      |
  :                                          :
Z31 |                               :      V31      |
    +----          ////            -----------------+
                                             31    0
     VL-1                  0                +-------+
    +----       ////      --+          FPSR |       |
 P0 |                       |               +-------+
  : |                       |         *FPCR |       |
P15 |                       |               +-------+
    +----       ////      --+
FFR |                       |               +-----+
    +----       ////      --+            VL |     |
                                            +-----+”…””}”hj¿  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1j½  h³hÊh´M	hj«  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hjî  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´MìhjÏ  h²hubjã  )”}”(hhh]”jè  )”}”(hŒŒ(*) callee-save:
This only applies to bits [63:0] of Z-/V-registers.
FPCR contains callee-save and caller-save bits.  See [4] for details.

”h]”(jî  )”}”(hŒ(*) callee-save:”h]”hŒ(*) callee-save:”…””}”(hjâ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´M#hjÞ  ubjþ  )”}”(hhh]”hÌ)”}”(hŒyThis only applies to bits [63:0] of Z-/V-registers.
FPCR contains callee-save and caller-save bits.  See [4] for details.”h]”hŒyThis only applies to bits [63:0] of Z-/V-registers.
FPCR contains callee-save and caller-save bits.  See [4] for details.”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M!hjð  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hjÞ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´M#hjÛ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hjÏ  h²hh³hÊh´Nubeh}”(h]”Œa-1-registers”ah ]”h"]”Œa.1. registers”ah$]”h&]”uh1hµhh·h²hh³hÊh´Mèubh¶)”}”(hhh]”(h»)”}”(hŒA.2.  Procedure call standard”h]”hŒA.2.  Procedure call standard”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´M&ubhÌ)”}”(hŒrThe ARMv8-A base procedure call standard is extended as follows with respect to
the additional SVE register state:”h]”hŒrThe ARMv8-A base procedure call standard is extended as follows with respect to
the additional SVE register state:”…””}”(hj,  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M(hj  h²hubj;  )”}”(hhh]”(j@  )”}”(hŒHAll SVE register bits that are not shared with FP/SIMD are caller-save.
”h]”hÌ)”}”(hŒGAll SVE register bits that are not shared with FP/SIMD are caller-save.”h]”hŒGAll SVE register bits that are not shared with FP/SIMD are caller-save.”…””}”(hjA  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M+hj=  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj:  h²hh³hÊh´Nubj@  )”}”(hŒ­Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.

This follows from the way these bits are mapped to V8..V15, which are caller-
save in the base procedure call standard.

”h]”(hÌ)”}”(hŒ2Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.”h]”hŒ2Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.”…””}”(hjY  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M-hjU  ubhÌ)”}”(hŒwThis follows from the way these bits are mapped to V8..V15, which are caller-
save in the base procedure call standard.”h]”hŒwThis follows from the way these bits are mapped to V8..V15, which are caller-
save in the base procedure call standard.”…””}”(hjg  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M/hjU  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj:  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´M+hj  h²hubh¶)”}”(hhh]”(h»)”}”(hŒ/Appendix B.  ARMv8-A FP/SIMD programmer's model”h]”hŒ1Appendix B.  ARMv8-A FP/SIMD programmerâ€™s model”…””}”(hj„  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´M4ubhÌ)”}”(hŒyNote: This section is for information only and not intended to be complete or
to replace any architectural specification.”h]”hŒyNote: This section is for information only and not intended to be complete or
to replace any architectural specification.”…””}”(hj’  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M6hj  h²hubhÌ)”}”(hŒ"Refer to [4] for more information.”h]”hŒ"Refer to [4] for more information.”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M9hj  h²hubhÌ)”}”(hŒCARMv8-A defines the following floating-point / SIMD register state:”h]”hŒCARMv8-A defines the following floating-point / SIMD register state:”…””}”(hj®  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M;hj  h²hubj;  )”}”(hhh]”(j@  )”}”(hŒ#32 128-bit vector registers V0..V31”h]”hÌ)”}”(hjÁ  h]”hŒ#32 128-bit vector registers V0..V31”…””}”(hjÃ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M=hj¿  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj¼  h²hh³hÊh´Nubj@  )”}”(hŒ-2 32-bit status/control registers FPSR, FPCR
”h]”hÌ)”}”(hŒ,2 32-bit status/control registers FPSR, FPCR”h]”hŒ,2 32-bit status/control registers FPSR, FPCR”…””}”(hjÚ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M>hjÖ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j?  hj¼  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jY  jZ  uh1j:  h³hÊh´M=hj  h²hubj¾  )”}”(hX§        127           0  bit index
     +---------------+
  V0 |               |
   : :               :
  V7 |               |
* V8 |               |
:  : :               :
*V15 |               |
 V16 |               |
   : :               :
 V31 |               |
     +---------------+

              31    0
             +-------+
        FPSR |       |
             +-------+
       *FPCR |       |
             +-------+”h]”hX§        127           0  bit index
     +---------------+
  V0 |               |
   : :               :
  V7 |               |
* V8 |               |
:  : :               :
*V15 |               |
 V16 |               |
   : :               :
 V31 |               |
     +---------------+

              31    0
             +-------+
        FPSR |       |
             +-------+
       *FPCR |       |
             +-------+”…””}”hjô  sbah}”(h]”h ]”h"]”h$]”h&]”jÍ  jÎ  uh1j½  h³hÊh´MBhj  h²hubjã  )”}”(hhh]”jè  )”}”(hŒ€(*) callee-save:
This only applies to bits [63:0] of V-registers.
FPCR contains a mixture of callee-save and caller-save bits.

”h]”(jî  )”}”(hŒ(*) callee-save:”h]”hŒ(*) callee-save:”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´MYhj  ubjþ  )”}”(hhh]”hÌ)”}”(hŒmThis only applies to bits [63:0] of V-registers.
FPCR contains a mixture of callee-save and caller-save bits.”h]”hŒmThis only applies to bits [63:0] of V-registers.
FPCR contains a mixture of callee-save and caller-save bits.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MWhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´MYhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hj  h²hh³hÊh´Nubeh}”(h]”Œ-appendix-b-armv8-a-fp-simd-programmer-s-model”ah ]”h"]”Œ.appendix b. armv8-a fp/simd programmer's model”ah$]”h&]”uh1hµhj  h²hh³hÊh´M4ubh¶)”}”(hhh]”(h»)”}”(hŒ
References”h]”hŒ
References”…””}”(hjE  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjB  h²hh³hÊh´M\ubjã  )”}”(hhh]”(jè  )”}”(hŒR[1] arch/arm64/include/uapi/asm/sigcontext.h
AArch64 Linux signal ABI definitions
”h]”(jî  )”}”(hŒ,[1] arch/arm64/include/uapi/asm/sigcontext.h”h]”hŒ,[1] arch/arm64/include/uapi/asm/sigcontext.h”…””}”(hjZ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´M_hjV  ubjþ  )”}”(hhh]”hÌ)”}”(hŒ$AArch64 Linux signal ABI definitions”h]”hŒ$AArch64 Linux signal ABI definitions”…””}”(hjk  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M_hjh  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hjV  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´M_hjS  ubjè  )”}”(hŒN[2] arch/arm64/include/uapi/asm/ptrace.h
AArch64 Linux ptrace ABI definitions
”h]”(jî  )”}”(hŒ([2] arch/arm64/include/uapi/asm/ptrace.h”h]”hŒ([2] arch/arm64/include/uapi/asm/ptrace.h”…””}”(hj‰  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´Mbhj…  ubjþ  )”}”(hhh]”hÌ)”}”(hŒ$AArch64 Linux ptrace ABI definitions”h]”hŒ$AArch64 Linux ptrace ABI definitions”…””}”(hjš  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mbhj—  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hj…  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´MbhjS  h²hubeh}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hjB  h²hh³hÊh´NubhÌ)”}”(hŒ6[3] Documentation/arch/arm64/cpu-feature-registers.rst”h]”hŒ6[3] Documentation/arch/arm64/cpu-feature-registers.rst”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MdhjB  h²hubjã  )”}”(hhh]”jè  )”}”(hŒô[4] ARM IHI0055C
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
”h]”(jî  )”}”(hŒ[4] ARM IHI0055C”h]”hŒ[4] ARM IHI0055C”…””}”(hjÏ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jí  h³hÊh´MihjË  ubjþ  )”}”(hhh]”hÌ)”}”(hŒâhttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)”h]”(hÖ)”}”(hŒShttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf”h]”hŒShttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf”…””}”(hjä  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jæ  uh1hÕhjà  ubhŒ
”…””}”(hjà  h²hh³Nh´NubhÖ)”}”(hŒLhttp://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html”h]”hŒLhttp://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html”…””}”(hj÷  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jù  uh1hÕhjà  ubhŒB
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)”…””}”(hjà  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MghjÝ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jý  hjË  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jç  h³hÊh´MihjÈ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jâ  hjB  h²hh³hÊh´NubhÌ)”}”(hŒL[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst”h]”(hŒ[5] ”…””}”(hj"  h²hh³Nh´NubhÖ)”}”(hŒHhttps://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst”h]”hŒHhttps://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst”…””}”(hj*  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j,  uh1hÕhj"  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MkhjB  h²hubeh}”(h]”Œ
references”ah ]”h"]”Œ
references”ah$]”h&]”uh1hµhj  h²hh³hÊh´M\ubeh}”(h]”Œa-2-procedure-call-standard”ah ]”h"]”Œa.2. procedure call standard”ah$]”h&]”uh1hµhh·h²hh³hÊh´M&ubeh}”(h]”Œ3scalable-vector-extension-support-for-aarch64-linux”ah ]”h"]”Œ3scalable vector extension support for aarch64 linux”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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