€•      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ"/translations/zh_CN/arch/arm64/sme”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/zh_TW/arch/arm64/sme”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/it_IT/arch/arm64/sme”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ja_JP/arch/arm64/sme”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ko_KR/arch/arm64/sme”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/sp_SP/arch/arm64/sme”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ3Scalable Matrix Extension support for AArch64 Linux”h]”hŒ3Scalable Matrix Extension support for AArch64 Linux”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒ</var/lib/git/docbuild/linux/Documentation/arch/arm64/sme.rst”h KubhŒ	paragraph”“”)”}”(hŒThis document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Matrix Extension (SME).”h]”hŒThis document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Matrix Extension (SME).”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒîThis is an outline of the most important features and issues only and not
intended to be exhaustive.  It should be read in conjunction with the SVE
documentation in sve.rst which provides details on the Streaming SVE mode
included in SME.”h]”hŒîThis is an outline of the most important features and issues only and not
intended to be exhaustive.  It should be read in conjunction with the SVE
documentation in sve.rst which provides details on the Streaming SVE mode
included in SME.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒÊThis document does not aim to describe the SME architecture or programmer's
model.  To aid understanding, a minimal description of relevant programmer's
model features for SME is included in Appendix A.”h]”hŒÎThis document does not aim to describe the SME architecture or programmerâ€™s
model.  To aid understanding, a minimal description of relevant programmerâ€™s
model features for SME is included in Appendix A.”…””}”(hhÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒ1.  General”h]”hŒ1.  General”…””}”(hhæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhãhžhhŸh¶h KubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒŒPSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
present) ZTn register state and TPIDR2_EL0 are tracked per thread.
”h]”h¸)”}”(hŒ‹PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
present) ZTn register state and TPIDR2_EL0 are tracked per thread.”h]”hŒ‹PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
present) ZTn register state and TPIDR2_EL0 are tracked per thread.”…””}”(hhÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhûubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hX#  The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
AT_HWCAP2 entry.  Presence of this flag implies the presence of the SME
instructions and registers, and the Linux-specific system interfaces
described in this document.  SME is reported in /proc/cpuinfo as "sme".
”h]”h¸)”}”(hX"  The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
AT_HWCAP2 entry.  Presence of this flag implies the presence of the SME
instructions and registers, and the Linux-specific system interfaces
described in this document.  SME is reported in /proc/cpuinfo as "sme".”h]”hX&  The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
AT_HWCAP2 entry.  Presence of this flag implies the presence of the SME
instructions and registers, and the Linux-specific system interfaces
described in this document.  SME is reported in /proc/cpuinfo as â€œsmeâ€.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hX"  The presence of SME2 is reported to userspace via HWCAP2_SME2 in the
aux vector AT_HWCAP2 entry.  Presence of this flag implies the presence of
the SME2 instructions and ZT0, and the Linux-specific system interfaces
described in this document.  SME2 is reported in /proc/cpuinfo as "sme2".
”h]”h¸)”}”(hX!  The presence of SME2 is reported to userspace via HWCAP2_SME2 in the
aux vector AT_HWCAP2 entry.  Presence of this flag implies the presence of
the SME2 instructions and ZT0, and the Linux-specific system interfaces
described in this document.  SME2 is reported in /proc/cpuinfo as "sme2".”h]”hX%  The presence of SME2 is reported to userspace via HWCAP2_SME2 in the
aux vector AT_HWCAP2 entry.  Presence of this flag implies the presence of
the SME2 instructions and ZT0, and the Linux-specific system interfaces
described in this document.  SME2 is reported in /proc/cpuinfo as â€œsme2â€.”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj+  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hX›  Support for the execution of SME instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS
instruction, and checking that the value of the SME field is nonzero. [3]

It does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP2_SME instead.
”h]”(h¸)”}”(hŒÕSupport for the execution of SME instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS
instruction, and checking that the value of the SME field is nonzero. [3]”h]”hŒÕSupport for the execution of SME instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS
instruction, and checking that the value of the SME field is nonzero. [3]”…””}”(hjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K"hjC  ubh¸)”}”(hŒÃIt does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP2_SME instead.”h]”hŒÃIt does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP2_SME instead.”…””}”(hjU  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K&hjC  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hX$  There are a number of optional SME features, presence of these is reported
through AT_HWCAP2 through:

      HWCAP2_SME_I16I64
      HWCAP2_SME_F64F64
      HWCAP2_SME_I8I32
      HWCAP2_SME_F16F32
      HWCAP2_SME_B16F32
      HWCAP2_SME_F32F32
      HWCAP2_SME_FA64
      HWCAP2_SME2

This list may be extended over time as the SME architecture evolves.

These extensions are also reported via the CPU ID register ID_AA64SMFR0_EL1,
which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
cpu-feature-registers.txt for details.
”h]”(h¸)”}”(hŒeThere are a number of optional SME features, presence of these is reported
through AT_HWCAP2 through:”h]”hŒeThere are a number of optional SME features, presence of these is reported
through AT_HWCAP2 through:”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K*hji  ubhŒblock_quote”“”)”}”(hŒ‡HWCAP2_SME_I16I64
HWCAP2_SME_F64F64
HWCAP2_SME_I8I32
HWCAP2_SME_F16F32
HWCAP2_SME_B16F32
HWCAP2_SME_F32F32
HWCAP2_SME_FA64
HWCAP2_SME2
”h]”h¸)”}”(hŒ†HWCAP2_SME_I16I64
HWCAP2_SME_F64F64
HWCAP2_SME_I8I32
HWCAP2_SME_F16F32
HWCAP2_SME_B16F32
HWCAP2_SME_F32F32
HWCAP2_SME_FA64
HWCAP2_SME2”h]”hŒ†HWCAP2_SME_I16I64
HWCAP2_SME_F64F64
HWCAP2_SME_I8I32
HWCAP2_SME_F16F32
HWCAP2_SME_B16F32
HWCAP2_SME_F32F32
HWCAP2_SME_FA64
HWCAP2_SME2”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K-hj}  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h K-hji  ubh¸)”}”(hŒDThis list may be extended over time as the SME architecture evolves.”h]”hŒDThis list may be extended over time as the SME architecture evolves.”…””}”(hj•  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K6hji  ubh¸)”}”(hŒ¾These extensions are also reported via the CPU ID register ID_AA64SMFR0_EL1,
which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
cpu-feature-registers.txt for details.”h]”hŒ¾These extensions are also reported via the CPU ID register ID_AA64SMFR0_EL1,
which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
cpu-feature-registers.txt for details.”…””}”(hj£  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K8hji  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hX:  Debuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets.  The recommended
way of detecting support for these regsets is to connect to a target process
first and then attempt a

      ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).
”h]”(h¸)”}”(hŒüDebuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets.  The recommended
way of detecting support for these regsets is to connect to a target process
first and then attempt a”h]”hŒüDebuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets.  The recommended
way of detecting support for these regsets is to connect to a target process
first and then attempt a”…””}”(hj»  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K<hj·  ubj|  )”}”(hŒ6ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).
”h]”h¸)”}”(hŒ5ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).”h]”hŒ5ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).”…””}”(hjÍ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KAhjÉ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h KAhj·  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hŒüWhenever ZA register values are exchanged in memory between userspace and
the kernel, the register value is encoded in memory as a series of horizontal
vectors from 0 to VL/8-1 stored in the same endianness invariant format as is
used for SVE vectors.
”h]”h¸)”}”(hŒûWhenever ZA register values are exchanged in memory between userspace and
the kernel, the register value is encoded in memory as a series of horizontal
vectors from 0 to VL/8-1 stored in the same endianness invariant format as is
used for SVE vectors.”h]”hŒûWhenever ZA register values are exchanged in memory between userspace and
the kernel, the register value is encoded in memory as a series of horizontal
vectors from 0 to VL/8-1 stored in the same endianness invariant format as is
used for SVE vectors.”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KChjç  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubhú)”}”(hŒ˜On thread creation PSTATE.ZA and TPIDR2_EL0 are preserved unless CLONE_VM
is specified, in which case PSTATE.ZA is set to 0 and TPIDR2_EL0 is set to 0.
”h]”h¸)”}”(hŒ—On thread creation PSTATE.ZA and TPIDR2_EL0 are preserved unless CLONE_VM
is specified, in which case PSTATE.ZA is set to 0 and TPIDR2_EL0 is set to 0.”h]”hŒ—On thread creation PSTATE.ZA and TPIDR2_EL0 are preserved unless CLONE_VM
is specified, in which case PSTATE.ZA is set to 0 and TPIDR2_EL0 is set to 0.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KHhjÿ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhhöhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1hôhŸh¶h Khhãhžhubeh}”(h]”Œgeneral”ah ]”h"]”Œ
1. general”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒ2.  Vector lengths”h]”hŒ2.  Vector lengths”…””}”(hj*  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj'  hžhhŸh¶h KLubh¸)”}”(hŒòSME defines a second vector length similar to the SVE vector length which
controls the size of the streaming mode SVE vectors and the ZA matrix array.
The ZA matrix is square with each side having as many bytes as a streaming
mode SVE vector.”h]”hŒòSME defines a second vector length similar to the SVE vector length which
controls the size of the streaming mode SVE vectors and the ZA matrix array.
The ZA matrix is square with each side having as many bytes as a streaming
mode SVE vector.”…””}”(hj8  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KNhj'  hžhubeh}”(h]”Œvector-lengths”ah ]”h"]”Œ2. vector lengths”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KLubh¢)”}”(hhh]”(h§)”}”(hŒ3.  System call behaviour”h]”hŒ3.  System call behaviour”…””}”(hjQ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjN  hžhhŸh¶h KUubhõ)”}”(hhh]”(hú)”}”(hŒzOn syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
ZA matrix and ZTn (if present) are preserved.
”h]”h¸)”}”(hŒyOn syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
ZA matrix and ZTn (if present) are preserved.”h]”hŒyOn syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
ZA matrix and ZTn (if present) are preserved.”…””}”(hjf  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KWhjb  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj_  hžhhŸh¶h Nubhú)”}”(hŒhOn syscall PSTATE.SM will be cleared and the SVE registers will be handled
as per the standard SVE ABI.
”h]”h¸)”}”(hŒgOn syscall PSTATE.SM will be cleared and the SVE registers will be handled
as per the standard SVE ABI.”h]”hŒgOn syscall PSTATE.SM will be cleared and the SVE registers will be handled
as per the standard SVE ABI.”…””}”(hj~  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KZhjz  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj_  hžhhŸh¶h Nubhú)”}”(hŒhNone of the SVE registers, ZA or ZTn are used to pass arguments to
or receive results from any syscall.
”h]”h¸)”}”(hŒgNone of the SVE registers, ZA or ZTn are used to pass arguments to
or receive results from any syscall.”h]”hŒgNone of the SVE registers, ZA or ZTn are used to pass arguments to
or receive results from any syscall.”…””}”(hj–  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K]hj’  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj_  hžhhŸh¶h Nubhú)”}”(hŒYOn process creation (eg, clone()) the newly created process will have
PSTATE.SM cleared.
”h]”h¸)”}”(hŒXOn process creation (eg, clone()) the newly created process will have
PSTATE.SM cleared.”h]”hŒXOn process creation (eg, clone()) the newly created process will have
PSTATE.SM cleared.”…””}”(hj®  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K`hjª  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj_  hžhhŸh¶h Nubhú)”}”(hX  All other SME state of a thread, including the currently configured vector
length, the state of the PR_SME_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.

”h]”h¸)”}”(hX  All other SME state of a thread, including the currently configured vector
length, the state of the PR_SME_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.”h]”hX  All other SME state of a thread, including the currently configured vector
length, the state of the PR_SME_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.”…””}”(hjÆ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KchjÂ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj_  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h KWhjN  hžhubeh}”(h]”Œsystem-call-behaviour”ah ]”h"]”Œ3. system call behaviour”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KUubh¢)”}”(hhh]”(h§)”}”(hŒ4.  Signal handling”h]”hŒ4.  Signal handling”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjè  hžhhŸh¶h Kjubhõ)”}”(hhh]”(hú)”}”(hŒMSignal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.
”h]”h¸)”}”(hŒLSignal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.”h]”hŒLSignal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Klhjü  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒ‰A new signal frame record TPIDR2_MAGIC is added formatted as a struct
tpidr2_context to allow access to TPIDR2_EL0 from signal handlers.
”h]”h¸)”}”(hŒˆA new signal frame record TPIDR2_MAGIC is added formatted as a struct
tpidr2_context to allow access to TPIDR2_EL0 from signal handlers.”h]”hŒˆA new signal frame record TPIDR2_MAGIC is added formatted as a struct
tpidr2_context to allow access to TPIDR2_EL0 from signal handlers.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Knhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒ^A new signal frame record za_context encodes the ZA register contents on
signal delivery. [1]
”h]”h¸)”}”(hŒ]A new signal frame record za_context encodes the ZA register contents on
signal delivery. [1]”h]”hŒ]A new signal frame record za_context encodes the ZA register contents on
signal delivery. [1]”…””}”(hj0  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kqhj,  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒ|The signal frame record for ZA always contains basic metadata, in particular
the thread's vector length (in za_context.vl).
”h]”h¸)”}”(hŒ{The signal frame record for ZA always contains basic metadata, in particular
the thread's vector length (in za_context.vl).”h]”hŒ}The signal frame record for ZA always contains basic metadata, in particular
the threadâ€™s vector length (in za_context.vl).”…””}”(hjH  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KthjD  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒñThe ZA matrix may or may not be included in the record, depending on
the value of PSTATE.ZA.  The registers are present if and only if:
za_context.head.size >= ZA_SIG_CONTEXT_SIZE(sve_vq_from_vl(za_context.vl))
in which case PSTATE.ZA == 1.
”h]”h¸)”}”(hŒðThe ZA matrix may or may not be included in the record, depending on
the value of PSTATE.ZA.  The registers are present if and only if:
za_context.head.size >= ZA_SIG_CONTEXT_SIZE(sve_vq_from_vl(za_context.vl))
in which case PSTATE.ZA == 1.”h]”hŒðThe ZA matrix may or may not be included in the record, depending on
the value of PSTATE.ZA.  The registers are present if and only if:
za_context.head.size >= ZA_SIG_CONTEXT_SIZE(sve_vq_from_vl(za_context.vl))
in which case PSTATE.ZA == 1.”…””}”(hj`  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kwhj\  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒšIf matrix data is present, the remainder of the record has a vl-dependent
size and layout.  Macros ZA_SIG_* are defined [1] to facilitate access to
them.
”h]”h¸)”}”(hŒ™If matrix data is present, the remainder of the record has a vl-dependent
size and layout.  Macros ZA_SIG_* are defined [1] to facilitate access to
them.”h]”hŒ™If matrix data is present, the remainder of the record has a vl-dependent
size and layout.  Macros ZA_SIG_* are defined [1] to facilitate access to
them.”…””}”(hjx  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K|hjt  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒfThe matrix is stored as a series of horizontal vectors in the same format as
is used for SVE vectors.
”h]”h¸)”}”(hŒeThe matrix is stored as a series of horizontal vectors in the same format as
is used for SVE vectors.”h]”hŒeThe matrix is stored as a series of horizontal vectors in the same format as
is used for SVE vectors.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K€hjŒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hX  If the ZA context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space.  za_context is then written in the
extra space.  Refer to [1] for further details about this mechanism.
”h]”h¸)”}”(hX  If the ZA context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space.  za_context is then written in the
extra space.  Refer to [1] for further details about this mechanism.”h]”hX  If the ZA context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space.  za_context is then written in the
extra space.  Refer to [1] for further details about this mechanism.”…””}”(hj¨  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kƒhj¤  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hŒ[If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
be generated.
”h]”h¸)”}”(hŒZIf ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
be generated.”h]”hŒZIf ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
be generated.”…””}”(hjÀ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kˆhj¼  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubhú)”}”(hX	  The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a
standard signal frame header followed by a struct zt_context specifying
the number of ZTn registers supported by the system, then zt_context.nregs
blocks of 64 bytes of data per register.

”h]”h¸)”}”(hX  The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a
standard signal frame header followed by a struct zt_context specifying
the number of ZTn registers supported by the system, then zt_context.nregs
blocks of 64 bytes of data per register.”h]”hX  The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a
standard signal frame header followed by a struct zt_context specifying
the number of ZTn registers supported by the system, then zt_context.nregs
blocks of 64 bytes of data per register.”…””}”(hjØ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K‹hjÔ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjù  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h Klhjè  hžhubeh}”(h]”Œsignal-handling”ah ]”h"]”Œ4. signal handling”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kjubh¢)”}”(hhh]”(h§)”}”(hŒ5.  Signal return”h]”hŒ5.  Signal return”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjú  hžhhŸh¶h K’ubh¸)”}”(hŒ%When returning from a signal handler:”h]”hŒ%When returning from a signal handler:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K”hjú  hžhubhõ)”}”(hhh]”(hú)”}”(hŒ«If there is no za_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then ZA is disabled.
”h]”h¸)”}”(hŒªIf there is no za_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then ZA is disabled.”h]”hŒªIf there is no za_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then ZA is disabled.”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K–hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj  hžhhŸh¶h Nubhú)”}”(hŒŽIf za_context is present in the signal frame and contains matrix data then
PSTATE.ZA is set to 1 and ZA is populated with the specified data.
”h]”h¸)”}”(hŒIf za_context is present in the signal frame and contains matrix data then
PSTATE.ZA is set to 1 and ZA is populated with the specified data.”h]”hŒIf za_context is present in the signal frame and contains matrix data then
PSTATE.ZA is set to 1 and ZA is populated with the specified data.”…””}”(hj8  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kšhj4  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj  hžhhŸh¶h Nubhú)”}”(hŒ×The vector length cannot be changed via signal return.  If za_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.
”h]”h¸)”}”(hŒÖThe vector length cannot be changed via signal return.  If za_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.”h]”hŒÖThe vector length cannot be changed via signal return.  If za_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.”…””}”(hjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjL  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj  hžhhŸh¶h Nubhú)”}”(hŒ‚If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a
signal frame record for ZTn, resulting in a forced SIGSEGV.

”h]”h¸)”}”(hŒ€If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a
signal frame record for ZTn, resulting in a forced SIGSEGV.”h]”hŒ€If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a
signal frame record for ZTn, resulting in a forced SIGSEGV.”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¡hjd  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h K–hjú  hžhubeh}”(h]”Œsignal-return”ah ]”h"]”Œ5. signal return”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K’ubh¢)”}”(hhh]”(h§)”}”(hŒ6.  prctl extensions”h]”hŒ6.  prctl extensions”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjŠ  hžhhŸh¶h K¦ubh¸)”}”(hŒSSome new prctl() calls are added to allow programs to manage the SME vector
length:”h]”hŒSSome new prctl() calls are added to allow programs to manage the SME vector
length:”…””}”(hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¨hjŠ  hžhubh¸)”}”(hŒ'prctl(PR_SME_SET_VL, unsigned long arg)”h]”hŒ'prctl(PR_SME_SET_VL, unsigned long arg)”…””}”(hj©  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K«hjŠ  hžhubj|  )”}”(hX“
  Sets the vector length of the calling thread and related flags, where
arg == vl | flags.  Other threads of the calling process are unaffected.

vl is the desired vector length, where sve_vl_valid(vl) must be true.

flags:

    PR_SME_VL_INHERIT

        Inherit the current vector length across execve().  Otherwise, the
        vector length is reset to the system default at execve().  (See
        Section 9.)

    PR_SME_SET_VL_ONEXEC

        Defer the requested vector length change until the next execve()
        performed by this thread.

        The effect is equivalent to implicit execution of the following
        call immediately after the next execve() (if any) by the thread:

            prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)

        This allows launching of a new program with a different vector
        length, while avoiding runtime side effects in the caller.

        Without PR_SME_SET_VL_ONEXEC, the requested change takes effect
        immediately.


Return value: a nonnegative on success, or a negative value on error:
    EINVAL: SME not supported, invalid vector length requested, or
        invalid flags.


On success:

* Either the calling thread's vector length or the deferred vector length
  to be applied at the next execve() by the thread (dependent on whether
  PR_SME_SET_VL_ONEXEC is present in arg), is set to the largest value
  supported by the system that is less than or equal to vl.  If vl ==
  SVE_VL_MAX, the value set will be the largest value supported by the
  system.

* Any previously outstanding deferred vector length change in the calling
  thread is cancelled.

* The returned value describes the resulting configuration, encoded as for
  PR_SME_GET_VL.  The vector length reported in this value is the new
  current vector length for this thread if PR_SME_SET_VL_ONEXEC was not
  present in arg; otherwise, the reported vector length is the deferred
  vector length that will be applied at the next execve() by the calling
  thread.

* Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
  bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
  unspecified, including both streaming and non-streaming SVE state.
  Calling PR_SME_SET_VL with vl equal to the thread's current vector
  length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
  does not constitute a change to the vector length for this purpose.

* Changing the vector length causes PSTATE.ZA to be cleared.
  Calling PR_SME_SET_VL with vl equal to the thread's current vector
  length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
  does not constitute a change to the vector length for this purpose.

”h]”(h¸)”}”(hŒŽSets the vector length of the calling thread and related flags, where
arg == vl | flags.  Other threads of the calling process are unaffected.”h]”hŒŽSets the vector length of the calling thread and related flags, where
arg == vl | flags.  Other threads of the calling process are unaffected.”…””}”(hj»  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K­hj·  ubh¸)”}”(hŒEvl is the desired vector length, where sve_vl_valid(vl) must be true.”h]”hŒEvl is the desired vector length, where sve_vl_valid(vl) must be true.”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K°hj·  ubh¸)”}”(hŒflags:”h]”hŒflags:”…””}”(hj×  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K²hj·  ubj|  )”}”(hXÇ  PR_SME_VL_INHERIT

    Inherit the current vector length across execve().  Otherwise, the
    vector length is reset to the system default at execve().  (See
    Section 9.)

PR_SME_SET_VL_ONEXEC

    Defer the requested vector length change until the next execve()
    performed by this thread.

    The effect is equivalent to implicit execution of the following
    call immediately after the next execve() (if any) by the thread:

        prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)

    This allows launching of a new program with a different vector
    length, while avoiding runtime side effects in the caller.

    Without PR_SME_SET_VL_ONEXEC, the requested change takes effect
    immediately.

”h]”(h¸)”}”(hŒPR_SME_VL_INHERIT”h]”hŒPR_SME_VL_INHERIT”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K´hjå  ubj|  )”}”(hŒInherit the current vector length across execve().  Otherwise, the
vector length is reset to the system default at execve().  (See
Section 9.)
”h]”h¸)”}”(hŒŽInherit the current vector length across execve().  Otherwise, the
vector length is reset to the system default at execve().  (See
Section 9.)”h]”hŒŽInherit the current vector length across execve().  Otherwise, the
vector length is reset to the system default at execve().  (See
Section 9.)”…””}”(hjû  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¶hj÷  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h K¶hjå  ubh¸)”}”(hŒPR_SME_SET_VL_ONEXEC”h]”hŒPR_SME_SET_VL_ONEXEC”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kºhjå  ubj|  )”}”(hXÞ  Defer the requested vector length change until the next execve()
performed by this thread.

The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:

    prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)

This allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.

Without PR_SME_SET_VL_ONEXEC, the requested change takes effect
immediately.

”h]”(h¸)”}”(hŒZDefer the requested vector length change until the next execve()
performed by this thread.”h]”hŒZDefer the requested vector length change until the next execve()
performed by this thread.”…””}”(hj!  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¼hj  ubh¸)”}”(hŒ€The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:”h]”hŒ€The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¿hj  ubj|  )”}”(hŒ2prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)
”h]”h¸)”}”(hŒ1prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)”h]”hŒ1prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)”…””}”(hjA  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÂhj=  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h KÂhj  ubh¸)”}”(hŒyThis allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.”h]”hŒyThis allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.”…””}”(hjU  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÄhj  ubh¸)”}”(hŒLWithout PR_SME_SET_VL_ONEXEC, the requested change takes effect
immediately.”h]”hŒLWithout PR_SME_SET_VL_ONEXEC, the requested change takes effect
immediately.”…””}”(hjc  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÇhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h K¼hjå  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h K´hj·  ubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒ™Return value: a nonnegative on success, or a negative value on error:
EINVAL: SME not supported, invalid vector length requested, or
    invalid flags.

”h]”(hŒterm”“”)”}”(hŒEReturn value: a nonnegative on success, or a negative value on error:”h]”hŒEReturn value: a nonnegative on success, or a negative value on error:”…””}”(hjŠ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  hŸh¶h KÎhj„  ubhŒ
definition”“”)”}”(hhh]”j~  )”}”(hhh]”jƒ  )”}”(hŒOEINVAL: SME not supported, invalid vector length requested, or
invalid flags.

”h]”(j‰  )”}”(hŒ>EINVAL: SME not supported, invalid vector length requested, or”h]”hŒ>EINVAL: SME not supported, invalid vector length requested, or”…””}”(hj¤  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  hŸh¶h KÎhj   ubj™  )”}”(hhh]”h¸)”}”(hŒinvalid flags.”h]”hŒinvalid flags.”…””}”(hjµ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÍhj²  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j˜  hj   ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j‚  hŸh¶h KÎhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j}  hjš  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j˜  hj„  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j‚  hŸh¶h KÎhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j}  hj·  ubh¸)”}”(hŒOn success:”h]”hŒOn success:”…””}”(hjç  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÐhj·  ubhõ)”}”(hhh]”(hú)”}”(hXe  Either the calling thread's vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SME_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl.  If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.
”h]”h¸)”}”(hXd  Either the calling thread's vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SME_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl.  If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.”h]”hXf  Either the calling threadâ€™s vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SME_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl.  If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.”…””}”(hjü  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÒhjø  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjõ  ubhú)”}”(hŒ]Any previously outstanding deferred vector length change in the calling
thread is cancelled.
”h]”h¸)”}”(hŒ\Any previously outstanding deferred vector length change in the calling
thread is cancelled.”h]”hŒ\Any previously outstanding deferred vector length change in the calling
thread is cancelled.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÙhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjõ  ubhú)”}”(hXh  The returned value describes the resulting configuration, encoded as for
PR_SME_GET_VL.  The vector length reported in this value is the new
current vector length for this thread if PR_SME_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.
”h]”h¸)”}”(hXg  The returned value describes the resulting configuration, encoded as for
PR_SME_GET_VL.  The vector length reported in this value is the new
current vector length for this thread if PR_SME_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.”h]”hXg  The returned value describes the resulting configuration, encoded as for
PR_SME_GET_VL.  The vector length reported in this value is the new
current vector length for this thread if PR_SME_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.”…””}”(hj,  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÜhj(  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjõ  ubhú)”}”(hXŸ  Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified, including both streaming and non-streaming SVE state.
Calling PR_SME_SET_VL with vl equal to the thread's current vector
length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.
”h]”h¸)”}”(hXž  Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified, including both streaming and non-streaming SVE state.
Calling PR_SME_SET_VL with vl equal to the thread's current vector
length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.”h]”hX   Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified, including both streaming and non-streaming SVE state.
Calling PR_SME_SET_VL with vl equal to the threadâ€™s current vector
length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.”…””}”(hjD  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kãhj@  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjõ  ubhú)”}”(hX  Changing the vector length causes PSTATE.ZA to be cleared.
Calling PR_SME_SET_VL with vl equal to the thread's current vector
length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.

”h]”h¸)”}”(hX  Changing the vector length causes PSTATE.ZA to be cleared.
Calling PR_SME_SET_VL with vl equal to the thread's current vector
length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.”h]”hX  Changing the vector length causes PSTATE.ZA to be cleared.
Calling PR_SME_SET_VL with vl equal to the threadâ€™s current vector
length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KêhjX  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjõ  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h KÒhj·  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h K­hjŠ  hžhubh¸)”}”(hŒprctl(PR_SME_GET_VL)”h]”hŒprctl(PR_SME_GET_VL)”…””}”(hj|  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KðhjŠ  hžhubj|  )”}”(hXD  Gets the vector length of the calling thread.

The following flag may be OR-ed into the result:

    PR_SME_VL_INHERIT

        Vector length will be inherited across execve().

There is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).

To extract the vector length from the result, bitwise and it with
PR_SME_VL_LEN_MASK.

Return value: a nonnegative value on success, or a negative value on error:
    EINVAL: SME not supported.

”h]”(h¸)”}”(hŒ-Gets the vector length of the calling thread.”h]”hŒ-Gets the vector length of the calling thread.”…””}”(hjŽ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KòhjŠ  ubh¸)”}”(hŒ0The following flag may be OR-ed into the result:”h]”hŒ0The following flag may be OR-ed into the result:”…””}”(hjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KôhjŠ  ubj|  )”}”(hŒHPR_SME_VL_INHERIT

    Vector length will be inherited across execve().
”h]”(h¸)”}”(hŒPR_SME_VL_INHERIT”h]”hŒPR_SME_VL_INHERIT”…””}”(hj®  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Köhjª  ubj|  )”}”(hŒ1Vector length will be inherited across execve().
”h]”h¸)”}”(hŒ0Vector length will be inherited across execve().”h]”hŒ0Vector length will be inherited across execve().”…””}”(hjÀ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Køhj¼  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h Køhjª  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h KöhjŠ  ubh¸)”}”(hŒÍThere is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).”h]”hŒÍThere is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KúhjŠ  ubh¸)”}”(hŒUTo extract the vector length from the result, bitwise and it with
PR_SME_VL_LEN_MASK.”h]”hŒUTo extract the vector length from the result, bitwise and it with
PR_SME_VL_LEN_MASK.”…””}”(hjè  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KþhjŠ  ubj~  )”}”(hhh]”jƒ  )”}”(hŒhReturn value: a nonnegative value on success, or a negative value on error:
EINVAL: SME not supported.

”h]”(j‰  )”}”(hŒKReturn value: a nonnegative value on success, or a negative value on error:”h]”hŒKReturn value: a nonnegative value on success, or a negative value on error:”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  hŸh¶h Mhjù  ubj™  )”}”(hhh]”h¸)”}”(hŒEINVAL: SME not supported.”h]”hŒEINVAL: SME not supported.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j˜  hjù  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j‚  hŸh¶h Mhjö  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j}  hjŠ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h KòhjŠ  hžhubeh}”(h]”Œprctl-extensions”ah ]”h"]”Œ6. prctl extensions”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K¦ubh¢)”}”(hhh]”(h§)”}”(hŒ7.  ptrace extensions”h]”hŒ7.  ptrace extensions”…””}”(hj?  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj<  hžhhŸh¶h Mubhõ)”}”(hhh]”(hú)”}”(hŒ–A new regset NT_ARM_SSVE is defined for access to streaming mode SVE
state via PTRACE_GETREGSET and  PTRACE_SETREGSET, this is documented in
sve.rst.
”h]”h¸)”}”(hŒ•A new regset NT_ARM_SSVE is defined for access to streaming mode SVE
state via PTRACE_GETREGSET and  PTRACE_SETREGSET, this is documented in
sve.rst.”h]”hŒ•A new regset NT_ARM_SSVE is defined for access to streaming mode SVE
state via PTRACE_GETREGSET and  PTRACE_SETREGSET, this is documented in
sve.rst.”…””}”(hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjP  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjM  hžhhŸh¶h Nubhú)”}”(hŒA new regset NT_ARM_ZA is defined for ZA state for access to ZA state via
PTRACE_GETREGSET and PTRACE_SETREGSET.

Refer to [2] for definitions.
”h]”(h¸)”}”(hŒpA new regset NT_ARM_ZA is defined for ZA state for access to ZA state via
PTRACE_GETREGSET and PTRACE_SETREGSET.”h]”hŒpA new regset NT_ARM_ZA is defined for ZA state for access to ZA state via
PTRACE_GETREGSET and PTRACE_SETREGSET.”…””}”(hjl  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjh  ubh¸)”}”(hŒRefer to [2] for definitions.”h]”hŒRefer to [2] for definitions.”…””}”(hjz  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjh  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhjM  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h Mhj<  hžhubh¸)”}”(hŒ>The regset data starts with struct user_za_header, containing:”h]”hŒ>The regset data starts with struct user_za_header, containing:”…””}”(hj”  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj<  hžhubj|  )”}”(hXB  size

    Size of the complete regset, in bytes.
    This depends on vl and possibly on other things in the future.

    If a call to PTRACE_GETREGSET requests less data than the value of
    size, the caller can allocate a larger buffer and retry in order to
    read the complete regset.

max_size

    Maximum size in bytes that the regset can grow to for the target
    thread.  The regset won't grow bigger than this even if the target
    thread changes its vector length etc.

vl

    Target thread's current streaming vector length, in bytes.

max_vl

    Maximum possible streaming vector length for the target thread.

flags

    Zero or more of the following flags, which have the same
    meaning and behaviour as the corresponding PR_SET_VL_* flags:

        SME_PT_VL_INHERIT

        SME_PT_VL_ONEXEC (SETREGSET only).
”h]”(h¸)”}”(hŒsize”h]”hŒsize”…””}”(hj¦  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¢  ubj|  )”}”(hX  Size of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.

If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.
”h]”(h¸)”}”(hŒeSize of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.”h]”hŒeSize of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.”…””}”(hj¸  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj´  ubh¸)”}”(hŒ If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.”h]”hŒ If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.”…””}”(hjÆ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj´  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h Mhj¢  ubh¸)”}”(hŒmax_size”h]”hŒmax_size”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¢  ubj|  )”}”(hŒªMaximum size in bytes that the regset can grow to for the target
thread.  The regset won't grow bigger than this even if the target
thread changes its vector length etc.
”h]”h¸)”}”(hŒ©Maximum size in bytes that the regset can grow to for the target
thread.  The regset won't grow bigger than this even if the target
thread changes its vector length etc.”h]”hŒ«Maximum size in bytes that the regset can grow to for the target
thread.  The regset wonâ€™t grow bigger than this even if the target
thread changes its vector length etc.”…””}”(hjì  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjè  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h Mhj¢  ubh¸)”}”(hŒvl”h]”hŒvl”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M"hj¢  ubj|  )”}”(hŒ;Target thread's current streaming vector length, in bytes.
”h]”h¸)”}”(hŒ:Target thread's current streaming vector length, in bytes.”h]”hŒ<Target threadâ€™s current streaming vector length, in bytes.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M$hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h M$hj¢  ubh¸)”}”(hŒmax_vl”h]”hŒmax_vl”…””}”(hj&  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M&hj¢  ubj|  )”}”(hŒ@Maximum possible streaming vector length for the target thread.
”h]”h¸)”}”(hŒ?Maximum possible streaming vector length for the target thread.”h]”hŒ?Maximum possible streaming vector length for the target thread.”…””}”(hj8  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M(hj4  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h M(hj¢  ubh¸)”}”(hŒflags”h]”hŒflags”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M*hj¢  ubj|  )”}”(hŒ¶Zero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:

    SME_PT_VL_INHERIT

    SME_PT_VL_ONEXEC (SETREGSET only).
”h]”(h¸)”}”(hŒvZero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:”h]”hŒvZero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:”…””}”(hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M,hjZ  ubj|  )”}”(hŒ6SME_PT_VL_INHERIT

SME_PT_VL_ONEXEC (SETREGSET only).
”h]”(h¸)”}”(hŒSME_PT_VL_INHERIT”h]”hŒSME_PT_VL_INHERIT”…””}”(hjp  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M/hjl  ubh¸)”}”(hŒ"SME_PT_VL_ONEXEC (SETREGSET only).”h]”hŒ"SME_PT_VL_ONEXEC (SETREGSET only).”…””}”(hj~  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M1hjl  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h M/hjZ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h M,hj¢  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h Mhj<  hžhubhõ)”}”(hhh]”(hú)”}”(hX  The effects of changing the vector length and/or flags are equivalent to
those documented for PR_SME_SET_VL.

The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.
”h]”(h¸)”}”(hŒlThe effects of changing the vector length and/or flags are equivalent to
those documented for PR_SME_SET_VL.”h]”hŒlThe effects of changing the vector length and/or flags are equivalent to
those documented for PR_SME_SET_VL.”…””}”(hj¥  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M3hj¡  ubh¸)”}”(hŒ©The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.”h]”hŒ©The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M6hj¡  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒˆThe size and layout of the payload depends on the header fields.  The
ZA_PT_ZA*() macros are provided to facilitate access to the data.
”h]”h¸)”}”(hŒ‡The size and layout of the payload depends on the header fields.  The
ZA_PT_ZA*() macros are provided to facilitate access to the data.”h]”hŒ‡The size and layout of the payload depends on the header fields.  The
ZA_PT_ZA*() macros are provided to facilitate access to the data.”…””}”(hjË  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M:hjÇ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hX   In either case, for SETREGSET it is permissible to omit the payload, in which
case the vector length and flags are changed and PSTATE.ZA is set to 0
(along with any consequences of those changes).  If a payload is provided
then PSTATE.ZA will be set to 1.
”h]”h¸)”}”(hŒÿIn either case, for SETREGSET it is permissible to omit the payload, in which
case the vector length and flags are changed and PSTATE.ZA is set to 0
(along with any consequences of those changes).  If a payload is provided
then PSTATE.ZA will be set to 1.”h]”hŒÿIn either case, for SETREGSET it is permissible to omit the payload, in which
case the vector length and flags are changed and PSTATE.ZA is set to 0
(along with any consequences of those changes).  If a payload is provided
then PSTATE.ZA will be set to 1.”…””}”(hjã  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M=hjß  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hXW  For SETREGSET, if the requested VL is not supported, the effect will be the
same as if the payload were omitted, except that an EIO error is reported.
No attempt is made to translate the payload data to the correct layout
for the vector length actually set.  It is up to the caller to translate the
payload layout for the actual VL and retry.
”h]”h¸)”}”(hXV  For SETREGSET, if the requested VL is not supported, the effect will be the
same as if the payload were omitted, except that an EIO error is reported.
No attempt is made to translate the payload data to the correct layout
for the vector length actually set.  It is up to the caller to translate the
payload layout for the actual VL and retry.”h]”hXV  For SETREGSET, if the requested VL is not supported, the effect will be the
same as if the payload were omitted, except that an EIO error is reported.
No attempt is made to translate the payload data to the correct layout
for the vector length actually set.  It is up to the caller to translate the
payload layout for the actual VL and retry.”…””}”(hjû  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MBhj÷  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒDThe effect of writing a partial, incomplete payload is unspecified.
”h]”h¸)”}”(hŒCThe effect of writing a partial, incomplete payload is unspecified.”h]”hŒCThe effect of writing a partial, incomplete payload is unspecified.”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MHhj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒeA new regset NT_ARM_ZT is defined for access to ZTn state via
PTRACE_GETREGSET and PTRACE_SETREGSET.
”h]”h¸)”}”(hŒdA new regset NT_ARM_ZT is defined for access to ZTn state via
PTRACE_GETREGSET and PTRACE_SETREGSET.”h]”hŒdA new regset NT_ARM_ZT is defined for access to ZTn state via
PTRACE_GETREGSET and PTRACE_SETREGSET.”…””}”(hj+	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MJhj'	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒ<The NT_ARM_ZT regset consists of a single 512 bit register.
”h]”h¸)”}”(hŒ;The NT_ARM_ZT regset consists of a single 512 bit register.”h]”hŒ;The NT_ARM_ZT regset consists of a single 512 bit register.”…””}”(hjC	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MMhj?	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒGWhen PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.
”h]”h¸)”}”(hŒFWhen PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.”h]”hŒFWhen PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.”…””}”(hj[	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MOhjW	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒ-Writes to NT_ARM_ZT will set PSTATE.ZA to 1.
”h]”h¸)”}”(hŒ,Writes to NT_ARM_ZT will set PSTATE.ZA to 1.”h]”hŒ,Writes to NT_ARM_ZT will set PSTATE.ZA to 1.”…””}”(hjs	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MQhjo	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubhú)”}”(hŒ¼If any register data is provided along with SME_PT_VL_ONEXEC then the
registers data will be interpreted with the current vector length, not
the vector length configured for use on exec.

”h]”h¸)”}”(hŒºIf any register data is provided along with SME_PT_VL_ONEXEC then the
registers data will be interpreted with the current vector length, not
the vector length configured for use on exec.”h]”hŒºIf any register data is provided along with SME_PT_VL_ONEXEC then the
registers data will be interpreted with the current vector length, not
the vector length configured for use on exec.”…””}”(hj‹	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MShj‡	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjž  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h M3hj<  hžhubeh}”(h]”Œptrace-extensions”ah ]”h"]”Œ7. ptrace extensions”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Mubh¢)”}”(hhh]”(h§)”}”(hŒ8.  ELF coredump extensions”h]”hŒ8.  ELF coredump extensions”…””}”(hj°	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj­	  hžhhŸh¶h MYubhõ)”}”(hhh]”(hú)”}”(hX  NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process.  The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.
”h]”h¸)”}”(hX  NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process.  The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.”h]”hX  NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process.  The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.”…””}”(hjÅ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M[hjÁ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj¾	  hžhhŸh¶h Nubhú)”}”(hX   A NT_ARM_ZA note will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
when the coredump was generated.
”h]”h¸)”}”(hŒÿA NT_ARM_ZA note will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
when the coredump was generated.”h]”hŒÿA NT_ARM_ZA note will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
when the coredump was generated.”…””}”(hjÝ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M`hjÙ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj¾	  hžhhŸh¶h Nubhú)”}”(hX   A NT_ARM_ZT note will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread
when the coredump was generated.
”h]”h¸)”}”(hŒÿA NT_ARM_ZT note will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread
when the coredump was generated.”h]”hŒÿA NT_ARM_ZT note will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread
when the coredump was generated.”…””}”(hjõ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mehjñ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj¾	  hžhhŸh¶h Nubhú)”}”(hŒ·The NT_ARM_TLS note will be extended to two registers, the second register
will contain TPIDR2_EL0 on systems that support SME and will be read as
zero with writes ignored otherwise.
”h]”h¸)”}”(hŒ¶The NT_ARM_TLS note will be extended to two registers, the second register
will contain TPIDR2_EL0 on systems that support SME and will be read as
zero with writes ignored otherwise.”h]”hŒ¶The NT_ARM_TLS note will be extended to two registers, the second register
will contain TPIDR2_EL0 on systems that support SME and will be read as
zero with writes ignored otherwise.”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mjhj	
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj¾	  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h M[hj­	  hžhubeh}”(h]”Œelf-coredump-extensions”ah ]”h"]”Œ8. elf coredump extensions”ah$]”h&]”uh1h¡hh£hžhhŸh¶h MYubh¢)”}”(hhh]”(h§)”}”(hŒ 9.  System runtime configuration”h]”hŒ 9.  System runtime configuration”…””}”(hj2
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj/
  hžhhŸh¶h Moubhõ)”}”(hhh]”hú)”}”(hŒÌTo mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:
”h]”h¸)”}”(hŒËTo mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:”h]”hŒËTo mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:”…””}”(hjG
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MqhjC
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj@
  hžhhŸh¶h Nubah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h Mqhj/
  hžhubh¸)”}”(hŒ'/proc/sys/abi/sme_default_vector_length”h]”hŒ'/proc/sys/abi/sme_default_vector_length”…””}”(hja
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Muhj/
  hžhubj|  )”}”(hX<  Writing the text representation of an integer to this file sets the system
default vector length to the specified value rounded to a supported value
using the same rules as for setting vector length via PR_SME_SET_VL.

The result can be determined by reopening the file and reading its
contents.

At boot, the default vector length is initially set to 32 or the maximum
supported vector length, whichever is smaller and supported.  This
determines the initial vector length of the init process (PID 1).

Reading this file returns the current system default vector length.
”h]”(h¸)”}”(hŒÙWriting the text representation of an integer to this file sets the system
default vector length to the specified value rounded to a supported value
using the same rules as for setting vector length via PR_SME_SET_VL.”h]”hŒÙWriting the text representation of an integer to this file sets the system
default vector length to the specified value rounded to a supported value
using the same rules as for setting vector length via PR_SME_SET_VL.”…””}”(hjs
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mwhjo
  ubh¸)”}”(hŒLThe result can be determined by reopening the file and reading its
contents.”h]”hŒLThe result can be determined by reopening the file and reading its
contents.”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M{hjo
  ubh¸)”}”(hŒÍAt boot, the default vector length is initially set to 32 or the maximum
supported vector length, whichever is smaller and supported.  This
determines the initial vector length of the init process (PID 1).”h]”hŒÍAt boot, the default vector length is initially set to 32 or the maximum
supported vector length, whichever is smaller and supported.  This
determines the initial vector length of the init process (PID 1).”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M~hjo
  ubh¸)”}”(hŒCReading this file returns the current system default vector length.”h]”hŒCReading this file returns the current system default vector length.”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M‚hjo
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h Mwhj/
  hžhubhõ)”}”(hhh]”(hú)”}”(hXO  At every execve() call, the new vector length of the new process is set to
the system default vector length, unless

  * PR_SME_VL_INHERIT (or equivalently SME_PT_VL_INHERIT) is set for the
    calling thread, or

  * a deferred vector length change is pending, established via the
    PR_SME_SET_VL_ONEXEC flag (or SME_PT_VL_ONEXEC).
”h]”(h¸)”}”(hŒsAt every execve() call, the new vector length of the new process is set to
the system default vector length, unless”•÷:      h]”hŒsAt every execve() call, the new vector length of the new process is set to
the system default vector length, unless”…””}”(hj¸
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M„hj´
  ubj|  )”}”(hŒÒ* PR_SME_VL_INHERIT (or equivalently SME_PT_VL_INHERIT) is set for the
  calling thread, or

* a deferred vector length change is pending, established via the
  PR_SME_SET_VL_ONEXEC flag (or SME_PT_VL_ONEXEC).
”h]”hõ)”}”(hhh]”(hú)”}”(hŒXPR_SME_VL_INHERIT (or equivalently SME_PT_VL_INHERIT) is set for the
calling thread, or
”h]”h¸)”}”(hŒWPR_SME_VL_INHERIT (or equivalently SME_PT_VL_INHERIT) is set for the
calling thread, or”h]”hŒWPR_SME_VL_INHERIT (or equivalently SME_PT_VL_INHERIT) is set for the
calling thread, or”…””}”(hjÑ
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M‡hjÍ
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjÊ
  ubhú)”}”(hŒqa deferred vector length change is pending, established via the
PR_SME_SET_VL_ONEXEC flag (or SME_PT_VL_ONEXEC).
”h]”h¸)”}”(hŒpa deferred vector length change is pending, established via the
PR_SME_SET_VL_ONEXEC flag (or SME_PT_VL_ONEXEC).”h]”hŒpa deferred vector length change is pending, established via the
PR_SME_SET_VL_ONEXEC flag (or SME_PT_VL_ONEXEC).”…””}”(hjé
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MŠhjå
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhjÊ
  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h M‡hjÆ
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j{  hŸh¶h M‡hj´
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhj±
  hžhhŸh¶h Nubhú)”}”(hŒ•Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.

”h]”h¸)”}”(hŒ“Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.”h]”hŒ“Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj±
  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h M„hj/
  hžhubh¢)”}”(hhh]”(h§)”}”(hŒ1Appendix A.  SME programmer's model (informative)”h]”hŒ3Appendix A.  SME programmerâ€™s model (informative)”…””}”(hj0  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj-  hžhhŸh¶h M’ubh¸)”}”(hŒŽThis section provides a minimal description of the additions made by SME to the
ARMv8-A programmer's model that are relevant to this document.”h]”hŒThis section provides a minimal description of the additions made by SME to the
ARMv8-A programmerâ€™s model that are relevant to this document.”…””}”(hj>  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M”hj-  hžhubh¸)”}”(hŒyNote: This section is for information only and not intended to be complete or
to replace any architectural specification.”h]”hŒyNote: This section is for information only and not intended to be complete or
to replace any architectural specification.”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M—hj-  hžhubeh}”(h]”Œ-appendix-a-sme-programmer-s-model-informative”ah ]”h"]”Œ0appendix a. sme programmer's model (informative)”ah$]”h&]”uh1h¡hj/
  hžhhŸh¶h M’ubeh}”(h]”Œsystem-runtime-configuration”ah ]”h"]”Œ9. system runtime configuration”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Moubh¢)”}”(hhh]”(h§)”}”(hŒA.1.  Registers”h]”hŒA.1.  Registers”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjj  hžhhŸh¶h M›ubh¸)”}”(hŒ%In A64 state, SME adds the following:”h]”hŒ%In A64 state, SME adds the following:”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjj  hžhubhõ)”}”(hhh]”(hú)”}”(hX2  A new mode, streaming mode, in which a subset of the normal FPSIMD and SVE
features are available.  When supported EL0 software may enter and leave
streaming mode at any time.

For best system performance it is strongly encouraged for software to enable
streaming mode only when it is actively being used.
”h]”(h¸)”}”(hŒ¯A new mode, streaming mode, in which a subset of the normal FPSIMD and SVE
features are available.  When supported EL0 software may enter and leave
streaming mode at any time.”h]”hŒ¯A new mode, streaming mode, in which a subset of the normal FPSIMD and SVE
features are available.  When supported EL0 software may enter and leave
streaming mode at any time.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MŸhjŒ  ubh¸)”}”(hŒ€For best system performance it is strongly encouraged for software to enable
streaming mode only when it is actively being used.”h]”hŒ€For best system performance it is strongly encouraged for software to enable
streaming mode only when it is actively being used.”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M£hjŒ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhj‰  hžhhŸh¶h Nubhú)”}”(hX‰  A new vector length controlling the size of ZA and the Z registers when in
streaming mode, separately to the vector length used for SVE when not in
streaming mode.  There is no requirement that either the currently selected
vector length or the set of vector lengths supported for the two modes in
a given system have any relationship.  The streaming mode vector length
is referred to as SVL.
”h]”h¸)”}”(hXˆ  A new vector length controlling the size of ZA and the Z registers when in
streaming mode, separately to the vector length used for SVE when not in
streaming mode.  There is no requirement that either the currently selected
vector length or the set of vector lengths supported for the two modes in
a given system have any relationship.  The streaming mode vector length
is referred to as SVL.”h]”hXˆ  A new vector length controlling the size of ZA and the Z registers when in
streaming mode, separately to the vector length used for SVE when not in
streaming mode.  There is no requirement that either the currently selected
vector length or the set of vector lengths supported for the two modes in
a given system have any relationship.  The streaming mode vector length
is referred to as SVL.”…””}”(hj¶  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¦hj²  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj‰  hžhhŸh¶h Nubhú)”}”(hXM  A new ZA matrix register.  This is a square matrix of SVLxSVL bits.  Most
operations on ZA require that streaming mode be enabled but ZA can be
enabled without streaming mode in order to load, save and retain data.

For best system performance it is strongly encouraged for software to enable
ZA only when it is actively being used.
”h]”(h¸)”}”(hŒÖA new ZA matrix register.  This is a square matrix of SVLxSVL bits.  Most
operations on ZA require that streaming mode be enabled but ZA can be
enabled without streaming mode in order to load, save and retain data.”h]”hŒÖA new ZA matrix register.  This is a square matrix of SVLxSVL bits.  Most
operations on ZA require that streaming mode be enabled but ZA can be
enabled without streaming mode in order to load, save and retain data.”…””}”(hjÎ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M­hjÊ  ubh¸)”}”(hŒtFor best system performance it is strongly encouraged for software to enable
ZA only when it is actively being used.”h]”hŒtFor best system performance it is strongly encouraged for software to enable
ZA only when it is actively being used.”…””}”(hjÜ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M±hjÊ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhj‰  hžhhŸh¶h Nubhú)”}”(hŒŽA new ZT0 register is introduced when SME2 is present. This is a 512 bit
register which is accessible when PSTATE.ZA is set, as ZA itself is.
”h]”h¸)”}”(hŒA new ZT0 register is introduced when SME2 is present. This is a 512 bit
register which is accessible when PSTATE.ZA is set, as ZA itself is.”h]”hŒA new ZT0 register is introduced when SME2 is present. This is a 512 bit
register which is accessible when PSTATE.ZA is set, as ZA itself is.”…””}”(hjô  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M´hjð  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj‰  hžhhŸh¶h Nubhú)”}”(hXR  Two new 1 bit fields in PSTATE which may be controlled via the SMSTART and
SMSTOP instructions or by access to the SVCR system register:

* PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
  data while if it is 0 then ZA can not be accessed.  When PSTATE.ZA is
  changed from 0 to 1 all bits in ZA are cleared.

* PSTATE.SM, if this is 1 then the PE is in streaming mode.  When the value
  of PSTATE.SM is changed then it is implementation defined if the subset
  of the floating point register bits valid in both modes may be retained.
  Any other bits will be cleared.

”h]”(h¸)”}”(hŒˆTwo new 1 bit fields in PSTATE which may be controlled via the SMSTART and
SMSTOP instructions or by access to the SVCR system register:”h]”hŒˆTwo new 1 bit fields in PSTATE which may be controlled via the SMSTART and
SMSTOP instructions or by access to the SVCR system register:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M·hj  ubhõ)”}”(hhh]”(hú)”}”(hŒ½PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
data while if it is 0 then ZA can not be accessed.  When PSTATE.ZA is
changed from 0 to 1 all bits in ZA are cleared.
”h]”h¸)”}”(hŒ¼PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
data while if it is 0 then ZA can not be accessed.  When PSTATE.ZA is
changed from 0 to 1 all bits in ZA are cleared.”h]”hŒ¼PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
data while if it is 0 then ZA can not be accessed.  When PSTATE.ZA is
changed from 0 to 1 all bits in ZA are cleared.”…””}”(hj!  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mºhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj  ubhú)”}”(hŒüPSTATE.SM, if this is 1 then the PE is in streaming mode.  When the value
of PSTATE.SM is changed then it is implementation defined if the subset
of the floating point register bits valid in both modes may be retained.
Any other bits will be cleared.

”h]”h¸)”}”(hŒúPSTATE.SM, if this is 1 then the PE is in streaming mode.  When the value
of PSTATE.SM is changed then it is implementation defined if the subset
of the floating point register bits valid in both modes may be retained.
Any other bits will be cleared.”h]”hŒúPSTATE.SM, if this is 1 then the PE is in streaming mode.  When the value
of PSTATE.SM is changed then it is implementation defined if the subset
of the floating point register bits valid in both modes may be retained.
Any other bits will be cleared.”…””}”(hj9  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¾hj5  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hùhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h Mºhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hùhj‰  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hôhŸh¶h MŸhjj  hžhubh¢)”}”(hhh]”(h§)”}”(hŒ
References”h]”hŒ
References”…””}”(hjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj_  hžhhŸh¶h MÅubj~  )”}”(hhh]”(jƒ  )”}”(hŒR[1] arch/arm64/include/uapi/asm/sigcontext.h
AArch64 Linux signal ABI definitions
”h]”(j‰  )”}”(hŒ,[1] arch/arm64/include/uapi/asm/sigcontext.h”h]”hŒ,[1] arch/arm64/include/uapi/asm/sigcontext.h”…””}”(hjw  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  hŸh¶h MÈhjs  ubj™  )”}”(hhh]”h¸)”}”(hŒ$AArch64 Linux signal ABI definitions”h]”hŒ$AArch64 Linux signal ABI definitions”…””}”(hjˆ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÈhj…  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j˜  hjs  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j‚  hŸh¶h MÈhjp  ubjƒ  )”}”(hŒN[2] arch/arm64/include/uapi/asm/ptrace.h
AArch64 Linux ptrace ABI definitions
”h]”(j‰  )”}”(hŒ([2] arch/arm64/include/uapi/asm/ptrace.h”h]”hŒ([2] arch/arm64/include/uapi/asm/ptrace.h”…””}”(hj¦  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  hŸh¶h MËhj¢  ubj™  )”}”(hhh]”h¸)”}”(hŒ$AArch64 Linux ptrace ABI definitions”h]”hŒ$AArch64 Linux ptrace ABI definitions”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MËhj´  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j˜  hj¢  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j‚  hŸh¶h MËhjp  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j}  hj_  hžhhŸh¶h Nubh¸)”}”(hŒ6[3] Documentation/arch/arm64/cpu-feature-registers.rst”h]”hŒ6[3] Documentation/arch/arm64/cpu-feature-registers.rst”…””}”(hj×  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÍhj_  hžhubeh}”(h]”Œ
references”ah ]”h"]”Œ
references”ah$]”h&]”uh1h¡hjj  hžhhŸh¶h MÅubeh}”(h]”Œa-1-registers”ah ]”h"]”Œa.1. registers”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M›ubeh}”(h]”Œ3scalable-matrix-extension-support-for-aarch64-linux”ah ]”h"]”Œ3scalable matrix extension support for aarch64 linux”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j   Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jú  j÷  j$  j!  jK  jH  jå  jâ  j÷  jô  j‡  j„  j9  j6  jª	  j§	  j,
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  j\  j-  jï  jj  jç  j_  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
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