Ҁsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/arch/arm64/perfmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/arch/arm64/perfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/arch/arm64/perfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/arch/arm64/perfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/arch/arm64/perfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/arch/arm64/perfmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/arch/arm64/perf.rsthKubhtarget)}(h.. _perf_index:h]h}(h]h ]h"]h$]h&]refid perf-indexuh1hhKhhhhhhubhsection)}(hhh](htitle)}(hPerfh]hPerf}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hPerf Event Attributesh]hPerf Event Attributes}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh field_list)}(hhh](hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(h%Andrew Murray h]h paragraph)}(hjh](hAndrew Murray <}(hj hhhNhNubh reference)}(handrew.murray@arm.comh]handrew.murray@arm.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:andrew.murray@arm.comuh1jhj ubh>}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhhubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hDateh]hDate}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhKubj)}(h 2019-03-06 h]j )}(h 2019-03-06h]h 2019-03-06}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK hjJubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h exclude_userh]h exclude_user}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhhhhhKubj )}(h"This attribute excludes userspace.h]h"This attribute excludes userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjnhhubj )}(hFUserspace always runs at EL0 and thus this attribute will exclude EL0.h]hFUserspace always runs at EL0 and thus this attribute will exclude EL0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjnhhubeh}(h] exclude-userah ]h"] exclude_userah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hexclude_kernelh]hexclude_kernel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(h#This attribute excludes the kernel.h]h#This attribute excludes the kernel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hQThe kernel runs at EL2 with VHE and EL1 without. Guest kernels always run at EL1.h]hQThe kernel runs at EL2 with VHE and EL1 without. Guest kernels always run at EL1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hRFor the host this attribute will exclude EL1 and additionally EL2 on a VHE system.h]hRFor the host this attribute will exclude EL1 and additionally EL2 on a VHE system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hdFor the guest this attribute will exclude EL1. Please note that EL2 is never counted within a guest.h]hdFor the guest this attribute will exclude EL1. Please note that EL2 is never counted within a guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK"hjhhubeh}(h]exclude-kernelah ]h"]exclude_kernelah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h exclude_hvh]h exclude_hv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK'ubj )}(h'This attribute excludes the hypervisor.h]h'This attribute excludes the hypervisor.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK)hjhhubj )}(h]For a VHE host this attribute is ignored as we consider the host kernel to be the hypervisor.h]h]For a VHE host this attribute is ignored as we consider the host kernel to be the hypervisor.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK+hjhhubj )}(hFor a non-VHE host this attribute will exclude EL2 as we consider the hypervisor to be any code that runs at EL2 which is predominantly used for guest/host transitions.h]hFor a non-VHE host this attribute will exclude EL2 as we consider the hypervisor to be any code that runs at EL2 which is predominantly used for guest/host transitions.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK.hjhhubj )}(haFor the guest this attribute has no effect. Please note that EL2 is never counted within a guest.h]haFor the guest this attribute has no effect. Please note that EL2 is never counted within a guest.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK2hjhhubeh}(h] exclude-hvah ]h"] exclude_hvah$]h&]uh1hhhhhhhhK'ubh)}(hhh](h)}(hexclude_host / exclude_guesth]hexclude_host / exclude_guest}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhhhhhK7ubj )}(h>These attributes exclude the KVM host and guest, respectively.h]h>These attributes exclude the KVM host and guest, respectively.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK9hjEhhubj )}(hiThe KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE kernel or non-VHE hypervisor).h]hiThe KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE kernel or non-VHE hypervisor).}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK;hjEhhubj )}(h:The KVM guest may run at EL0 (userspace) and EL1 (kernel).h]h:The KVM guest may run at EL0 (userspace) and EL1 (kernel).}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK>hjEhhubj )}(hXDue to the overlapping exception levels between host and guests we cannot exclusively rely on the PMU's hardware exception filtering - therefore we must enable/disable counting on the entry and exit to the guest. This is performed differently on VHE and non-VHE systems.h]hXDue to the overlapping exception levels between host and guests we cannot exclusively rely on the PMU’s hardware exception filtering - therefore we must enable/disable counting on the entry and exit to the guest. This is performed differently on VHE and non-VHE systems.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK@hjEhhubj )}(hFor non-VHE systems we exclude EL2 for exclude_host - upon entering and exiting the guest we disable/enable the event as appropriate based on the exclude_host and exclude_guest attributes.h]hFor non-VHE systems we exclude EL2 for exclude_host - upon entering and exiting the guest we disable/enable the event as appropriate based on the exclude_host and exclude_guest attributes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKEhjEhhubj )}(hFor VHE systems we exclude EL1 for exclude_guest and exclude both EL0,EL2 for exclude_host. Upon entering and exiting the guest we modify the event to include/exclude EL0 as appropriate based on the exclude_host and exclude_guest attributes.h]hFor VHE systems we exclude EL1 for exclude_guest and exclude both EL0,EL2 for exclude_host. Upon entering and exiting the guest we modify the event to include/exclude EL0 as appropriate based on the exclude_host and exclude_guest attributes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKIhjEhhubj )}(hThe statements above also apply when these attributes are used within a non-VHE guest however please note that EL2 is never counted within a guest.h]hThe statements above also apply when these attributes are used within a non-VHE guest however please note that EL2 is never counted within a guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKNhjEhhubeh}(h]exclude-host-exclude-guestah ]h"]exclude_host / exclude_guestah$]h&]uh1hhhhhhhhK7ubh)}(hhh](h)}(hAccuracyh]hAccuracy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKSubj )}(hXOn non-VHE hosts we enable/disable counters on the entry/exit of host/guest transition at EL2 - however there is a period of time between enabling/disabling the counters and entering/exiting the guest. We are able to eliminate counters counting host events on the boundaries of guest entry/exit when counting guest events by filtering out EL2 for exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured.h]hXOn non-VHE hosts we enable/disable counters on the entry/exit of host/guest transition at EL2 - however there is a period of time between enabling/disabling the counters and entering/exiting the guest. We are able to eliminate counters counting host events on the boundaries of guest entry/exit when counting guest events by filtering out EL2 for exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKUhjhhubj )}(h-On VHE systems there are no blackout windows.h]h-On VHE systems there are no blackout windows.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK]hjhhubeh}(h]accuracyah ]h"]accuracyah$]h&]uh1hhhhhhhhKSubeh}(h]perf-event-attributesah ]h"]perf event attributesah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h*Perf Userspace PMU Hardware Counter Accessh]h*Perf Userspace PMU Hardware Counter Access}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK`ubh)}(hhh](h)}(hOverviewh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKcubj )}(hXThe perf userspace tool relies on the PMU to monitor events. It offers an abstraction layer over the hardware counters since the underlying implementation is cpu-dependent. Arm64 allows userspace tools to have access to the registers storing the hardware counters' values directly.h]hXThe perf userspace tool relies on the PMU to monitor events. It offers an abstraction layer over the hardware counters since the underlying implementation is cpu-dependent. Arm64 allows userspace tools to have access to the registers storing the hardware counters’ values directly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKdhjhhubj )}(hThis targets specifically self-monitoring tasks in order to reduce the overhead by directly accessing the registers without having to go through the kernel.h]hThis targets specifically self-monitoring tasks in order to reduce the overhead by directly accessing the registers without having to go through the kernel.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKjhjhhubeh}(h]overviewah ]h"]h$]overviewah&]uh1hhjhhhhhKc referencedKubh)}(hhh](h)}(hHow-toh]hHow-to}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhKnubj )}(hThe focus is set on the armv8 PMUv3 which makes sure that the access to the pmu registers is enabled and that the userspace has access to the relevant information in order to use them.h]hThe focus is set on the armv8 PMUv3 which makes sure that the access to the pmu registers is enabled and that the userspace has access to the relevant information in order to use them.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKohjDhhubj )}(hrIn order to have access to the hardware counters, the global sysctl kernel/perf_user_access must first be enabled:h]hrIn order to have access to the hardware counters, the global sysctl kernel/perf_user_access must first be enabled:}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKshjDhhubh literal_block)}(h*echo 1 > /proc/sys/kernel/perf_user_accessh]h*echo 1 > /proc/sys/kernel/perf_user_access}hjssbah}(h]h ]h"]h$]h&]hhforcelanguageshhighlight_args}uh1jqhhhKvhjDhhubj )}(hX{It is necessary to open the event using the perf tool interface with config1:1 attr bit set: the sys_perf_event_open syscall returns a fd which can subsequently be used with the mmap syscall in order to retrieve a page of memory containing information about the event. The PMU driver uses this page to expose to the user the hardware counter's index and other necessary data. Using this index enables the user to access the PMU registers using the `mrs` instruction. Access to the PMU registers is only valid while the sequence lock is unchanged. In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is changed.h](hXIt is necessary to open the event using the perf tool interface with config1:1 attr bit set: the sys_perf_event_open syscall returns a fd which can subsequently be used with the mmap syscall in order to retrieve a page of memory containing information about the event. The PMU driver uses this page to expose to the user the hardware counter’s index and other necessary data. Using this index enables the user to access the PMU registers using the }(hjhhhNhNubhtitle_reference)}(h`mrs`h]hmrs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh instruction. Access to the PMU registers is only valid while the sequence lock is unchanged. In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is changed.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKzhjDhhubj )}(hThe userspace access is supported in libperf using the perf_evsel__mmap() and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for an example.h](hpThe userspace access is supported in libperf using the perf_evsel__mmap() and perf_evsel__read() functions. See }(hjhhhNhNubj)}(h$`tools/lib/perf/tests/test-evsel.c`_h]h!tools/lib/perf/tests/test-evsel.c}(hjhhhNhNubah}(h]h ]h"]h$]h&]name!tools/lib/perf/tests/test-evsel.crefuriihttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.cuh1jhjresolvedKubh for an example.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjDhhubeh}(h]how-toah ]h"]h$]how-toah&]uh1hhjhhhhhKnjCKubh)}(hhh](h)}(hAbout heterogeneous systemsh]hAbout heterogeneous systems}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(hX'On heterogeneous systems such as big.LITTLE, userspace PMU counter access can only be enabled when the tasks are pinned to a homogeneous subset of cores and the corresponding PMU instance is opened by specifying the 'type' attribute. The use of generic event types is not supported in this case.h]hX+On heterogeneous systems such as big.LITTLE, userspace PMU counter access can only be enabled when the tasks are pinned to a homogeneous subset of cores and the corresponding PMU instance is opened by specifying the ‘type’ attribute. The use of generic event types is not supported in this case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hHave a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It can be run using the perf tool to check that the access to the registers works correctly from userspace:h](hHave a look at }(hjhhhNhNubj)}(h,`tools/perf/arch/arm64/tests/user-events.c`_h]h)tools/perf/arch/arm64/tests/user-events.c}(hjhhhNhNubah}(h]h ]h"]h$]h&]name)tools/perf/arch/arm64/tests/user-events.cjqhttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.cuh1jhjjKubh| for an example. It can be run using the perf tool to check that the access to the registers works correctly from userspace:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubjr)}(hperf test -v userh]hperf test -v user}hjsbah}(h]h ]h"]h$]h&]hhjjshj}uh1jqhhhKhjhhubeh}(h]about-heterogeneous-systemsah ]h"]about heterogeneous systemsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h&About chained events and counter sizesh]h&About chained events and counter sizes}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhKubj )}(hX[The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1) counter along with userspace access. The sys_perf_event_open syscall will fail if a 64-bit counter is requested and the hardware doesn't support 64-bit counters. Chained events are not supported in conjunction with userspace counter access. If a 32-bit counter is requested on hardware with 64-bit counters, then userspace must treat the upper 32-bits read from the counter as UNKNOWN. The 'pmc_width' field in the user page will indicate the valid width of the counter and should be used to mask the upper bits as needed.h]hXaThe user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1) counter along with userspace access. The sys_perf_event_open syscall will fail if a 64-bit counter is requested and the hardware doesn’t support 64-bit counters. Chained events are not supported in conjunction with userspace counter access. If a 32-bit counter is requested on hardware with 64-bit counters, then userspace must treat the upper 32-bits read from the counter as UNKNOWN. The ‘pmc_width’ field in the user page will indicate the valid width of the counter and should be used to mask the upper bits as needed.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj/hhubh)}(hLinksh]hLinks}hjNsbah}(h]h ]h"]h$]h&]hhuh1hhj/hhhhhKubh)}(h.. _tools/perf/arch/arm64/tests/user-events.c: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.ch]h}(h])tools-perf-arch-arm64-tests-user-events-cah ]h"])tools/perf/arch/arm64/tests/user-events.cah$]h&]jj uh1hhKhj/hhhhjCKubh)}(h.. _tools/lib/perf/tests/test-evsel.c: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.ch]h}(h]!tools-lib-perf-tests-test-evsel-cah ]h"]!tools/lib/perf/tests/test-evsel.cah$]h&]jjuh1hhKhj/hhhhjCKubeh}(h]&about-chained-events-and-counter-sizesah ]h"]&about chained events and counter sizesah$]h&]uh1hhjhhhhhKubeh}(h]*perf-userspace-pmu-hardware-counter-accessah ]h"]*perf userspace pmu hardware counter accessah$]h&]uh1hhhhhhhhK`ubh)}(hhh](h)}(hEvent Counting Thresholdh]hEvent Counting Threshold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(hX}FEAT_PMUv3_TH (Armv8.8) permits a PMU counter to increment only on events whose count meets a specified threshold condition. For example if threshold_compare is set to 2 ('Greater than or equal'), and the threshold is set to 2, then the PMU counter will now only increment by when an event would have previously incremented the PMU counter by 2 or more on a single processor cycle.h]hXFEAT_PMUv3_TH (Armv8.8) permits a PMU counter to increment only on events whose count meets a specified threshold condition. For example if threshold_compare is set to 2 (‘Greater than or equal’), and the threshold is set to 2, then the PMU counter will now only increment by when an event would have previously incremented the PMU counter by 2 or more on a single processor cycle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hTo increment by 1 after passing the threshold condition instead of the number of events on that cycle, add the 'threshold_count' option to the commandline.h]hTo increment by 1 after passing the threshold condition instead of the number of events on that cycle, add the ‘threshold_count’ option to the commandline.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]id1ah ]h"]h$]jAah&]uh1hhjhhhhhKjCKubh)}(hhh](h)}(hHow-toh]hHow-to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(h5These are the parameters for controlling the feature:h]h5These are the parameters for controlling the feature:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK2uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]jK2uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]j )}(h Parameterh]h Parameter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j )}(h Descriptionh]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh](j )}(hhh](j)}(hhh]j )}(h thresholdh]h threshold}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjUubah}(h]h ]h"]h$]h&]uh1jhjRubj)}(hhh]j )}(hzValue to threshold the event by. A value of 0 means that thresholding is disabled and the other parameters have no effect.h]hzValue to threshold the event by. A value of 0 means that thresholding is disabled and the other parameters have no effect.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjlubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j hjOubj )}(hhh](j)}(hhh]j )}(hthreshold_compareh]hthreshold_compare}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h line_block)}(hhh](hh)}(h@Comparison function to use, with the following values supported:h]h@Comparison function to use, with the following values supported:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjhhhKubj)}(hhh]h}(h]h ]h"]h$]h&]uh1hhjjKhhhKubj)}(h 0: Not-equalh]h 0: Not-equal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubj)}(h 1: Equalsh]h 1: Equals}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubj)}(h2: Greater-than-or-equalh]h2: Greater-than-or-equal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubj)}(h 3: Less-thanh]h 3: Less-than}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjOubj )}(hhh](j)}(hhh]j )}(hthreshold_counth]hthreshold_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j )}(hqIf this is set, count by 1 after passing the threshold condition instead of the value of the event on this cycle.h]hqIf this is set, count by 1 after passing the threshold condition instead of the value of the event on this cycle.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j hjOubeh}(h]h ]h"]h$]h&]uh1jMhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj )}(hcThe threshold, threshold_compare and threshold_count values can be provided per event, for example:h]hcThe threshold, threshold_compare and threshold_count values can be provided per event, for example:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubjr)}(hperf stat -e stall_slot/threshold=2,threshold_compare=2/ \ -e dtlb_walk/threshold=10,threshold_compare=3,threshold_count/h]hperf stat -e stall_slot/threshold=2,threshold_compare=2/ \ -e dtlb_walk/threshold=10,threshold_compare=3,threshold_count/}hjfsbah}(h]h ]h"]h$]h&]hhjjshj}uh1jqhhhKhjhhubj )}(hIn this example the stall_slot event will count by 2 or more on every cycle where 2 or more stalls happen. And dtlb_walk will count by 1 on every cycle where the number of dtlb walks were less than 10.h]hIn this example the stall_slot event will count by 2 or more on every cycle where 2 or more stalls happen. And dtlb_walk will count by 1 on every cycle where the number of dtlb walks were less than 10.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hYThe maximum supported threshold value can be read from the caps of each PMU, for example:h]hYThe maximum supported threshold value can be read from the caps of each PMU, for example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubjr)}(hLcat /sys/bus/event_source/devices/armv8_pmuv3/caps/threshold_max 0x000000ffh]hLcat /sys/bus/event_source/devices/armv8_pmuv3/caps/threshold_max 0x000000ff}hjsbah}(h]h ]h"]h$]h&]hhjjshj}uh1jqhhhKhjhhubj )}(hIf a value higher than this is given, then opening the event will result in an error. The highest possible maximum is 4095, as the config field for threshold is limited to 12 bits, and the Perf tool will refuse to parse higher values.h]hIf a value higher than this is given, then opening the event will result in an error. The highest possible maximum is 4095, as the config field for threshold is limited to 12 bits, and the Perf tool will refuse to parse higher values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj )}(hIf the PMU doesn't support FEAT_PMUv3_TH, then threshold_max will read 0, and attempting to set a threshold value will also result in an error. threshold_max will also read as 0 on aarch32 guests, even if the host is running on hardware with the feature.h]hXIf the PMU doesn’t support FEAT_PMUv3_TH, then threshold_max will read 0, and attempting to set a threshold value will also result in an error. threshold_max will also read as 0 on aarch32 guests, even if the host is running on hardware with the feature.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]id2ah ]h"]h$]jah&]uh1hhjhhhhhKjCKubeh}(h]event-counting-thresholdah ]h"]event counting thresholdah$]h&]uh1hhhhhhhhKubeh}(h](perfheh ]h"](perf perf_indexeh$]h&]uh1hhhhhhhhKexpect_referenced_by_name}jhsexpect_referenced_by_id}hhsubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}(!tools/lib/perf/tests/test-evsel.c]ja)tools/perf/arch/arm64/tests/user-events.c]jaurefids}h]hasnameids}(jhjjjjjjjjjBj?jjjjjj~overviewNhow-toNj,j)jyjvjejbjqjnjju nametypes}(jjjjjjBjjjjEjFj,jyjejqjuh}(hhjhjhjjnjjj?jjjEjjj~jj=jjjDj)jjvj/jbj\jnjhjjjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}j KsRparse_messages](hsystem_message)}(hhh]j )}(h+Duplicate implicit target name: "overview".h]h/Duplicate implicit target name: “overview”.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]jalevelKtypeINFOsourcehlineKuh1jehjhhhhhKubjf)}(hhh]j )}(h)Duplicate implicit target name: "how-to".h]h-Duplicate implicit target name: “how-to”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jalevelKtypejsourcehlineKuh1jehjhhhhhKubetransform_messages]jf)}(hhh]j )}(hhh]h0Hyperlink target "perf-index" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]levelKtypejsourcehlineKuh1jeuba transformerN include_log] decorationNhhub.