sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget4/translations/zh_CN/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/zh_TW/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/it_IT/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/ja_JP/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/ko_KR/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/pt_BR/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/sp_SP/arch/arm64/cpu-feature-registersmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hARM64 CPU Feature Registersh]hARM64 CPU Feature Registers}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhN/var/lib/git/docbuild/linux/Documentation/arch/arm64/cpu-feature-registers.rsthKubh paragraph)}(h1Author: Suzuki K Poulose h](hAuthor: Suzuki K Poulose <}(hhhhhNhNubh reference)}(hsuzuki.poulose@arm.comh]hsuzuki.poulose@arm.com}(hhhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:suzuki.poulose@arm.comuh1hhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThis file describes the ABI for exporting the AArch64 CPU ID/feature registers to userspace. The availability of this ABI is advertised via the HWCAP_CPUID in HWCAPs.h]hThis file describes the ABI for exporting the AArch64 CPU ID/feature registers to userspace. The availability of this ABI is advertised via the HWCAP_CPUID in HWCAPs.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h 1. Motivationh]h 1. Motivation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hXThe ARM architecture defines a set of feature registers, which describe the capabilities of the CPU/system. Access to these system registers is restricted from EL0 and there is no reliable way for an application to extract this information to make better decisions at runtime. There is limited information available to the application via HWCAPs, however there are some issues with their usage.h]hXThe ARM architecture defines a set of feature registers, which describe the capabilities of the CPU/system. Access to these system registers is restricted from EL0 and there is no reliable way for an application to extract this information to make better decisions at runtime. There is limited information available to the application via HWCAPs, however there are some issues with their usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hX{a) Any change to the HWCAPs requires an update to userspace (e.g libc) to detect the new changes, which can take a long time to appear in distributions. Exposing the registers allows applications to get the information without requiring updates to the toolchains. b) Access to HWCAPs is sometimes limited (e.g prior to libc, or when ld is initialised at startup time). c) HWCAPs cannot represent non-boolean information effectively. The architecture defines a canonical format for representing features in the ID registers; this is well defined and is capable of representing all valid architecture variations. h]henumerated_list)}(hhh](h list_item)}(hXAny change to the HWCAPs requires an update to userspace (e.g libc) to detect the new changes, which can take a long time to appear in distributions. Exposing the registers allows applications to get the information without requiring updates to the toolchains. h]h)}(hXAny change to the HWCAPs requires an update to userspace (e.g libc) to detect the new changes, which can take a long time to appear in distributions. Exposing the registers allows applications to get the information without requiring updates to the toolchains.h]hXAny change to the HWCAPs requires an update to userspace (e.g libc) to detect the new changes, which can take a long time to appear in distributions. Exposing the registers allows applications to get the information without requiring updates to the toolchains.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ubah}(h]h ]h"]h$]h&]uh1j)hj&ubj*)}(hfAccess to HWCAPs is sometimes limited (e.g prior to libc, or when ld is initialised at startup time). h]h)}(heAccess to HWCAPs is sometimes limited (e.g prior to libc, or when ld is initialised at startup time).h]heAccess to HWCAPs is sometimes limited (e.g prior to libc, or when ld is initialised at startup time).}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubah}(h]h ]h"]h$]h&]uh1j)hj&ubj*)}(hHWCAPs cannot represent non-boolean information effectively. The architecture defines a canonical format for representing features in the ID registers; this is well defined and is capable of representing all valid architecture variations. h]h)}(hHWCAPs cannot represent non-boolean information effectively. The architecture defines a canonical format for representing features in the ID registers; this is well defined and is capable of representing all valid architecture variations.h]hHWCAPs cannot represent non-boolean information effectively. The architecture defines a canonical format for representing features in the ID registers; this is well defined and is capable of representing all valid architecture variations.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj[ubah}(h]h ]h"]h$]h&]uh1j)hj&ubeh}(h]h ]h"]h$]h&]enumtype loweralphaprefixhsuffix)uh1j$hj ubah}(h]h ]h"]h$]h&]uh1jhhhKhhhhubeh}(h] motivationah ]h"] 1. motivationah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h2. Requirementsh]h2. Requirements}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK%ubj)}(hXa) Safety: Applications should be able to use the information provided by the infrastructure to run safely across the system. This has greater implications on a system with heterogeneous CPUs. The infrastructure exports a value that is safe across all the available CPU on the system. e.g, If at least one CPU doesn't implement CRC32 instructions, while others do, we should report that the CRC32 is not implemented. Otherwise an application could crash when scheduled on the CPU which doesn't support CRC32. b) Security: Applications should only be able to receive information that is relevant to the normal operation in userspace. Hence, some of the fields are masked out(i.e, made invisible) and their values are set to indicate the feature is 'not supported'. See Section 4 for the list of visible features. Also, the kernel may manipulate the fields based on what it supports. e.g, If FP is not supported by the kernel, the values could indicate that the FP is not available (even when the CPU provides it). c) Implementation Defined Features The infrastructure doesn't expose any register which is IMPLEMENTATION DEFINED as per ARMv8-A Architecture. d) CPU Identification: MIDR_EL1 is exposed to help identify the processor. On a heterogeneous system, this could be racy (just like getcpu()). The process could be migrated to another CPU by the time it uses the register value, unless the CPU affinity is set. Hence, there is no guarantee that the value reflects the processor that it is currently executing on. REVIDR and AIDR are not exposed due to this constraint, as these registers only make sense in conjunction with the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed via sysfs at:: /sys/devices/system/cpu/cpu$ID/regs/identification/ \- midr_el1 \- revidr_el1 \- aidr_el1 h]j%)}(hhh](j*)}(hXSafety: Applications should be able to use the information provided by the infrastructure to run safely across the system. This has greater implications on a system with heterogeneous CPUs. The infrastructure exports a value that is safe across all the available CPU on the system. e.g, If at least one CPU doesn't implement CRC32 instructions, while others do, we should report that the CRC32 is not implemented. Otherwise an application could crash when scheduled on the CPU which doesn't support CRC32. h](h)}(hSafety:h]hSafety:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubh)}(hXApplications should be able to use the information provided by the infrastructure to run safely across the system. This has greater implications on a system with heterogeneous CPUs. The infrastructure exports a value that is safe across all the available CPU on the system.h]hXApplications should be able to use the information provided by the infrastructure to run safely across the system. This has greater implications on a system with heterogeneous CPUs. The infrastructure exports a value that is safe across all the available CPU on the system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubh)}(he.g, If at least one CPU doesn't implement CRC32 instructions, while others do, we should report that the CRC32 is not implemented. Otherwise an application could crash when scheduled on the CPU which doesn't support CRC32.h]he.g, If at least one CPU doesn’t implement CRC32 instructions, while others do, we should report that the CRC32 is not implemented. Otherwise an application could crash when scheduled on the CPU which doesn’t support CRC32.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hXSecurity: Applications should only be able to receive information that is relevant to the normal operation in userspace. Hence, some of the fields are masked out(i.e, made invisible) and their values are set to indicate the feature is 'not supported'. See Section 4 for the list of visible features. Also, the kernel may manipulate the fields based on what it supports. e.g, If FP is not supported by the kernel, the values could indicate that the FP is not available (even when the CPU provides it). h](h)}(h Security:h]h Security:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubh)}(hXApplications should only be able to receive information that is relevant to the normal operation in userspace. Hence, some of the fields are masked out(i.e, made invisible) and their values are set to indicate the feature is 'not supported'. See Section 4 for the list of visible features. Also, the kernel may manipulate the fields based on what it supports. e.g, If FP is not supported by the kernel, the values could indicate that the FP is not available (even when the CPU provides it).h]hXApplications should only be able to receive information that is relevant to the normal operation in userspace. Hence, some of the fields are masked out(i.e, made invisible) and their values are set to indicate the feature is ‘not supported’. See Section 4 for the list of visible features. Also, the kernel may manipulate the fields based on what it supports. e.g, If FP is not supported by the kernel, the values could indicate that the FP is not available (even when the CPU provides it).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hImplementation Defined Features The infrastructure doesn't expose any register which is IMPLEMENTATION DEFINED as per ARMv8-A Architecture. h](h)}(hImplementation Defined Featuresh]hImplementation Defined Features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubh)}(hkThe infrastructure doesn't expose any register which is IMPLEMENTATION DEFINED as per ARMv8-A Architecture.h]hmThe infrastructure doesn’t expose any register which is IMPLEMENTATION DEFINED as per ARMv8-A Architecture.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hX!CPU Identification: MIDR_EL1 is exposed to help identify the processor. On a heterogeneous system, this could be racy (just like getcpu()). The process could be migrated to another CPU by the time it uses the register value, unless the CPU affinity is set. Hence, there is no guarantee that the value reflects the processor that it is currently executing on. REVIDR and AIDR are not exposed due to this constraint, as these registers only make sense in conjunction with the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed via sysfs at:: /sys/devices/system/cpu/cpu$ID/regs/identification/ \- midr_el1 \- revidr_el1 \- aidr_el1 h](h)}(hCPU Identification:h]hCPU Identification:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhj$ubh)}(hXMIDR_EL1 is exposed to help identify the processor. On a heterogeneous system, this could be racy (just like getcpu()). The process could be migrated to another CPU by the time it uses the register value, unless the CPU affinity is set. Hence, there is no guarantee that the value reflects the processor that it is currently executing on. REVIDR and AIDR are not exposed due to this constraint, as these registers only make sense in conjunction with the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed via sysfs at::h]hXMIDR_EL1 is exposed to help identify the processor. On a heterogeneous system, this could be racy (just like getcpu()). The process could be migrated to another CPU by the time it uses the register value, unless the CPU affinity is set. Hence, there is no guarantee that the value reflects the processor that it is currently executing on. REVIDR and AIDR are not exposed due to this constraint, as these registers only make sense in conjunction with the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed via sysfs at:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhj$ubh literal_block)}(h/sys/devices/system/cpu/cpu$ID/regs/identification/ \- midr_el1 \- revidr_el1 \- aidr_el1h]h/sys/devices/system/cpu/cpu$ID/regs/identification/ \- midr_el1 \- revidr_el1 \- aidr_el1}hjFsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jDhhhKPhj$ubeh}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]jyjzj{hj|j}uh1j$hjubah}(h]h ]h"]h$]h&]uh1jhhhK'hjhhubeh}(h] requirementsah ]h"]2. requirementsah$]h&]uh1hhhhhhhhK%ubh)}(hhh](h)}(h3. Implementationh]h3. Implementation}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphhhhhKVubh)}(hX[The infrastructure is built on the emulation of the 'MRS' instruction. Accessing a restricted system register from an application generates an exception and ends up in SIGILL being delivered to the process. The infrastructure hooks into the exception handler and emulates the operation if the source belongs to the supported system register space.h]hX_The infrastructure is built on the emulation of the ‘MRS’ instruction. Accessing a restricted system register from an application generates an exception and ends up in SIGILL being delivered to the process. The infrastructure hooks into the exception handler and emulates the operation if the source belongs to the supported system register space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjphhubh)}(hFThe infrastructure emulates only the following system register space::h]hEThe infrastructure emulates only the following system register space:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjphhubjE)}(h&Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7h]h&Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7}hjsbah}(h]h ]h"]h$]h&]jTjUuh1jDhhhK`hjphhubh)}(h(See Table C5-6 'System instruction encodings for non-Debug System register accesses' in ARMv8 ARM DDI 0487A.h, for the list of registers).h]h(See Table C5-6 ‘System instruction encodings for non-Debug System register accesses’ in ARMv8 ARM DDI 0487A.h, for the list of registers).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjphhubh)}(hLThe following rules are applied to the value returned by the infrastructure:h]hLThe following rules are applied to the value returned by the infrastructure:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjphhubj)}(hXa) The value of an 'IMPLEMENTATION DEFINED' field is set to 0. b) The value of a reserved field is populated with the reserved value as defined by the architecture. c) The value of a 'visible' field holds the system wide safe value for the particular feature (except for MIDR_EL1, see section 4). d) All other fields (i.e, invisible fields) are set to indicate the feature is missing (as defined by the architecture). h]j%)}(hhh](j*)}(h;The value of an 'IMPLEMENTATION DEFINED' field is set to 0.h]h)}(hjh]h?The value of an ‘IMPLEMENTATION DEFINED’ field is set to 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubah}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hbThe value of a reserved field is populated with the reserved value as defined by the architecture.h]h)}(hbThe value of a reserved field is populated with the reserved value as defined by the architecture.h]hbThe value of a reserved field is populated with the reserved value as defined by the architecture.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hThe value of a 'visible' field holds the system wide safe value for the particular feature (except for MIDR_EL1, see section 4).h]h)}(hThe value of a 'visible' field holds the system wide safe value for the particular feature (except for MIDR_EL1, see section 4).h]hThe value of a ‘visible’ field holds the system wide safe value for the particular feature (except for MIDR_EL1, see section 4).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hvAll other fields (i.e, invisible fields) are set to indicate the feature is missing (as defined by the architecture). h]h)}(huAll other fields (i.e, invisible fields) are set to indicate the feature is missing (as defined by the architecture).h]huAll other fields (i.e, invisible fields) are set to indicate the feature is missing (as defined by the architecture).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]jyjzj{hj|j}uh1j$hjubah}(h]h ]h"]h$]h&]uh1jhhhKihjphhubeh}(h]implementationah ]h"]3. implementationah$]h&]uh1hhhhhhhhKVubh)}(hhh](h)}(h*4. List of registers with visible featuresh]h*4. List of registers with visible features}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhKrubj)}(hX,1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | RNDR | [63-60] | y | +------------------------------+---------+---------+ | TS | [55-52] | y | +------------------------------+---------+---------+ | FHM | [51-48] | y | +------------------------------+---------+---------+ | DP | [47-44] | y | +------------------------------+---------+---------+ | SM4 | [43-40] | y | +------------------------------+---------+---------+ | SM3 | [39-36] | y | +------------------------------+---------+---------+ | SHA3 | [35-32] | y | +------------------------------+---------+---------+ | RDM | [31-28] | y | +------------------------------+---------+---------+ | ATOMICS | [23-20] | y | +------------------------------+---------+---------+ | CRC32 | [19-16] | y | +------------------------------+---------+---------+ | SHA2 | [15-12] | y | +------------------------------+---------+---------+ | SHA1 | [11-8] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | DIT | [51-48] | y | +------------------------------+---------+---------+ | MPAM | [43-40] | n | +------------------------------+---------+---------+ | SVE | [35-32] | y | +------------------------------+---------+---------+ | GIC | [27-24] | n | +------------------------------+---------+---------+ | AdvSIMD | [23-20] | y | +------------------------------+---------+---------+ | FP | [19-16] | y | +------------------------------+---------+---------+ | EL3 | [15-12] | n | +------------------------------+---------+---------+ | EL2 | [11-8] | n | +------------------------------+---------+---------+ | EL1 | [7-4] | n | +------------------------------+---------+---------+ | EL0 | [3-0] | n | +------------------------------+---------+---------+ 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | SME | [27-24] | y | +------------------------------+---------+---------+ | MTE | [11-8] | y | +------------------------------+---------+---------+ | SSBS | [7-4] | y | +------------------------------+---------+---------+ | BT | [3-0] | y | +------------------------------+---------+---------+ 4) MIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | Implementer | [31-24] | y | +------------------------------+---------+---------+ | Variant | [23-20] | y | +------------------------------+---------+---------+ | Architecture | [19-16] | y | +------------------------------+---------+---------+ | PartNum | [15-4] | y | +------------------------------+---------+---------+ | Revision | [3-0] | y | +------------------------------+---------+---------+ NOTE: The 'visible' fields of MIDR_EL1 will contain the value as available on the CPU where it is fetched and is not a system wide safe value. 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | I8MM | [55-52] | y | +------------------------------+---------+---------+ | DGH | [51-48] | y | +------------------------------+---------+---------+ | BF16 | [47-44] | y | +------------------------------+---------+---------+ | SB | [39-36] | y | +------------------------------+---------+---------+ | FRINTTS | [35-32] | y | +------------------------------+---------+---------+ | GPI | [31-28] | y | +------------------------------+---------+---------+ | GPA | [27-24] | y | +------------------------------+---------+---------+ | LRCPC | [23-20] | y | +------------------------------+---------+---------+ | FCMA | [19-16] | y | +------------------------------+---------+---------+ | JSCVT | [15-12] | y | +------------------------------+---------+---------+ | API | [11-8] | y | +------------------------------+---------+---------+ | APA | [7-4] | y | +------------------------------+---------+---------+ | DPB | [3-0] | y | +------------------------------+---------+---------+ 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | ECV | [63-60] | y | +------------------------------+---------+---------+ 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | AT | [35-32] | y | +------------------------------+---------+---------+ 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | F64MM | [59-56] | y | +------------------------------+---------+---------+ | F32MM | [55-52] | y | +------------------------------+---------+---------+ | I8MM | [47-44] | y | +------------------------------+---------+---------+ | SM4 | [43-40] | y | +------------------------------+---------+---------+ | SHA3 | [35-32] | y | +------------------------------+---------+---------+ | B16B16 | [27-24] | y | +------------------------------+---------+---------+ | BF16 | [23-20] | y | +------------------------------+---------+---------+ | BitPerm | [19-16] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ | SVEVer | [3-0] | y | +------------------------------+---------+---------+ 8) ID_AA64MMFR1_EL1 - Memory model feature register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | AFP | [47-44] | y | +------------------------------+---------+---------+ 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | CSSC | [55-52] | y | +------------------------------+---------+---------+ | RPRFM | [51-48] | y | +------------------------------+---------+---------+ | BC | [23-20] | y | +------------------------------+---------+---------+ | MOPS | [19-16] | y | +------------------------------+---------+---------+ | APA3 | [15-12] | y | +------------------------------+---------+---------+ | GPA3 | [11-8] | y | +------------------------------+---------+---------+ | RPRES | [7-4] | y | +------------------------------+---------+---------+ | WFXT | [3-0] | y | +------------------------------+---------+---------+ 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | FPDP | [11-8] | y | +------------------------------+---------+---------+ 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | SIMDFMAC | [31-28] | y | +------------------------------+---------+---------+ | SIMDSP | [19-16] | y | +------------------------------+---------+---------+ | SIMDInt | [15-12] | y | +------------------------------+---------+---------+ | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | CRC32 | [19-16] | y | +------------------------------+---------+---------+ | SHA2 | [15-12] | y | +------------------------------+---------+---------+ | SHA1 | [11-8] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ h](j%)}(hhh](j*)}(hX;ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | RNDR | [63-60] | y | +------------------------------+---------+---------+ | TS | [55-52] | y | +------------------------------+---------+---------+ | FHM | [51-48] | y | +------------------------------+---------+---------+ | DP | [47-44] | y | +------------------------------+---------+---------+ | SM4 | [43-40] | y | +------------------------------+---------+---------+ | SM3 | [39-36] | y | +------------------------------+---------+---------+ | SHA3 | [35-32] | y | +------------------------------+---------+---------+ | RDM | [31-28] | y | +------------------------------+---------+---------+ | ATOMICS | [23-20] | y | +------------------------------+---------+---------+ | CRC32 | [19-16] | y | +------------------------------+---------+---------+ | SHA2 | [15-12] | y | +------------------------------+---------+---------+ | SHA1 | [11-8] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ h](h)}(h7ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0h]h7ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjYubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjrubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjrubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjrubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hvisibleh]hvisible}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRNDRh]hRNDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[63-60]h]h[63-60]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hyh]hy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hTSh]hTS}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hj=ubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h)}(h[55-52]h]h[55-52]}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjTubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h)}(hj"h]hy}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjkubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFHMh]hFHM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[51-48]h]h[51-48]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDPh]hDP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[47-44]h]h[47-44]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSM4h]hSM4}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h[43-40]h]h[43-40]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj;ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(hj"h]hy}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSM3h]hSM3}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(h[39-36]h]h[39-36]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSHA3h]hSHA3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[35-32]h]h[35-32]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRDMh]hRDM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[31-28]h]h[31-28]}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hATOMICSh]hATOMICS}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(h[23-20]h]h[23-20]}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjoubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hCRC32h]hCRC32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSHA2h]hSHA2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[15-12]h]h[15-12]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSHA1h]hSHA1}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj?ubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjVubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hhh]h)}(hj"h]hy}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hAESh]hAES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[7-4]h]h[7-4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]colsKuh1jphjmubah}(h]h ]h"]h$]h&]uh1jkhjYubeh}(h]h ]h"]h$]h&]uh1j)hjVubj*)}(hXID_AA64PFR0_EL1 - Processor Feature Register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | DIT | [51-48] | y | +------------------------------+---------+---------+ | MPAM | [43-40] | n | +------------------------------+---------+---------+ | SVE | [35-32] | y | +------------------------------+---------+---------+ | GIC | [27-24] | n | +------------------------------+---------+---------+ | AdvSIMD | [23-20] | y | +------------------------------+---------+---------+ | FP | [19-16] | y | +------------------------------+---------+---------+ | EL3 | [15-12] | n | +------------------------------+---------+---------+ | EL2 | [11-8] | n | +------------------------------+---------+---------+ | EL1 | [7-4] | n | +------------------------------+---------+---------+ | EL0 | [3-0] | n | +------------------------------+---------+---------+ h](h)}(h.ID_AA64PFR0_EL1 - Processor Feature Register 0h]h.ID_AA64PFR0_EL1 - Processor Feature Register 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]h)}(hbitsh]hbits}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjBubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]h)}(hvisibleh]hvisible}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjYubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hDITh]hDIT}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh]h)}(h[51-48]h]h[51-48]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hMPAMh]hMPAM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[43-40]h]h[43-40]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hnh]hn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hSVEh]hSVE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[35-32]h]h[35-32]}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjB ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hGICh]hGIC}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhja ubah}(h]h ]h"]h$]h&]uh1jhj^ ubj)}(hhh]h)}(h[27-24]h]h[27-24]}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjx ubah}(h]h ]h"]h$]h&]uh1jhj^ ubj)}(hhh]h)}(hjh]hn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj^ ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hAdvSIMDh]hAdvSIMD}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[23-20]h]h[23-20]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hFPh]hFP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj) ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hEL3h]hEL3}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjH ubah}(h]h ]h"]h$]h&]uh1jhjE ubj)}(hhh]h)}(h[15-12]h]h[15-12]}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj_ ubah}(h]h ]h"]h$]h&]uh1jhjE ubj)}(hhh]h)}(hjh]hn}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjv ubah}(h]h ]h"]h$]h&]uh1jhjE ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hEL2h]hEL2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hjh]hn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hEL1h]hEL1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[7-4]h]h[7-4]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hjh]hn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(hEL0h]hEL0}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj/ ubah}(h]h ]h"]h$]h&]uh1jhj, ubj)}(hhh]h)}(h[3-0]h]h[3-0]}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjF ubah}(h]h ]h"]h$]h&]uh1jhj, ubj)}(hhh]h)}(hjh]hn}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj] ubah}(h]h ]h"]h$]h&]uh1jhj, ubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1j)hjVubj*)}(hXxID_AA64PFR1_EL1 - Processor Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | SME | [27-24] | y | +------------------------------+---------+---------+ | MTE | [11-8] | y | +------------------------------+---------+---------+ | SSBS | [7-4] | y | +------------------------------+---------+---------+ | BT | [3-0] | y | +------------------------------+---------+---------+ h](h)}(h.ID_AA64PFR1_EL1 - Processor Feature Register 1h]h.ID_AA64PFR1_EL1 - Processor Feature Register 1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhj ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hbitsh]hbits}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hvisibleh]hvisible}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hSMEh]hSME}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[27-24]h]h[27-24]}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj3 ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hMTEh]hMTE}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhji ubah}(h]h ]h"]h$]h&]uh1jhjf ubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjf ubj)}(hhh]h)}(hj"h]hy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjf ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hSSBSh]hSSBS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[7-4]h]h[7-4]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hBTh]hBT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[3-0]h]h[3-0]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj1 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jphj ubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1j)hjVubj*)}(hXMIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | Implementer | [31-24] | y | +------------------------------+---------+---------+ | Variant | [23-20] | y | +------------------------------+---------+---------+ | Architecture | [19-16] | y | +------------------------------+---------+---------+ | PartNum | [15-4] | y | +------------------------------+---------+---------+ | Revision | [3-0] | y | +------------------------------+---------+---------+ h](h)}(hMIDR_EL1 - Main ID Registerh]hMIDR_EL1 - Main ID Register}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjf ubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhj{ ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj{ ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj{ ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hbitsh]hbits}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hvisibleh]hvisible}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h Implementerh]h Implementer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h[31-24]h]h[31-24]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj"h]hy}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hVarianth]hVariant}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj=ubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h)}(h[23-20]h]h[23-20]}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h)}(hj"h]hy}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h Architectureh]h Architecture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hPartNumh]hPartNum}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[15-4]h]h[15-4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(hRevisionh]hRevision}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h[3-0]h]h[3-0]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj;ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(hj"h]hy}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj{ ubeh}(h]h ]h"]h$]h&]colsKuh1jphjx ubah}(h]h ]h"]h$]h&]uh1jkhjf ubeh}(h]h ]h"]h$]h&]uh1j)hjVubeh}(h]h ]h"]h$]h&]jyarabicj{hj|j}uh1j$hjRubj)}(hNOTE: The 'visible' fields of MIDR_EL1 will contain the value as available on the CPU where it is fetched and is not a system wide safe value. h]h)}(hNOTE: The 'visible' fields of MIDR_EL1 will contain the value as available on the CPU where it is fetched and is not a system wide safe value.h]hNOTE: The ‘visible’ fields of MIDR_EL1 will contain the value as available on the CPU where it is fetched and is not a system wide safe value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhhhKhjRubj%)}(hhh](j*)}(hX:ID_AA64ISAR1_EL1 - Instruction set attribute register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | I8MM | [55-52] | y | +------------------------------+---------+---------+ | DGH | [51-48] | y | +------------------------------+---------+---------+ | BF16 | [47-44] | y | +------------------------------+---------+---------+ | SB | [39-36] | y | +------------------------------+---------+---------+ | FRINTTS | [35-32] | y | +------------------------------+---------+---------+ | GPI | [31-28] | y | +------------------------------+---------+---------+ | GPA | [27-24] | y | +------------------------------+---------+---------+ | LRCPC | [23-20] | y | +------------------------------+---------+---------+ | FCMA | [19-16] | y | +------------------------------+---------+---------+ | JSCVT | [15-12] | y | +------------------------------+---------+---------+ | API | [11-8] | y | +------------------------------+---------+---------+ | APA | [7-4] | y | +------------------------------+---------+---------+ | DPB | [3-0] | y | +------------------------------+---------+---------+ h](h)}(h7ID_AA64ISAR1_EL1 - Instruction set attribute register 1h]h7ID_AA64ISAR1_EL1 - Instruction set attribute register 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hvisibleh]hvisible}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hI8MMh]hI8MM}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj3ubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(hhh]h)}(h[55-52]h]h[55-52]}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(hhh]h)}(hj"h]hy}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjaubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDGHh]hDGH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(h[51-48]h]h[51-48]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBF16h]hBF16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[47-44]h]h[47-44]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSBh]hSB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[39-36]h]h[39-36]}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj1ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjKhhhNUhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjHubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFRINTTSh]hFRINTTS}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjgubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(h[35-32]h]h[35-32]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj~ubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hGPIh]hGPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[31-28]h]h[31-28]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hGPAh]hGPA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[27-24]h]h[27-24]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hLRCPCh]hLRCPC}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1jhjKubj)}(hhh]h)}(h[23-20]h]h[23-20]}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1jhjKubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj|ubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFCMAh]hFCMA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hJSCVTh]hJSCVT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[15-12]h]h[15-12]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hAPIh]hAPI}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]h)}(hj"h]hy}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hAPAh]hAPA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[7-4]h]h[7-4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDPBh]hDPB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[3-0]h]h[3-0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hX=ID_AA64MMFR0_EL1 - Memory model feature register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | ECV | [63-60] | y | +------------------------------+---------+---------+ h](h)}(h2ID_AA64MMFR0_EL1 - Memory model feature register 0h]h2ID_AA64MMFR0_EL1 - Memory model feature register 0}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjGubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjGubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjGubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnubah}(h]h ]h"]h$]h&]uh1jhjkubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjkubj)}(hhh]h)}(hvisibleh]hvisible}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjhubj)}(hhh](j)}(hhh]h)}(hECVh]hECV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[63-60]h]h[63-60]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]colsKuh1jphjDubah}(h]h ]h"]h$]h&]uh1jkhj2ubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hX=ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | AT | [35-32] | y | +------------------------------+---------+---------+ h](h)}(h2ID_AA64MMFR2_EL1 - Memory model feature register 2h]h2ID_AA64MMFR2_EL1 - Memory model feature register 2}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhj4ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj4ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj4ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj[ubah}(h]h ]h"]h$]h&]uh1jhjXubj)}(hhh]h)}(hbitsh]hbits}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrubah}(h]h ]h"]h$]h&]uh1jhjXubj)}(hhh]h)}(hvisibleh]hvisible}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh](j)}(hhh]h)}(hATh]hAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[35-32]h]h[35-32]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]colsKuh1jphj1ubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hXID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | F64MM | [59-56] | y | +------------------------------+---------+---------+ | F32MM | [55-52] | y | +------------------------------+---------+---------+ | I8MM | [47-44] | y | +------------------------------+---------+---------+ | SM4 | [43-40] | y | +------------------------------+---------+---------+ | SHA3 | [35-32] | y | +------------------------------+---------+---------+ | B16B16 | [27-24] | y | +------------------------------+---------+---------+ | BF16 | [23-20] | y | +------------------------------+---------+---------+ | BitPerm | [19-16] | y | +------------------------------+---------+---------+ | AES | [7-4] | y | +------------------------------+---------+---------+ | SVEVer | [3-0] | y | +------------------------------+---------+---------+ h](h)}(h+ID_AA64ZFR0_EL1 - SVE feature ID register 0h]h+ID_AA64ZFR0_EL1 - SVE feature ID register 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhj!ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj!ubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhj!ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjHubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hbitsh]hbits}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_ubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hvisibleh]hvisible}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjvubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hF64MMh]hF64MM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[59-56]h]h[59-56]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hF32MMh]hF32MM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[55-52]h]h[55-52]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hI8MMh]hI8MM}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj0ubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]h)}(h[47-44]h]h[47-44]}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjGubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]h)}(hj"h]hy}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hSM4h]hSM4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj}ubah}(h]h ]h"]h$]h&]uh1jhjzubj)}(hhh]h)}(h[43-40]h]h[43-40]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjzubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hSHA3h]hSHA3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[35-32]h]h[35-32]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hB16B16h]hB16B16}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[27-24]h]h[27-24]}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hBF16h]hBF16}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjdubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(h[23-20]h]h[23-20]}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj{ubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hBitPermh]hBitPerm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hAESh]hAES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[7-4]h]h[7-4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(hSVEVerh]hSVEVer}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKubah}(h]h ]h"]h$]h&]uh1jhjHubj)}(hhh]h)}(h[3-0]h]h[3-0]}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjbubah}(h]h ]h"]h$]h&]uh1jhjHubj)}(hhh]h)}(hj"h]hy}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjyubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]jyjj{hj|j}startKuh1j$hjRubj%)}(hhh](j*)}(hX=ID_AA64MMFR1_EL1 - Memory model feature register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | AFP | [47-44] | y | +------------------------------+---------+---------+ h](h)}(h2ID_AA64MMFR1_EL1 - Memory model feature register 1h]h2ID_AA64MMFR1_EL1 - Memory model feature register 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hvisibleh]hvisible}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hAFPh]hAFP}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjBubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(h[47-44]h]h[47-44]}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjYubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(hj"h]hy}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjpubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(hX(ID_AA64ISAR2_EL1 - Instruction set attribute register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | CSSC | [55-52] | y | +------------------------------+---------+---------+ | RPRFM | [51-48] | y | +------------------------------+---------+---------+ | BC | [23-20] | y | +------------------------------+---------+---------+ | MOPS | [19-16] | y | +------------------------------+---------+---------+ | APA3 | [15-12] | y | +------------------------------+---------+---------+ | GPA3 | [11-8] | y | +------------------------------+---------+---------+ | RPRES | [7-4] | y | +------------------------------+---------+---------+ | WFXT | [3-0] | y | +------------------------------+---------+---------+ h](h)}(h7ID_AA64ISAR2_EL1 - Instruction set attribute register 2h]h7ID_AA64ISAR2_EL1 - Instruction set attribute register 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjubjl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hvisibleh]hvisible}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hCSSCh]hCSSC}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hj/ubah}(h]h ]h"]h$]h&]uh1jhj,ubj)}(hhh]h)}(h[55-52]h]h[55-52]}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hjFubah}(h]h ]h"]h$]h&]uh1jhj,ubj)}(hhh]h)}(hj"h]hy}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hj]ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRPRFMh]hRPRFM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj|ubah}(h]h ]h"]h$]h&]uh1jhjyubj)}(hhh]h)}(h[51-48]h]h[51-48]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjubah}(h]h ]h"]h$]h&]uh1jhjyubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBCh]hBC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[23-20]h]h[23-20]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMOPSh]hMOPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj-ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjDubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hAPA3h]hAPA3}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjcubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(hhh]h)}(h[15-12]h]h[15-12]}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjzubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hGPA3h]hGPA3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRPRESh]hRPRES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[7-4]h]h[7-4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hWFXTh]hWFXT}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hjJubah}(h]h ]h"]h$]h&]uh1jhjGubj)}(hhh]h)}(h[3-0]h]h[3-0]}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hjaubah}(h]h ]h"]h$]h&]uh1jhjGubj)}(hhh]h)}(hj"h]hy}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hjxubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ]h"]h$]h&]uh1j)hjubj*)}(h5MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 h]h)}(h4MVFR0_EL1 - AArch32 Media and VFP Feature Register 0h]h4MVFR0_EL1 - AArch32 Media and VFP Feature Register 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]jyjj{hj|j}jKuh1j$hjRubj)}(hX +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | FPDP | [11-8] | y | +------------------------------+---------+---------+ h]jl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hvisibleh]hvisible}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFPDPh]hFPDP}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjGubah}(h]h ]h"]h$]h&]uh1jhjDubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hj^ubah}(h]h ]h"]h$]h&]uh1jhjDubj)}(hhh]h)}(hj"h]hy}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjuubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhjubah}(h]h ]h"]h$]h&]uh1jhhhM=hjRubj%)}(hhh]j*)}(h5MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 h]h)}(h4MVFR1_EL1 - AArch32 Media and VFP Feature Register 1h]h4MVFR1_EL1 - AArch32 Media and VFP Feature Register 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]jyjj{hj|j}jK uh1j$hjRubj)}(hXG+------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ | SIMDFMAC | [31-28] | y | +------------------------------+---------+---------+ | SIMDSP | [19-16] | y | +------------------------------+---------+---------+ | SIMDInt | [15-12] | y | +------------------------------+---------+---------+ | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ h]jl)}(hhh]jq)}(hhh](jv)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubjv)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1juhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hbitsh]hbits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hvisibleh]hvisible}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSIMDFMACh]hSIMDFMAC}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjGubah}(h]h ]h"]h$]h&]uh1jhjDubj)}(hhh]h)}(h[31-28]h]h[31-28]}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj^ubah}(h]h ]h"]h$]h&]uh1jhjDubj)}(hhh]h)}(hj"h]hy}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjuubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSIMDSPh]hSIMDSP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[19-16]h]h[19-16]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSIMDInth]hSIMDInt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[15-12]h]h[15-12]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hj"h]hy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSIMDLSh]hSIMDLS}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj. ubah}(h]h ]h"]h$]h&]uh1jhj+ ubj)}(hhh]h)}(h[11-8]h]h[11-8]}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjE ubah}(h]h ]h"]h$]h&]uh1jhj+ ubj)}(hhh]h)}(hj"h]hy}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj\ ubah}(h]h ]h"]h$]h&]uh1jhj+ ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jphjubah}(h]h ]h"]h$]h&]uh1jkhjubah}(h]h ]h"]h$]h&]uh1jhhhMEhjRubj%)}(hhh]j*)}(h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #define get_cpu_ftr(id) ({ \ unsigned long __val; \ asm("mrs %0, "#id : "=r" (__val)); \ printf("%-20s: 0x%016lx\n", #id, __val); \ }) int main(void) { if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { fputs("CPUID registers unavailable\n", stderr); return 1; } get_cpu_ftr(ID_AA64ISAR0_EL1); get_cpu_ftr(ID_AA64ISAR1_EL1); get_cpu_ftr(ID_AA64MMFR0_EL1); get_cpu_ftr(ID_AA64MMFR1_EL1); get_cpu_ftr(ID_AA64PFR0_EL1); get_cpu_ftr(ID_AA64PFR1_EL1); get_cpu_ftr(ID_AA64DFR0_EL1); get_cpu_ftr(ID_AA64DFR1_EL1); get_cpu_ftr(MIDR_EL1); get_cpu_ftr(MPIDR_EL1); get_cpu_ftr(REVIDR_EL1); #if 0 /* Unexposed register access causes SIGILL */ get_cpu_ftr(ID_MMFR0_EL1); #endif return 0; }h]hX/* * Sample program to demonstrate the MRS emulation ABI. * * Copyright (C) 2015-2016, ARM Ltd * * Author: Suzuki K Poulose * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #define get_cpu_ftr(id) ({ \ unsigned long __val; \ asm("mrs %0, "#id : "=r" (__val)); \ printf("%-20s: 0x%016lx\n", #id, __val); \ }) int main(void) { if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { fputs("CPUID registers unavailable\n", stderr); return 1; } get_cpu_ftr(ID_AA64ISAR0_EL1); get_cpu_ftr(ID_AA64ISAR1_EL1); get_cpu_ftr(ID_AA64MMFR0_EL1); get_cpu_ftr(ID_AA64MMFR1_EL1); get_cpu_ftr(ID_AA64PFR0_EL1); get_cpu_ftr(ID_AA64PFR1_EL1); get_cpu_ftr(ID_AA64DFR0_EL1); get_cpu_ftr(ID_AA64DFR1_EL1); get_cpu_ftr(MIDR_EL1); get_cpu_ftr(MPIDR_EL1); get_cpu_ftr(REVIDR_EL1); #if 0 /* Unexposed register access causes SIGILL */ get_cpu_ftr(ID_MMFR0_EL1); #endif return 0; }}hj"sbah}(h]h ]h"]h$]h&]jTjUuh1jDhhhMehj"hhubeh}(h]appendix-i-exampleah ]h"]appendix i: exampleah$]h&]uh1hhhhhhhhMaubeh}(h]arm64-cpu-feature-registersah ]h"]arm64 cpu feature registersah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj"error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehʌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j"j"jjjmjjj>j;j"j"j"j"u nametypes}(j"jjmj>j"j"uh}(j"hjhjjjj;jpj"jAj"j"u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages](hsystem_message)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "5" (ordinal 5)h]h>Enumerated list start value not ordinal-1: “5” (ordinal 5)}(hj>#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;#ubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehʌlineKuh1j9#hjRubj:#)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "8" (ordinal 8)h]h>Enumerated list start value not ordinal-1: “8” (ordinal 8)}(hjZ#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjW#ubah}(h]h ]h"]h$]h&]levelKtypejT#sourcehʌlineKuh1j9#hjRubj:#)}(hhh]h)}(h