€•ëNŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ"/translations/zh_CN/arch/arm64/amu”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ"/translations/zh_TW/arch/arm64/amu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ"/translations/it_IT/arch/arm64/amu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ"/translations/ja_JP/arch/arm64/amu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ"/translations/ko_KR/arch/arm64/amu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ"/translations/sp_SP/arch/arm64/amu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒtarget”“”)”}”(hŒ.. _amu_index:”h]”h}”(h]”h ]”h"]”h$]”h&]”Œrefid”Œ amu-index”uh1h¡h KhhhžhhŸŒ”h]”(hŒAuthor: Ionela Voinescu <”…””}”(hhÇhžhhŸNh NubhŒ reference”“”)”}”(hŒionela.voinescu@arm.com”h]”hŒionela.voinescu@arm.com”…””}”(hhÑhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:ionela.voinescu@arm.com”uh1hÏhhÇubhŒ>”…””}”(hhÇhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Khh²hžhubhÆ)”}”(hŒDate: 2019-09-10”h]”hŒDate: 2019-09-10”…””}”(hhëhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K hh²hžhubhÆ)”}”(hŒaThis document briefly describes the provision of Activity Monitors Unit support in AArch64 Linux.”h]”hŒaThis document briefly describes the provision of Activity Monitors Unit support in AArch64 Linux.”…””}”(hhùhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K hh²hžhubh±)”}”(hhh]”(h¶)”}”(hŒArchitecture overview”h]”hŒArchitecture overview”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hµhjhžhhŸh¯h KubhÆ)”}”(hŒdThe activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture.”h]”hŒdThe activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KhjhžhubhÆ)”}”(hXThe activity monitors unit, implemented in each CPU, provides performance counters intended for system management use. The AMU extension provides a system register interface to the counter registers and also supports an optional external memory-mapped interface.”h]”hXThe activity monitors unit, implemented in each CPU, provides performance counters intended for system management use. The AMU extension provides a system register interface to the counter registers and also supports an optional external memory-mapped interface.”…””}”(hj&hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KhjhžhubhÆ)”}”(hŒ‹Version 1 of the Activity Monitors architecture implements a counter group of four fixed and architecturally defined 64-bit event counters.”h]”hŒ‹Version 1 of the Activity Monitors architecture implements a counter group of four fixed and architecturally defined 64-bit event counters.”…””}”(hj4hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KhjhžhubhŒ block_quote”“”)”}”(hXd- CPU cycle counter: increments at the frequency of the CPU. - Constant counter: increments at the fixed frequency of the system clock. - Instructions retired: increments with every architecturally executed instruction. - Memory stall cycles: counts instruction dispatch stall cycles caused by misses in the last level cache within the clock domain. ”h]”hŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ:CPU cycle counter: increments at the frequency of the CPU.”h]”hÆ)”}”(hjQh]”hŒ:CPU cycle counter: increments at the frequency of the CPU.”…””}”(hjShžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KhjOubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjJubjN)”}”(hŒHConstant counter: increments at the fixed frequency of the system clock.”h]”hÆ)”}”(hŒHConstant counter: increments at the fixed frequency of the system clock.”h]”hŒHConstant counter: increments at the fixed frequency of the system clock.”…””}”(hjjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Khjfubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjJubjN)”}”(hŒQInstructions retired: increments with every architecturally executed instruction.”h]”hÆ)”}”(hŒQInstructions retired: increments with every architecturally executed instruction.”h]”hŒQInstructions retired: increments with every architecturally executed instruction.”…””}”(hj‚hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K hj~ubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjJubjN)”}”(hŒ€Memory stall cycles: counts instruction dispatch stall cycles caused by misses in the last level cache within the clock domain. ”h]”hÆ)”}”(hŒMemory stall cycles: counts instruction dispatch stall cycles caused by misses in the last level cache within the clock domain.”h]”hŒMemory stall cycles: counts instruction dispatch stall cycles caused by misses in the last level cache within the clock domain.”…””}”(hjšhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K"hj–ubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjJubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jHhŸh¯h KhjDubah}”(h]”h ]”h"]”h$]”h&]”uh1jBhŸh¯h KhjhžhubhÆ)”}”(hŒ3When in WFI or WFE these counters do not increment.”h]”hŒ3When in WFI or WFE these counters do not increment.”…””}”(hj¼hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K%hjhžhubhÆ)”}”(hŒÅThe Activity Monitors architecture provides space for up to 16 architected event counters. Future versions of the architecture may use this space to implement additional architected event counters.”h]”hŒÅThe Activity Monitors architecture provides space for up to 16 architected event counters. Future versions of the architecture may use this space to implement additional architected event counters.”…””}”(hjÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K'hjhžhubhÆ)”}”(hŒ_Additionally, version 1 implements a counter group of up to 16 auxiliary 64-bit event counters.”h]”hŒ_Additionally, version 1 implements a counter group of up to 16 auxiliary 64-bit event counters.”…””}”(hjØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K+hjhžhubhÆ)”}”(hŒ&On cold reset all counters reset to 0.”h]”hŒ&On cold reset all counters reset to 0.”…””}”(hjæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K.hjhžhubeh}”(h]”Œarchitecture-overview”ah ]”h"]”Œarchitecture overview”ah$]”h&]”uh1h°hh²hžhhŸh¯h Kubh±)”}”(hhh]”(h¶)”}”(hŒ Basic support”h]”hŒ Basic support”…””}”(hjÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hµhjühžhhŸh¯h K2ubhÆ)”}”(hXThe kernel can safely run a mix of CPUs with and without support for the activity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is selected we unconditionally enable the capability to allow any late CPU (secondary or hotplugged) to detect and use the feature.”h]”hXThe kernel can safely run a mix of CPUs with and without support for the activity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is selected we unconditionally enable the capability to allow any late CPU (secondary or hotplugged) to detect and use the feature.”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K4hjühžhubhÆ)”}”(hŒ¹When the feature is detected on a CPU, we flag the availability of the feature but this does not guarantee the correct functionality of the counters, only the presence of the extension.”h]”hŒ¹When the feature is detected on a CPU, we flag the availability of the feature but this does not guarantee the correct functionality of the counters, only the presence of the extension.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K9hjühžhubhÆ)”}”(hŒUFirmware (code running at higher exception levels, e.g. arm-tf) support is needed to:”h]”hŒUFirmware (code running at higher exception levels, e.g. arm-tf) support is needed to:”…””}”(hj)hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K=hjühžhubjC)”}”(hŒô- Enable access for lower exception levels (EL2 and EL1) to the AMU registers. - Enable the counters. If not enabled these will read as 0. - Save/restore the counters before/after the CPU is being put/brought up from the 'off' power state. ”h]”jI)”}”(hhh]”(jN)”}”(hŒLEnable access for lower exception levels (EL2 and EL1) to the AMU registers.”h]”hÆ)”}”(hŒLEnable access for lower exception levels (EL2 and EL1) to the AMU registers.”h]”hŒLEnable access for lower exception levels (EL2 and EL1) to the AMU registers.”…””}”(hjBhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K@hj>ubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj;ubjN)”}”(hŒ9Enable the counters. If not enabled these will read as 0.”h]”hÆ)”}”(hjXh]”hŒ9Enable the counters. If not enabled these will read as 0.”…””}”(hjZhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KBhjVubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj;ubjN)”}”(hŒcSave/restore the counters before/after the CPU is being put/brought up from the 'off' power state. ”h]”hÆ)”}”(hŒbSave/restore the counters before/after the CPU is being put/brought up from the 'off' power state.”h]”hŒfSave/restore the counters before/after the CPU is being put/brought up from the ‘off’ power state.”…””}”(hjqhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KChjmubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj;ubeh}”(h]”h ]”h"]”h$]”h&]”j´jµuh1jHhŸh¯h K@hj7ubah}”(h]”h ]”h"]”h$]”h&]”uh1jBhŸh¯h K@hjühžhubhÆ)”}”(hXiWhen using kernels that have this feature enabled but boot with broken firmware the user may experience panics or lockups when accessing the counter registers. Even if these symptoms are not observed, the values returned by the register reads might not correctly reflect reality. Most commonly, the counters will read as 0, indicating that they are not enabled.”h]”hXiWhen using kernels that have this feature enabled but boot with broken firmware the user may experience panics or lockups when accessing the counter registers. Even if these symptoms are not observed, the values returned by the register reads might not correctly reflect reality. Most commonly, the counters will read as 0, indicating that they are not enabled.”…””}”(hj‘hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KFhjühžhubhÆ)”}”(hXGIf proper support is not provided in firmware it's best to disable CONFIG_ARM64_AMU_EXTN. To be noted that for security reasons, this does not bypass the setting of AMUSERENR_EL0 to trap accesses from EL0 (userspace) to EL1 (kernel). Therefore, firmware should still ensure accesses to AMU registers are not trapped in EL2/EL3.”h]”hXIIf proper support is not provided in firmware it’s best to disable CONFIG_ARM64_AMU_EXTN. To be noted that for security reasons, this does not bypass the setting of AMUSERENR_EL0 to trap accesses from EL0 (userspace) to EL1 (kernel). Therefore, firmware should still ensure accesses to AMU registers are not trapped in EL2/EL3.”…””}”(hjŸhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KMhjühžhubhÆ)”}”(hŒ]The fixed counters of AMUv1 are accessible through the following system register definitions:”h]”hŒ]The fixed counters of AMUv1 are accessible through the following system register definitions:”…””}”(hj­hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KShjühžhubjC)”}”(hŒn- SYS_AMEVCNTR0_CORE_EL0 - SYS_AMEVCNTR0_CONST_EL0 - SYS_AMEVCNTR0_INST_RET_EL0 - SYS_AMEVCNTR0_MEM_STALL_EL0 ”h]”jI)”}”(hhh]”(jN)”}”(hŒSYS_AMEVCNTR0_CORE_EL0”h]”hÆ)”}”(hjÄh]”hŒSYS_AMEVCNTR0_CORE_EL0”…””}”(hjÆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KVhjÂubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj¿ubjN)”}”(hŒSYS_AMEVCNTR0_CONST_EL0”h]”hÆ)”}”(hjÛh]”hŒSYS_AMEVCNTR0_CONST_EL0”…””}”(hjÝhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KWhjÙubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj¿ubjN)”}”(hŒSYS_AMEVCNTR0_INST_RET_EL0”h]”hÆ)”}”(hjòh]”hŒSYS_AMEVCNTR0_INST_RET_EL0”…””}”(hjôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KXhjðubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj¿ubjN)”}”(hŒSYS_AMEVCNTR0_MEM_STALL_EL0 ”h]”hÆ)”}”(hŒSYS_AMEVCNTR0_MEM_STALL_EL0”h]”hŒSYS_AMEVCNTR0_MEM_STALL_EL0”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KYhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhj¿ubeh}”(h]”h ]”h"]”h$]”h&]”j´jµuh1jHhŸh¯h KVhj»ubah}”(h]”h ]”h"]”h$]”h&]”uh1jBhŸh¯h KVhjühžhubhÆ)”}”(hŒuAuxiliary platform specific counters can be accessed using SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15.”h]”hŒuAuxiliary platform specific counters can be accessed using SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15.”…””}”(hj+hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K[hjühžhubhÆ)”}”(hŒ9Details can be found in: arch/arm64/include/asm/sysreg.h.”h]”hŒ9Details can be found in: arch/arm64/include/asm/sysreg.h.”…””}”(hj9hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h K^hjühžhubeh}”(h]”Œ basic-support”ah ]”h"]”Œ basic support”ah$]”h&]”uh1h°hh²hžhhŸh¯h K2ubh±)”}”(hhh]”(h¶)”}”(hŒUserspace access”h]”hŒUserspace access”…””}”(hjRhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hµhjOhžhhŸh¯h KbubhÆ)”}”(hŒICurrently, access from userspace to the AMU registers is disabled due to:”h]”hŒICurrently, access from userspace to the AMU registers is disabled due to:”…””}”(hj`hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KdhjOhžhubjC)”}”(hŒ˜- Security reasons: they might expose information about code executed in secure mode. - Purpose: AMU counters are intended for system management use. ”h]”jI)”}”(hhh]”(jN)”}”(hŒSSecurity reasons: they might expose information about code executed in secure mode.”h]”hÆ)”}”(hŒSSecurity reasons: they might expose information about code executed in secure mode.”h]”hŒSSecurity reasons: they might expose information about code executed in secure mode.”…””}”(hjyhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Kfhjuubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjrubjN)”}”(hŒ>Purpose: AMU counters are intended for system management use. ”h]”hÆ)”}”(hŒ=Purpose: AMU counters are intended for system management use.”h]”hŒ=Purpose: AMU counters are intended for system management use.”…””}”(hj‘hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Khhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjrubeh}”(h]”h ]”h"]”h$]”h&]”j´jµuh1jHhŸh¯h Kfhjnubah}”(h]”h ]”h"]”h$]”h&]”uh1jBhŸh¯h KfhjOhžhubhÆ)”}”(hŒ>Also, the presence of the feature is not visible to userspace.”h]”hŒ>Also, the presence of the feature is not visible to userspace.”…””}”(hj±hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KjhjOhžhubeh}”(h]”Œuserspace-access”ah ]”h"]”Œuserspace access”ah$]”h&]”uh1h°hh²hžhhŸh¯h Kbubh±)”}”(hhh]”(h¶)”}”(hŒVirtualization”h]”hŒVirtualization”…””}”(hjÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hµhjÇhžhhŸh¯h KnubhÆ)”}”(hŒfCurrently, access from userspace (EL0) and kernelspace (EL1) on the KVM guest side is disabled due to:”h]”hŒfCurrently, access from userspace (EL0) and kernelspace (EL1) on the KVM guest side is disabled due to:”…””}”(hjØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KphjÇhžhubjC)”}”(hŒe- Security reasons: they might expose information about code executed by other guests or the host. ”h]”jI)”}”(hhh]”jN)”}”(hŒaSecurity reasons: they might expose information about code executed by other guests or the host. ”h]”hÆ)”}”(hŒ`Security reasons: they might expose information about code executed by other guests or the host.”h]”hŒ`Security reasons: they might expose information about code executed by other guests or the host.”…””}”(hjñhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h Kshjíubah}”(h]”h ]”h"]”h$]”h&]”uh1jMhjêubah}”(h]”h ]”h"]”h$]”h&]”j´jµuh1jHhŸh¯h Kshjæubah}”(h]”h ]”h"]”h$]”h&]”uh1jBhŸh¯h KshjÇhžhubhÆ)”}”(hŒlAny attempt to access the AMU registers will result in an UNDEFINED exception being injected into the guest.”h]”hŒlAny attempt to access the AMU registers will result in an UNDEFINED exception being injected into the guest.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhŸh¯h KvhjÇhžhubeh}”(h]”Œvirtualization”ah ]”h"]”Œvirtualization”ah$]”h&]”uh1h°hh²hžhhŸh¯h Knubeh}”(h]”(Œ5activity-monitors-unit-amu-extension-in-aarch64-linux”h®eh ]”h"]”(Œ7activity monitors unit (amu) extension in aarch64 linux”Œ amu_index”eh$]”h&]”uh1h°hhhžhhŸh¯h KŒexpect_referenced_by_name”}”j-h£sŒexpect_referenced_by_id”}”h®h£subeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¯uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hµNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jWŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¯Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”h®]”h£asŒnameids”}”(j-h®j,j)jùjöjLjIjÄjÁj$j!uŒ nametypes”}”(j-ˆj,‰jù‰jL‰jĉj$‰uh}”(h®h²j)h²jöjjIjüjÁjOj!jÇuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”hŒsystem_message”“”)”}”(hhh]”hÆ)”}”(hhh]”hŒ/Hyperlink target "amu-index" is not referenced.”…””}”hjÁsbah}”(h]”h ]”h"]”h$]”h&]”uh1hÅhj¾ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”ŒINFO”Œsource”h¯Œline”Kuh1j¼ubaŒ transformer”NŒ include_log”]”Œ decoration”Nhžhub.