sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget0/translations/zh_CN/arch/arm64/acpi_object_usagemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget0/translations/zh_TW/arch/arm64/acpi_object_usagemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget0/translations/it_IT/arch/arm64/acpi_object_usagemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget0/translations/ja_JP/arch/arm64/acpi_object_usagemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget0/translations/ko_KR/arch/arm64/acpi_object_usagemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget0/translations/sp_SP/arch/arm64/acpi_object_usagemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h ACPI Tablesh]h ACPI Tables}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhJ/var/lib/git/docbuild/linux/Documentation/arch/arm64/acpi_object_usage.rsthKubh paragraph)}(hRThe expectations of individual ACPI tables are discussed in the list that follows.h]hRThe expectations of individual ACPI tables are discussed in the list that follows.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXqIf a section number is used, it refers to a section number in the ACPI specification where the object is defined. If "Signature Reserved" is used, the table signature (the first four bytes of the table) is the only portion of the table recognized by the specification, and the actual table is defined outside of the UEFI Forum (see Section 5.2.6 of the specification).h]hXuIf a section number is used, it refers to a section number in the ACPI specification where the object is defined. If “Signature Reserved” is used, the table signature (the first four bytes of the table) is the only portion of the table recognized by the specification, and the actual table is defined outside of the UEFI Forum (see Section 5.2.6 of the specification).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hBFor ACPI on arm64, tables also fall into the following categories:h]hBFor ACPI on arm64, tables also fall into the following categories:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hX- Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT - Optional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, HMAT, IBFT, IORT, MCHI, MPAM, MPST, MSCT, NFIT, PMTT, PPTT, RASF, SBST, SDEI, SLIT, SPMI, SRAT, STAO, TCPA, TPM2, UEFI, XENV - Not supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx, PDTT, PSDT, RAS2, RSDT, SLIC, WAET, WDAT, WDRT, WPBT h]h bullet_list)}(hhh](h list_item)}(h9Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT h]h)}(h8Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDTh]h8Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h0Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT h]h)}(h/Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDTh]h/Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hOptional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, HMAT, IBFT, IORT, MCHI, MPAM, MPST, MSCT, NFIT, PMTT, PPTT, RASF, SBST, SDEI, SLIT, SPMI, SRAT, STAO, TCPA, TPM2, UEFI, XENV h]h)}(hOptional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, HMAT, IBFT, IORT, MCHI, MPAM, MPST, MSCT, NFIT, PMTT, PPTT, RASF, SBST, SDEI, SLIT, SPMI, SRAT, STAO, TCPA, TPM2, UEFI, XENVh]hOptional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, HMAT, IBFT, IORT, MCHI, MPAM, MPST, MSCT, NFIT, PMTT, PPTT, RASF, SBST, SDEI, SLIT, SPMI, SRAT, STAO, TCPA, TPM2, UEFI, XENV}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hNot supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx, PDTT, PSDT, RAS2, RSDT, SLIC, WAET, WDAT, WDRT, WPBT h]h)}(hNot supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx, PDTT, PSDT, RAS2, RSDT, SLIC, WAET, WDAT, WDRT, WPBTh]hNot supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx, PDTT, PSDT, RAS2, RSDT, SLIC, WAET, WDAT, WDRT, WPBT}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj8ubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhhjeubji)}(hhh]h}(h]h ]h"]h$]h&]colwidthKOuh1jhhjeubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hTableh]hTable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hUsage for ARMv8 Linuxh]hUsage for ARMv8 Linux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j~hjeubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(hAESTh]hAEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "AEST")h]h,Signature Reserved (signature == “AEST”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h**Arm Error Source Table**h]hstrong)}(hjh]hArm Error Source Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhK hjubh)}(hlThis table informs the OS of any error nodes in the system that are compliant with the Arm RAS architecture.h]hlThis table informs the OS of any error nodes in the system that are compliant with the Arm RAS architecture.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hAGDIh]hAGDI}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj*ubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(hhh](h)}(h(Signature Reserved (signature == "AGDI")h]h,Signature Reserved (signature == “AGDI”)}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjAubh)}(h@**Arm Generic diagnostic Dump and Reset Device Interface Table**h]j)}(hjTh]hubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](h)}(h(Signature Reserved (signature == "BOOT")h]h,Signature Reserved (signature == “BOOT”)}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjUubh)}(h**simple BOOT flag table**h]j)}(hjhh]hsimple BOOT flag table}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hhhhKhjUubeh}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBGRTh]hBGRT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.22 (signature == "BGRT")h]h(Section 5.2.22 (signature == “BGRT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubh)}(h **Boot Graphics Resource Table**h]j)}(hjh]hBoot Graphics Resource Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKBhjubh)}(hKOptional, not currently supported, with no real use-case for an ARM server.h]hKOptional, not currently supported, with no real use-case for an ARM server.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hCEDTh]hCEDT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "CEDT")h]h,Signature Reserved (signature == “CEDT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhj ubh)}(h**CXL Early Discovery Table**h]j)}(hj h]hCXL Early Discovery Table}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKIhj ubh)}(hXThis table allows the OS to discover any CXL Host Bridges and the Host Bridge registers.h]hXThis table allows the OS to discover any CXL Host Bridges and the Host Bridge registers.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hCPEPh]hCPEP}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjRubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh](h)}(h$Section 5.2.18 (signature == "CPEP")h]h(Section 5.2.18 (signature == “CPEP”)}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjiubh)}(h***Corrected Platform Error Polling table**h]j)}(hj|h]h&Corrected Platform Error Polling table}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hhhhKPhjiubh)}(hOptional, not currently supported, and not recommended until such time as ARM-compatible hardware is available, and the specification suitably modified.h]hOptional, not currently supported, and not recommended until such time as ARM-compatible hardware is available, and the specification suitably modified.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjiubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hCSRTh]hCSRT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "CSRT")h]h,Signature Reserved (signature == “CSRT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubh)}(h**Core System Resources Table**h]j)}(hjh]hCore System Resources Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKXhjubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDBG2h]hDBG2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "DBG2")h]h,Signature Reserved (signature == “DBG2”)}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hj!ubh)}(h**DeBuG port table 2**h]j)}(hj4h]hDeBuG port table 2}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1hhhhK^hj!ubh)}(hmLicense has changed and should be usable. Optional if used instead of earlycon= on the command line.h]hmLicense has changed and should be usable. Optional if used instead of earlycon= on the command line.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hj!ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDBGPh]hDBGP}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchjfubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh](h)}(h(Signature Reserved (signature == "DBGP")h]h,Signature Reserved (signature == “DBGP”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchj}ubh)}(h**DeBuG Port table**h]j)}(hjh]hDeBuG Port table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKehj}ubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghj}ubeh}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDSDTh]hDSDT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h&Section 5.2.11.1 (signature == "DSDT")h]h*Section 5.2.11.1 (signature == “DSDT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubh)}(h+**Differentiated System Description Table**h]j)}(hjh]h'Differentiated System Description Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKkhjubh)}(h"A DSDT is required; see also SSDT.h]h"A DSDT is required; see also SSDT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubh)}(hACPI tables contain only one DSDT but can contain one or more SSDTs, which are optional. Each SSDT can only add to the ACPI namespace, but cannot modify or replace anything in the DSDT.h]hACPI tables contain only one DSDT but can contain one or more SSDTs, which are optional. Each SSDT can only add to the ACPI namespace, but cannot modify or replace anything in the DSDT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDMARh]hDMAR}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshj,ubah}(h]h ]h"]h$]h&]uh1jhj)ubj)}(hhh](h)}(h(Signature Reserved (signature == "DMAR")h]h,Signature Reserved (signature == “DMAR”)}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjCubh)}(h**DMA Remapping table**h]j)}(hjVh]hDMA Remapping table}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hhhhKuhjCubh)}(h&x86 only table, will not be supported.h]h&x86 only table, will not be supported.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjCubeh}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hDRTMh]hDRTM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "DRTM")h]h,Signature Reserved (signature == “DRTM”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubh)}(h/**Dynamic Root of Trust for Measurement table**h]j)}(hjh]h+Dynamic Root of Trust for Measurement table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hECDTh]hECDT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.16 (signature == "ECDT")h]h(Section 5.2.16 (signature == “ECDT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h)**Embedded Controller Description Table**h]j)}(hjh]h%Embedded Controller Description Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hOptional, not currently supported, but could be used on ARM if and only if one uses the GPE_BIT field to represent an IRQ number, since there are no GPE blocks defined in hardware reduced mode. This would need to be modified in the ACPI specification.h]hOptional, not currently supported, but could be used on ARM if and only if one uses the GPE_BIT field to represent an IRQ number, since there are no GPE blocks defined in hardware reduced mode. This would need to be modified in the ACPI specification.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hEINJh]hEINJ}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj@ubah}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh](h)}(h"Section 18.6 (signature == "EINJ")h]h&Section 18.6 (signature == “EINJ”)}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWubh)}(h**Error Injection table**h]j)}(hjjh]hError Injection table}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hhhhKhjWubh)}(hX:This table is very useful for testing platform response to error conditions; it allows one to inject an error into the system as if it had actually occurred. However, this table should not be shipped with a production system; it should be dynamically loaded and executed with the ACPICA tools only during testing.h]hX:This table is very useful for testing platform response to error conditions; it allows one to inject an error into the system as if it had actually occurred. However, this table should not be shipped with a production system; it should be dynamically loaded and executed with the ACPICA tools only during testing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hERSTh]hERST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h"Section 18.5 (signature == "ERST")h]h&Section 18.5 (signature == “ERST”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h$**Error Record Serialization Table**h]j)}(hjh]h Error Record Serialization Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hXOn a platform supports RAS, this table must be supplied if it is not UEFI-based; if it is UEFI-based, this table may be supplied. When this table is not present, UEFI run time service will be utilized to save and retrieve hardware error information to and from a persistent store.h]hXOn a platform supports RAS, this table must be supplied if it is not UEFI-based; if it is UEFI-based, this table may be supplied. When this table is not present, UEFI run time service will be utilized to save and retrieve hardware error information to and from a persistent store.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hETDTh]hETDT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "ETDT")h]h,Signature Reserved (signature == “ETDT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h!**Event Timer Description Table**h]j)}(hj"h]hEvent Timer Description Table}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h&Obsolete table, will not be supported.h]h&Obsolete table, will not be supported.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFACSh]hFACS}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh](h)}(h$Section 5.2.10 (signature == "FACS")h]h(Section 5.2.10 (signature == “FACS”)}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubh)}(h#**Firmware ACPI Control Structure**h]j)}(hj~h]hFirmware ACPI Control Structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubh)}(hIt is unlikely that this table will be terribly useful. If it is provided, the Global Lock will NOT be used since it is not part of the hardware reduced profile, and only 64-bit address fields will be considered valid.h]hIt is unlikely that this table will be terribly useful. If it is provided, the Global Lock will NOT be used since it is not part of the hardware reduced profile, and only 64-bit address fields will be considered valid.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubeh}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFADTh]hFADT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h#Section 5.2.9 (signature == "FACP")h]h'Section 5.2.9 (signature == “FACP”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h4**Fixed ACPI Description Table** Required for arm64.h](j)}(h **Fixed ACPI Description Table**h]hFixed ACPI Description Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh Required for arm64.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hThe HW_REDUCED_ACPI flag must be set. All of the fields that are to be ignored when HW_REDUCED_ACPI is set are expected to be set to zero.h]hThe HW_REDUCED_ACPI flag must be set. All of the fields that are to be ignored when HW_REDUCED_ACPI is set are expected to be set to zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hYIf an FACS table is provided, the X_FIRMWARE_CTRL field is to be used, not FIRMWARE_CTRL.h]hYIf an FACS table is provided, the X_FIRMWARE_CTRL field is to be used, not FIRMWARE_CTRL.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hIf PSCI is used (as is recommended), make sure that ARM_BOOT_ARCH is filled in properly - that the PSCI_COMPLIANT flag is set and that PSCI_USE_HVC is set or unset as needed (see table 5-37).h]hIf PSCI is used (as is recommended), make sure that ARM_BOOT_ARCH is filled in properly - that the PSCI_COMPLIANT flag is set and that PSCI_USE_HVC is set or unset as needed (see table 5-37).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hWFor the DSDT that is also required, the X_DSDT field is to be used, not the DSDT field.h]hWFor the DSDT that is also required, the X_DSDT field is to be used, not the DSDT field.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hFPDTh]hFPDT}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj; ubah}(h]h ]h"]h$]h&]uh1jhj8 ubj)}(hhh](h)}(h$Section 5.2.23 (signature == "FPDT")h]h(Section 5.2.23 (signature == “FPDT”)}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjR ubh)}(h#**Firmware Performance Data Table**h]j)}(hje h]hFirmware Performance Data Table}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc ubah}(h]h ]h"]h$]h&]uh1hhhhKhjR ubh)}(h0Optional, useful for boot performance profiling.h]h0Optional, useful for boot performance profiling.}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjR ubeh}(h]h ]h"]h$]h&]uh1jhj8 ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hGTDTh]hGTDT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h$Section 5.2.24 (signature == "GTDT")h]h(Section 5.2.24 (signature == “GTDT”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h#**Generic Timer Description Table**h]j)}(hj h]hGeneric Timer Description Table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hRequired for arm64.h]hRequired for arm64.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hHESTh]hHEST}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h$Section 18.3.2 (signature == "HEST")h]h(Section 18.3.2 (signature == “HEST”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h**Hardware Error Source Table**h]j)}(hj h]hHardware Error Source Table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hX&ARM-specific error sources have been defined; please use those or the PCI types such as type 6 (AER Root Port), 7 (AER Endpoint), or 8 (AER Bridge), or use type 9 (Generic Hardware Error Source). Firmware first error handling is possible if and only if Trusted Firmware is being used on arm64.h]hX&ARM-specific error sources have been defined; please use those or the PCI types such as type 6 (AER Root Port), 7 (AER Endpoint), or 8 (AER Bridge), or use type 9 (Generic Hardware Error Source). Firmware first error handling is possible if and only if Trusted Firmware is being used on arm64.}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hgMust be supplied if RAS support is provided by the platform. It is recommended this table be supplied.h]hgMust be supplied if RAS support is provided by the platform. It is recommended this table be supplied.}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hHMATh]hHMAT}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj] ubah}(h]h ]h"]h$]h&]uh1jhjZ ubj)}(hhh](h)}(h$Section 5.2.28 (signature == "HMAT")h]h(Section 5.2.28 (signature == “HMAT”)}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjt ubh)}(h(**Heterogeneous Memory Attribute Table**h]j)}(hj h]h$Heterogeneous Memory Attribute Table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjt ubh)}(hThis table describes the memory attributes, such as memory side cache attributes and bandwidth and latency details, related to Memory Proximity Domains. The OS uses this information to optimize the system memory configuration.h]hThis table describes the memory attributes, such as memory side cache attributes and bandwidth and latency details, related to Memory Proximity Domains. The OS uses this information to optimize the system memory configuration.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjt ubeh}(h]h ]h"]h$]h&]uh1jhjZ ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hHPETh]hHPET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h(Signature Reserved (signature == "HPET")h]h,Signature Reserved (signature == “HPET”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h$**High Precision Event timer Table**h]j)}(hj h]h High Precision Event timer Table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h&x86 only table, will not be supported.h]h&x86 only table, will not be supported.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hIBFTh]hIBFT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h(Signature Reserved (signature == "IBFT")h]h,Signature Reserved (signature == “IBFT”)}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj, ubh)}(h**iSCSI Boot Firmware Table**h]j)}(hj? h]hiSCSI Boot Firmware Table}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj= ubah}(h]h ]h"]h$]h&]uh1hhhhKhj, ubh)}(h%Microsoft defined table, support TBD.h]h%Microsoft defined table, support TBD.}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj, ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hIORTh]hIORT}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjq ubah}(h]h ]h"]h$]h&]uh1jhjn ubj)}(hhh](h)}(h(Signature Reserved (signature == "IORT")h]h,Signature Reserved (signature == “IORT”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h **Input Output Remapping Table**h]j)}(hj h]hInput Output Remapping Table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hXaarm64 only table, required in order to describe IO topology, SMMUs, and GIC ITSs, and how those various components are connected together, such as identifying which components are behind which SMMUs/ITSs. This table will only be required on certain SBSA platforms (e.g., when using GICv3-ITS and an SMMU); on SBSA Level 0 platforms, it remains optional.h]hXaarm64 only table, required in order to describe IO topology, SMMUs, and GIC ITSs, and how those various components are connected together, such as identifying which components are behind which SMMUs/ITSs. This table will only be required on certain SBSA platforms (e.g., when using GICv3-ITS and an SMMU); on SBSA Level 0 platforms, it remains optional.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhjn ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hIVRSh]hIVRS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h(Signature Reserved (signature == "IVRS")h]h,Signature Reserved (signature == “IVRS”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h***I/O Virtualization Reporting Structure**h]j)}(hj h]h&I/O Virtualization Reporting Structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h/x86_64 (AMD) only table, will not be supported.h]h/x86_64 (AMD) only table, will not be supported.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hLPITh]hLPIT}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj) ubah}(h]h ]h"]h$]h&]uh1jhj& ubj)}(hhh](h)}(h(Signature Reserved (signature == "LPIT")h]h,Signature Reserved (signature == “LPIT”)}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj@ ubh)}(h**Low Power Idle Table**h]j)}(hjS h]hLow Power Idle Table}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ ubah}(h]h ]h"]h$]h&]uh1hhhhKhj@ ubh)}(hx86 only table as of ACPI 5.1; starting with ACPI 6.0, processor descriptions and power states on ARM platforms should use the DSDT and define processor container devices (_HID ACPI0010, Section 8.4, and more specifically 8.4.3 and 8.4.4).h]hx86 only table as of ACPI 5.1; starting with ACPI 6.0, processor descriptions and power states on ARM platforms should use the DSDT and define processor container devices (_HID ACPI0010, Section 8.4, and more specifically 8.4.3 and 8.4.4).}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ ubeh}(h]h ]h"]h$]h&]uh1jhj& ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMADTh]hMADT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h$Section 5.2.12 (signature == "APIC")h]h(Section 5.2.12 (signature == “APIC”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(h#**Multiple APIC Description Table**h]j)}(hj h]hMultiple APIC Description Table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hcRequired for arm64. Only the GIC interrupt controller structures should be used (types 0xA - 0xF).h]hcRequired for arm64. Only the GIC interrupt controller structures should be used (types 0xA - 0xF).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMCFGh]hMCFG}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h(Signature Reserved (signature == "MCFG")h]h,Signature Reserved (signature == “MCFG”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubh)}(h%**Memory-mapped ConFiGuration space**h]j)}(hj h]h!Memory-mapped ConFiGuration space}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(h=If the platform supports PCI/PCIe, an MCFG table is required.h]h=If the platform supports PCI/PCIe, an MCFG table is required.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMCHIh]hMCHI}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj= ubah}(h]h ]h"]h$]h&]uh1jhj: ubj)}(hhh](h)}(h(Signature Reserved (signature == "MCHI")h]h,Signature Reserved (signature == “MCHI”)}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjT ubh)}(h.**Management Controller Host Interface table**h]j)}(hjg h]h*Management Controller Host Interface table}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje ubah}(h]h ]h"]h$]h&]uh1hhhhMhjT ubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjT ubeh}(h]h ]h"]h$]h&]uh1jhj: ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMPAMh]hMPAM}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h(Signature Reserved (signature == "MPAM")h]h,Signature Reserved (signature == “MPAM”)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(h,**Memory Partitioning And Monitoring table**h]j)}(hj h]h(Memory Partitioning And Monitoring table}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hUThis table allows the OS to discover the MPAM controls implemented by the subsystems.h]hUThis table allows the OS to discover the MPAM controls implemented by the subsystems.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMPSTh]hMPST}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h$Section 5.2.21 (signature == "MPST")h]h(Section 5.2.21 (signature == “MPST”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubh)}(h**Memory Power State Table**h]j)}(hjh]hMemory Power State Table}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM"hj ubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMSCTh]hMSCT}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjQubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](h)}(h$Section 5.2.19 (signature == "MSCT")h]h(Section 5.2.19 (signature == “MSCT”)}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjhubh)}(h'**Maximum System Characteristic Table**h]j)}(hj{h]h#Maximum System Characteristic Table}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hhhhM(hjhubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hjhubeh}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMSDMh]hMSDM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "MSDM")h]h,Signature Reserved (signature == “MSDM”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjubh)}(h#**Microsoft Data Management table**h]j)}(hjh]hMicrosoft Data Management table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM.hjubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hNFITh]hNFIT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.25 (signature == "NFIT")h]h(Section 5.2.25 (signature == “NFIT”)}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj ubh)}(h#**NVDIMM Firmware Interface Table**h]j)}(hj3h]hNVDIMM Firmware Interface Table}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1hhhhM4hj ubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hOEMxh]hOEMx}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hjeubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hhh](h)}(hSignature of "OEMx" onlyh]hSignature of “OEMx” only}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj|ubh)}(h**OEM Specific Tables**h]j)}(hjh]hOEM Specific Tables}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM:hj|ubh)}(hAll tables starting with a signature of "OEM" are reserved for OEM use. Since these are not meant to be of general use but are limited to very specific end users, they are not recommended for use and are not supported by the kernel for arm64.h]hAll tables starting with a signature of “OEM” are reserved for OEM use. Since these are not meant to be of general use but are limited to very specific end users, they are not recommended for use and are not supported by the kernel for arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj|ubeh}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hPCCTh]hPCCT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h!Section 14.1 (signature == "PCCT)h]h#Section 14.1 (signature == “PCCT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubh)}(h)**Platform Communications Channel Table**h]j)}(hjh]h%Platform Communications Channel Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMChjubh)}(hRecommend for use on arm64; use of PCC is recommended when using CPPC to control performance and power for platform processors.h]hRecommend for use on arm64; use of PCC is recommended when using CPPC to control performance and power for platform processors.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hPDTTh]hPDTT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.29 (signature == "PDTT")h]h(Section 5.2.29 (signature == “PDTT”)}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj4ubh)}(h **Platform Debug Trigger Table**h]j)}(hjGh]hPlatform Debug Trigger Table}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hhhhMJhj4ubh)}(hZThis table describes PCC channels used to gather debug logs of non-architectural features.h]hZThis table describes PCC channels used to gather debug logs of non-architectural features.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj4ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hPMTTh]hPMTT}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjyubah}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh](h)}(h'Section 5.2.21.12 (signature == "PMTT")h]h+Section 5.2.21.12 (signature == “PMTT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjubh)}(h"**Platform Memory Topology Table**h]j)}(hjh]hPlatform Memory Topology Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMRhjubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjubeh}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hPPTTh]hPPTT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.30 (signature == "PPTT")h]h(Section 5.2.30 (signature == “PPTT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjubh)}(h'**Processor Properties Topology Table**h]j)}(hjh]h#Processor Properties Topology Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMXhjubh)}(h5This table provides the processor and cache topology.h]h5This table provides the processor and cache topology.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hPSDTh]hPSDT}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hj1ubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hhh](h)}(h&Section 5.2.11.3 (signature == "PSDT")h]h*Section 5.2.11.3 (signature == “PSDT”)}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjHubh)}(h'**Persistent System Description Table**h]j)}(hj[h]h#Persistent System Description Table}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hhhhM^hjHubh)}(h&Obsolete table, will not be supported.h]h&Obsolete table, will not be supported.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjHubeh}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRAS2h]hRAS2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.21 (signature == "RAS2")h]h(Section 5.2.21 (signature == “RAS2”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhjubh)}(h**RAS Features 2 table**h]j)}(hjh]hRAS Features 2 table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMdhjubh)}(hTThis table provides interfaces for the RAS capabilities implemented in the platform.h]hTThis table provides interfaces for the RAS capabilities implemented in the platform.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRASFh]hRASF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.20 (signature == "RASF")h]h(Section 5.2.20 (signature == “RASF”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjubh)}(h**RAS Feature table**h]j)}(hjh]hRAS Feature table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMkhjubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRSDPh]hRSDP}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjEubah}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](h)}(h&Section 5.2.5 (signature == "RSD PTR")h]h*Section 5.2.5 (signature == “RSD PTR”)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj\ubh)}(h#**Root System Description PoinTeR**h]j)}(hjoh]hRoot System Description PoinTeR}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1hhhhMqhj\ubh)}(hRequired for arm64.h]hRequired for arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj\ubeh}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hRSDTh]hRSDT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h#Section 5.2.7 (signature == "RSDT")h]h'Section 5.2.7 (signature == “RSDT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjubh)}(h!**Root System Description Table**h]j)}(hjh]hRoot System Description Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMwhjubh)}(hSince this table can only provide 32-bit addresses, it is deprecated on arm64, and will not be used. If provided, it will be ignored.h]hSince this table can only provide 32-bit addresses, it is deprecated on arm64, and will not be used. If provided, it will be ignored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSBSTh]hSBST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.14 (signature == "SBST")h]h(Section 5.2.14 (signature == “SBST”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjubh)}(h!**Smart Battery Subsystem Table**h]j)}(hj'h]hSmart Battery Subsystem Table}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hhhhM~hjubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSDEIh]hSDEI}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1jhjVubj)}(hhh](h)}(h(Signature Reserved (signature == "SDEI")h]h,Signature Reserved (signature == “SDEI”)}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubh)}(h0**Software Delegated Exception Interface table**h]j)}(hjh]h,Software Delegated Exception Interface table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubh)}(h9This table advertises the presence of the SDEI interface.h]h9This table advertises the presence of the SDEI interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubeh}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSLICh]hSLIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "SLIC")h]h,Signature Reserved (signature == “SLIC”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h**Software LIcensing table**h]j)}(hjh]hSoftware LIcensing table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSLITh]hSLIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h$Section 5.2.17 (signature == "SLIT")h]h(Section 5.2.17 (signature == “SLIT”)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubh)}(h.**System Locality distance Information Table**h]j)}(hj;h]h*System Locality distance Information Table}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubh)}(h3Optional in general, but required for NUMA systems.h]h3Optional in general, but required for NUMA systems.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSPCRh]hSPCR}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjmubah}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh](h)}(h(Signature Reserved (signature == "SPCR")h]h,Signature Reserved (signature == “SPCR”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h)**Serial Port Console Redirection table**h]j)}(hjh]h%Serial Port Console Redirection table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hRequired for arm64.h]hRequired for arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSPMIh]hSPMI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "SPMI")h]h,Signature Reserved (signature == “SPMI”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h.**Server Platform Management Interface table**h]j)}(hjh]h*Server Platform Management Interface table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h"Optional, not currently supported.h]h"Optional, not currently supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSRATh]hSRAT}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh](h)}(h$Section 5.2.16 (signature == "SRAT")h]h(Section 5.2.16 (signature == “SRAT”)}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubh)}(h"**System Resource Affinity Table**h]j)}(hjOh]hSystem Resource Affinity Table}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubh)}(hqOptional, but if used, only the GICC Affinity structures are read. To support arm64 NUMA, this table is required.h]hqOptional, but if used, only the GICC Affinity structures are read. To support arm64 NUMA, this table is required.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubeh}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSSDTh]hSSDT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh](h)}(h&Section 5.2.11.2 (signature == "SSDT")h]h*Section 5.2.11.2 (signature == “SSDT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h&**Secondary System Description Table**h]j)}(hjh]h"Secondary System Description Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hThese tables are a continuation of the DSDT; these are recommended for use with devices that can be added to a running system, but can also serve the purpose of dividing up device descriptions into more manageable pieces.h]hThese tables are a continuation of the DSDT; these are recommended for use with devices that can be added to a running system, but can also serve the purpose of dividing up device descriptions into more manageable pieces.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hAn SSDT can only ADD to the ACPI namespace. It cannot modify or replace existing device descriptions already in the namespace.h]hAn SSDT can only ADD to the ACPI namespace. It cannot modify or replace existing device descriptions already in the namespace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hiThese tables are optional, however. ACPI tables should contain only one DSDT but can contain many SSDTs.h]hiThese tables are optional, however. ACPI tables should contain only one DSDT but can contain many SSDTs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hSTAOh]hSTAO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "STAO")h]h,Signature Reserved (signature == “STAO”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h**_STA Override table**h]j)}(hj#h]h_STA Override table}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(haOptional, but only necessary in virtualized environments in order to hide devices from guest OSs.h]haOptional, but only necessary in virtualized environments in order to hide devices from guest OSs.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hTCPAh]hTCPA}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhjRubj)}(hhh](h)}(h(Signature Reserved (signature == "TCPA")h]h,Signature Reserved (signature == “TCPA”)}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjlubh)}(h-**Trusted Computing Platform Alliance table**h]j)}(hjh]h)Trusted Computing Platform Alliance table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hhhhMhjlubh)}(hYOptional, not currently supported, and may need changes to fully interoperate with arm64.h]hYOptional, not currently supported, and may need changes to fully interoperate with arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjlubeh}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hTPM2h]hTPM2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "TPM2")h]h,Signature Reserved (signature == “TPM2”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h#**Trusted Platform Module 2 table**h]j)}(hjh]hTrusted Platform Module 2 table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hYOptional, not currently supported, and may need changes to fully interoperate with arm64.h]hYOptional, not currently supported, and may need changes to fully interoperate with arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hUEFIh]hUEFI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](h)}(h(Signature Reserved (signature == "UEFI")h]h,Signature Reserved (signature == “UEFI”)}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubh)}(h**UEFI ACPI data table**h]j)}(hj7h]hUEFI ACPI data table}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubh)}(hLOptional, not currently supported. No known use case for arm64, at present.h]hLOptional, not currently supported. No known use case for arm64, at present.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hWAETh]hWAET}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh](h)}(h(Signature Reserved (signature == "WAET")h]h,Signature Reserved (signature == “WAET”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h'**Windows ACPI Emulated devices Table**h]j)}(hjh]h#Windows ACPI Emulated devices Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hWDATh]hWDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "WDAT")h]h,Signature Reserved (signature == “WDAT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h**Watch Dog Action Table**h]j)}(hjh]hWatch Dog Action Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hWDRTh]hWDRT}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "WDRT")h]h,Signature Reserved (signature == “WDRT”)}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubh)}(h**Watch Dog Resource Table**h]j)}(hjKh]hWatch Dog Resource Table}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hWPBTh]hWPBT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj}ubah}(h]h ]h"]h$]h&]uh1jhjzubj)}(hhh](h)}(h(Signature Reserved (signature == "WPBT")h]h,Signature Reserved (signature == “WPBT”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h!**Windows Platform Binary Table**h]j)}(hjh]hWindows Platform Binary Table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h,Microsoft only table, will not be supported.h]h,Microsoft only table, will not be supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hXENVh]hXENV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h(Signature Reserved (signature == "XENV")h]h,Signature Reserved (signature == “XENV”)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h**Xen project table**h]j)}(hjh]hXen project table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h&Optional, used only by Xen at present.h]h&Optional, used only by Xen at present.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hXSDTh]hXSDT}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh](h)}(h#Section 5.2.8 (signature == "XSDT")h]h'Section 5.2.8 (signature == “XSDT”)}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLubh)}(h%**eXtended System Description Table**h]j)}(hj_h]h!eXtended System Description Table}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1hhhhMhjLubh)}(hRequired for arm64.h]hRequired for arm64.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLubeh}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]colsKuh1jchj`ubah}(h]h ]h"]h$]h&]uh1j^hhhhhhhNubh)}(hhh](h)}(h ACPI Objectsh]h ACPI Objects}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hXThe expectations on individual ACPI objects that are likely to be used are shown in the list that follows; any object not explicitly mentioned below should be used as needed for a particular platform or particular subsystem, such as power management or PCI.h]hXThe expectations on individual ACPI objects that are likely to be used are shown in the list that follows; any object not explicitly mentioned below should be used as needed for a particular platform or particular subsystem, such as power management or PCI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj_)}(hhh]jd)}(hhh](ji)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhhjubji)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhhjubji)}(hhh]h}(h]h ]h"]h$]h&]colwidthK8uh1jhhjubj)}(hhh]j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSectionh]hSection}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hUsage for ARMv8 Linuxh]hUsage for ARMv8 Linux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h_CCAh]h_CCA}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]h)}(h6.2.17h]h6.2.17}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh](h)}(hXRThis method must be defined for all bus masters on arm64 - there are no assumptions made about whether such devices are cache coherent or not. The _CCA value is inherited by all descendants of these devices so it does not need to be repeated. Without _CCA on arm64, the kernel does not know what to do about setting up DMA for the device.h]hXRThis method must be defined for all bus masters on arm64 - there are no assumptions made about whether such devices are cache coherent or not. The _CCA value is inherited by all descendants of these devices so it does not need to be repeated. Without _CCA on arm64, the kernel does not know what to do about setting up DMA for the device.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjoubh)}(hX.NB: this method provides default cache coherency attributes; the presence of an SMMU can be used to modify that, however. For example, a master could default to non-coherent, but be made coherent with the appropriate SMMU configuration (see Table 17 of the IORT specification, ARM Document DEN 0049B).h]hX.NB: this method provides default cache coherency attributes; the presence of an SMMU can be used to modify that, however. For example, a master could default to non-coherent, but be made coherent with the appropriate SMMU configuration (see Table 17 of the IORT specification, ARM Document DEN 0049B).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjoubeh}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_CIDh]h_CID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6.1.2h]h6.1.2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hUse as needed, see also _HID.h]hUse as needed, see also _HID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_CLSh]h_CLS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6.1.3h]h6.1.3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hUse as needed, see also _HID.h]hUse as needed, see also _HID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_CPCh]h_CPC}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh]h)}(h8.4.7.1h]h8.4.7.1}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh]h)}(hHUse as needed, power management specific. CPPC is recommended on arm64.h]hHUse as needed, power management specific. CPPC is recommended on arm64.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjgubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_CRSh]h_CRS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6.2.2h]h6.2.2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRequired on arm64.h]hRequired on arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_CSDh]h_CSD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8.4.2.2h]h8.4.2.2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2Use as needed, used only in conjunction with _CST.h]h2Use as needed, used only in conjunction with _CST.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_CSTh]h_CST}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h8.4.2.1h]h8.4.2.1}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hBLow power idle states (8.4.4) are recommended instead of C-states.h]hBLow power idle states (8.4.4) are recommended instead of C-states.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_DDNh]h_DDN}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjqubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(h6.1.4h]h6.1.4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(hThis field can be used for a device name. However, it is meant for DOS device names (e.g., COM1), so be careful of its use across OSes.h]hThis field can be used for a device name. However, it is meant for DOS device names (e.g., COM1), so be careful of its use across OSes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_DSDh]h_DSD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6.2.5h]h6.2.5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(hTo be used with caution. If this object is used, try to use it within the constraints already defined by the Device Properties UUID. Only in rare circumstances should it be necessary to create a new _DSD UUID.h]hTo be used with caution. If this object is used, try to use it within the constraints already defined by the Device Properties UUID. Only in rare circumstances should it be necessary to create a new _DSD UUID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubh)}(hXIn either case, submit the _DSD definition along with any driver patches for discussion, especially when device properties are used. A driver will not be considered complete without a corresponding _DSD description. Once approved by kernel maintainers, the UUID or device properties must then be registered with the UEFI Forum; this may cause some iteration as more than one OS will be registering entries.h]hXIn either case, submit the _DSD definition along with any driver patches for discussion, especially when device properties are used. A driver will not be considered complete without a corresponding _DSD description. Once approved by kernel maintainers, the UUID or device properties must then be registered with the UEFI Forum; this may cause some iteration as more than one OS will be registering entries.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_DSMh]h_DSM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h9.1.1h]h9.1.1}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj2ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hDo not use this method. It is not standardized, the return values are not well documented, and it is currently a frequent source of error.h]hDo not use this method. It is not standardized, the return values are not well documented, and it is currently a frequent source of error.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjIubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_GLh]h_GL}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjiubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]h)}(h5.7.1h]h5.7.1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]h)}(hbThis object is not to be used in hardware reduced mode, and therefore should not be used on arm64.h]hbThis object is not to be used in hardware reduced mode, and therefore should not be used on arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_GLKh]h_GLK}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6.5.7h]h6.5.7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hThis object requires a global lock be defined; there is no global lock on arm64 since it runs in hardware reduced mode. Hence, do not use this object on arm64.h]hThis object requires a global lock be defined; there is no global lock on arm64 since it runs in hardware reduced mode. Hence, do not use this object on arm64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_GPEh]h_GPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h5.3.1h]h5.3.1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hhjSubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(h6.1.5h]h6.1.5}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjjubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(h[This is the primary object to use in device probing, though _CID and _CLS may also be used.h]h[This is the primary object to use in device probing, though _CID and _CLS may also be used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_INIh]h_INI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6.5.1h]h6.5.1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hNot required, but can be useful in setting up devices when UEFI leaves them in a state that may not be what the driver expects before it starts probing.h]hNot required, but can be useful in setting up devices when UEFI leaves them in a state that may not be what the driver expects before it starts probing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_LPIh]h_LPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8.4.4.3h]h8.4.4.3}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hXRecommended for use with processor definitions (_HID ACPI0010) on arm64. See also _RDI.h]hXRecommended for use with processor definitions (_HID ACPI0010) on arm64. See also _RDI.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_MLSh]h_MLS}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj=ubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h)}(h6.1.7h]h6.1.7}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjTubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h)}(h3Highly recommended for use in internationalization.h]h3Highly recommended for use in internationalization.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjkubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_OFFh]h_OFF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h7.2.2h]h7.2.2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTIt is recommended to define this method for any device that can be turned on or off.h]hTIt is recommended to define this method for any device that can be turned on or off.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_ONh]h_ON}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h7.2.3h]h7.2.3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTIt is recommended to define this method for any device that can be turned on or off.h]hTIt is recommended to define this method for any device that can be turned on or off.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_OSh]h_OS}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhj' ubah}(h]h ]h"]h$]h&]uh1jhj$ ubj)}(hhh]h)}(h5.7.3h]h5.7.3}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhj> ubah}(h]h ]h"]h$]h&]uh1jhj$ ubj)}(hhh]h)}(hThis method will return "Linux" by default (this is the value of the macro ACPI_OS_NAME on Linux). The command line parameter acpi_os= can be used to set it to some other value.h]hThis method will return “Linux” by default (this is the value of the macro ACPI_OS_NAME on Linux). The command line parameter acpi_os= can be used to set it to some other value.}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjU ubah}(h]h ]h"]h$]h&]uh1jhj$ ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_OSCh]h_OSC}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhju ubah}(h]h ]h"]h$]h&]uh1jhjr ubj)}(hhh]h)}(h6.2.11h]h6.2.11}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhj ubah}(h]h ]h"]h$]h&]uh1jhjr ubj)}(hhh]h)}(hXFThis method can be a global method in ACPI (i.e., \_SB._OSC), or it may be associated with a specific device (e.g., \_SB.DEV0._OSC), or both. When used as a global method, only capabilities published in the ACPI specification are allowed. When used as a device-specific method, the process described for using _DSD MUST be used to create an _OSC definition; out-of-process use of _OSC is not allowed. That is, submit the device-specific _OSC usage description as part of the kernel driver submission, get it approved by the kernel community, then register it with the UEFI Forum.h]hXFThis method can be a global method in ACPI (i.e., _SB._OSC), or it may be associated with a specific device (e.g., _SB.DEV0._OSC), or both. When used as a global method, only capabilities published in the ACPI specification are allowed. When used as a device-specific method, the process described for using _DSD MUST be used to create an _OSC definition; out-of-process use of _OSC is not allowed. That is, submit the device-specific _OSC usage description as part of the kernel driver submission, get it approved by the kernel community, then register it with the UEFI Forum.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhj ubah}(h]h ]h"]h$]h&]uh1jhjr ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_OSIh]h_OSI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h5.7.2h]h5.7.2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hDeprecated on ARM64. As far as ACPI firmware is concerned, _OSI is not to be used to determine what sort of system is being used or what functionality is provided. The _OSC method is to be used instead.h]hDeprecated on ARM64. As far as ACPI firmware is concerned, _OSI is not to be used to determine what sort of system is being used or what functionality is provided. The _OSC method is to be used instead.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_PDCh]h_PDC}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h8.4.1h]h8.4.1}(hj+!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj(!ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h Deprecated, do not use on arm64.h]h Deprecated, do not use on arm64.}(hjB!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj?!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_PICh]h_PIC}(hjb!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj_!ubah}(h]h ]h"]h$]h&]uh1jhj\!ubj)}(hhh]h)}(h5.8.1h]h5.8.1}(hjy!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjv!ubah}(h]h ]h"]h$]h&]uh1jhj\!ubj)}(hhh]h)}(hTThe method should not be used. On arm64, the only interrupt model available is GIC.h]hTThe method should not be used. On arm64, the only interrupt model available is GIC.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj!ubah}(h]h ]h"]h$]h&]uh1jhj\!ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_PRh]h_PR}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h5.3.1h]h5.3.1}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(hMThis namespace is for x86 use only on legacy systems. Do not use it on arm64.h]hMThis namespace is for x86 use only on legacy systems. Do not use it on arm64.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_PRTh]h_PRT}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h6.2.13h]h6.2.13}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj"ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h;Required as part of the definition of all PCI root devices.h]h;Required as part of the definition of all PCI root devices.}(hj,"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj)"ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_PRxh]h_PRx}(hjL"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjI"ubah}(h]h ]h"]h$]h&]uh1jhjF"ubj)}(hhh]h)}(h7.3.8-11h]h7.3.8-11}(hjc"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhj`"ubah}(h]h ]h"]h$]h&]uh1jhjF"ubj)}(hhh]h)}(hYUse as needed; power management specific. If _PR0 is defined, _PR3 must also be defined.h]hYUse as needed; power management specific. If _PR0 is defined, _PR3 must also be defined.}(hjz"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjw"ubah}(h]h ]h"]h$]h&]uh1jhjF"ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_PSxh]h_PSx}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(h7.3.2-5h]h7.3.2-5}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(hUse as needed; power management specific. If _PS0 is defined, _PS3 must also be defined. If clocks or regulators need adjusting to be consistent with power usage, change them in these methods.h]hUse as needed; power management specific. If _PS0 is defined, _PS3 must also be defined. If clocks or regulators need adjusting to be consistent with power usage, change them in these methods.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_RDIh]h_RDI}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(h8.4.4.4h]h8.4.4.4}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(h|Recommended for use with processor definitions (_HID ACPI0010) on arm64. This should only be used in conjunction with _LPI.h]h|Recommended for use with processor definitions (_HID ACPI0010) on arm64. This should only be used in conjunction with _LPI.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj#ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_REVh]h_REV}(hj6#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hj3#ubah}(h]h ]h"]h$]h&]uh1jhj0#ubj)}(hhh]h)}(h5.7.4h]h5.7.4}(hjM#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjJ#ubah}(h]h ]h"]h$]h&]uh1jhj0#ubj)}(hhh]h)}(h4Always returns the latest version of ACPI supported.h]h4Always returns the latest version of ACPI supported.}(hjd#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hja#ubah}(h]h ]h"]h$]h&]uh1jhj0#ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h\_SBh]h_SB}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj~#ubj)}(hhh]h)}(h5.3.1h]h5.3.1}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj~#ubj)}(hhh]h)}(hARequired on arm64; all devices must be defined in this namespace.h]hARequired on arm64; all devices must be defined in this namespace.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj~#ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_SLIh]h_SLI}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(h6.2.15h]h6.2.15}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(h-Use is recommended when SLIT table is in use.h]h-Use is recommended when SLIT table is in use.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_STAh]h_STA}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubj)}(hhh]h)}(h 6.3.7, 7.2.4h]h 6.3.7, 7.2.4}(hj7$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4$ubah}(h]h ]h"]h$]h&]uh1jhj$ubj)}(hhh]h)}(hIt is recommended to define this method for any device that can be turned on or off. See also the STAO table that provides overrides to hide devices in virtualized environments.h]hIt is recommended to define this method for any device that can be turned on or off. See also the STAO table that provides overrides to hide devices in virtualized environments.}(hjN$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjK$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_SRSh]h_SRS}(hjn$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjk$ubah}(h]h ]h"]h$]h&]uh1jhjh$ubj)}(hhh]h)}(h6.2.16h]h6.2.16}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhjh$ubj)}(hhh]h)}(hUse as needed; see also _PRS.h]hUse as needed; see also _PRS.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhjh$ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_STRh]h_STR}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubj)}(hhh]h)}(h6.1.10h]h6.1.10}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubj)}(hhh]h)}(hWRecommended for conveying device names to end users; this is preferred over using _DDN.h]hWRecommended for conveying device names to end users; this is preferred over using _DDN.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_SUBh]h_SUB}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h6.1.9h]h6.1.9}(hj!%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h*Use as needed; _HID or _CID are preferred.h]h*Use as needed; _HID or _CID are preferred.}(hj8%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_SUNh]h_SUN}(hjX%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU%ubah}(h]h ]h"]h$]h&]uh1jhjR%ubj)}(hhh]h)}(h6.1.11h]h6.1.11}(hjo%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjl%ubah}(h]h ]h"]h$]h&]uh1jhjR%ubj)}(hhh]h)}(hUse as needed, but recommended.h]hUse as needed, but recommended.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhjR%ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_SWSh]h_SWS}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h7.4.3h]h7.4.3}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(hbUse as needed; power management specific; this may require specification changes for use on arm64.h]hbUse as needed; power management specific; this may require specification changes for use on arm64.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh](j)}(hhh]h)}(h_UIDh]h_UID}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h6.1.12h]h6.1.12}(hj &hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(hWRecommended for distinguishing devices of the same class; define it if at all possible.h]hWRecommended for distinguishing devices of the same class; define it if at all possible.}(hj"&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jchjubah}(h]h ]h"]h$]h&]uh1j^hjhhhhhNubeh}(h] acpi-objectsah ]h"] acpi objectsah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hACPI Event Modelh]hACPI Event Model}(hjZ&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjW&hhhhhMubh)}(hDo not use GPE block devices; these are not supported in the hardware reduced profile used by arm64. Since there are no GPE blocks defined for use on ARM platforms, ACPI events must be signaled differently.h]hDo not use GPE block devices; these are not supported in the hardware reduced profile used by arm64. Since there are no GPE blocks defined for use on ARM platforms, ACPI events must be signaled differently.}(hjh&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjW&hhubh)}(hXlThere are two options: GPIO-signaled interrupts (Section 5.6.5), and interrupt-signaled events (Section 5.6.9). Interrupt-signaled events are a new feature in the ACPI 6.1 specification. Either - or both - can be used on a given platform, and which to use may be dependent of limitations in any given SoC. If possible, interrupt-signaled events are recommended.h]hXlThere are two options: GPIO-signaled interrupts (Section 5.6.5), and interrupt-signaled events (Section 5.6.9). Interrupt-signaled events are a new feature in the ACPI 6.1 specification. Either - or both - can be used on a given platform, and which to use may be dependent of limitations in any given SoC. If possible, interrupt-signaled events are recommended.}(hjv&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjW&hhubeh}(h]acpi-event-modelah ]h"]acpi event modelah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hACPI Processor Controlh]hACPI Processor Control}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhMubh)}(hX"Section 8 of the ACPI specification changed significantly in version 6.0. Processors should now be defined as Device objects with _HID ACPI0007; do not use the deprecated Processor statement in ASL. All multiprocessor systems should also define a hierarchy of processors, done with Processor Container Devices (see Section 8.4.3.1, _HID ACPI0010); do not use processor aggregator devices (Section 8.5) to describe processor topology. Section 8.4 of the specification describes the semantics of these object definitions and how they interrelate.h]hX"Section 8 of the ACPI specification changed significantly in version 6.0. Processors should now be defined as Device objects with _HID ACPI0007; do not use the deprecated Processor statement in ASL. All multiprocessor systems should also define a hierarchy of processors, done with Processor Container Devices (see Section 8.4.3.1, _HID ACPI0010); do not use processor aggregator devices (Section 8.5) to describe processor topology. Section 8.4 of the specification describes the semantics of these object definitions and how they interrelate.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hXYMost importantly, the processor hierarchy defined also defines the low power idle states that are available to the platform, along with the rules for determining which processors can be turned on or off and the circumstances that control that. Without this information, the processors will run in whatever power state they were left in by UEFI.h]hXYMost importantly, the processor hierarchy defined also defines the low power idle states that are available to the platform, along with the rules for determining which processors can be turned on or off and the circumstances that control that. Without this information, the processors will run in whatever power state they were left in by UEFI.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hNote too, that the processor Device objects defined and the entries in the MADT for GICs are expected to be in synchronization. The _UID of the Device object must correspond to processor IDs used in the MADT.h]hNote too, that the processor Device objects defined and the entries in the MADT for GICs are expected to be in synchronization. The _UID of the Device object must correspond to processor IDs used in the MADT.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hIt is recommended that CPPC (8.4.5) be used as the primary model for processor performance control on arm64. C-states and P-states may become available at some point in the future, but most current design work appears to favor CPPC.h]hIt is recommended that CPPC (8.4.5) be used as the primary model for processor performance control on arm64. C-states and P-states may become available at some point in the future, but most current design work appears to favor CPPC.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hX3Further, it is essential that the ARMv8 SoC provide a fully functional implementation of PSCI; this will be the only mechanism supported by ACPI to control CPU power state. Booting of secondary CPUs using the ACPI parking protocol is possible, but discouraged, since only PSCI is supported for ARM servers.h]hX3Further, it is essential that the ARMv8 SoC provide a fully functional implementation of PSCI; this will be the only mechanism supported by ACPI to control CPU power state. Booting of secondary CPUs using the ACPI parking protocol is possible, but discouraged, since only PSCI is supported for ARM servers.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubeh}(h]acpi-processor-controlah ]h"]acpi processor controlah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h"ACPI System Address Map Interfacesh]h"ACPI System Address Map Interfaces}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhMubh)}(hX&In Section 15 of the ACPI specification, several methods are mentioned as possible mechanisms for conveying memory resource information to the kernel. For arm64, we will only support UEFI for booting with ACPI, hence the UEFI GetMemoryMap() boot service is the only mechanism that will be used.h]hX&In Section 15 of the ACPI specification, several methods are mentioned as possible mechanisms for conveying memory resource information to the kernel. For arm64, we will only support UEFI for booting with ACPI, hence the UEFI GetMemoryMap() boot service is the only mechanism that will be used.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubeh}(h]"acpi-system-address-map-interfacesah ]h"]"acpi system address map interfacesah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h%ACPI Platform Error Interfaces (APEI)h]h%ACPI Platform Error Interfaces (APEI)}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhMubh)}(h.The APEI tables supported are described above.h]h.The APEI tables supported are described above.}(hj#'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubh)}(hX@APEI requires the equivalent of an SCI and an NMI on ARMv8. The SCI is used to notify the OSPM of errors that have occurred but can be corrected and the system can continue correct operation, even if possibly degraded. The NMI is used to indicate fatal errors that cannot be corrected, and require immediate attention.h]hX@APEI requires the equivalent of an SCI and an NMI on ARMv8. The SCI is used to notify the OSPM of errors that have occurred but can be corrected and the system can continue correct operation, even if possibly degraded. The NMI is used to indicate fatal errors that cannot be corrected, and require immediate attention.}(hj1'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubh)}(hX"Since there is no direct equivalent of the x86 SCI or NMI, arm64 handles these slightly differently. The SCI is handled as a high priority interrupt; given that these are corrected (or correctable) errors being reported, this is sufficient. The NMI is emulated as the highest priority interrupt possible. This implies some caution must be used since there could be interrupts at higher privilege levels or even interrupts at the same priority as the emulated NMI. In Linux, this should not be the case but one should be aware it could happen.h]hX"Since there is no direct equivalent of the x86 SCI or NMI, arm64 handles these slightly differently. The SCI is handled as a high priority interrupt; given that these are corrected (or correctable) errors being reported, this is sufficient. The NMI is emulated as the highest priority interrupt possible. This implies some caution must be used since there could be interrupts at higher privilege levels or even interrupts at the same priority as the emulated NMI. In Linux, this should not be the case but one should be aware it could happen.}(hj?'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubeh}(h]#acpi-platform-error-interfaces-apeiah ]h"]%acpi platform error interfaces (apei)ah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h#ACPI Objects Not Supported on ARM64h]h#ACPI Objects Not Supported on ARM64}(hjX'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU'hhhhhMubh)}(hXWhile this may change in the future, there are several classes of objects that can be defined, but are not currently of general interest to ARM servers. Some of these objects have x86 equivalents, and may actually make sense in ARM servers. However, there is either no hardware available at present, or there may not even be a non-ARM implementation yet. Hence, they are not currently supported.h]hXWhile this may change in the future, there are several classes of objects that can be defined, but are not currently of general interest to ARM servers. Some of these objects have x86 equivalents, and may actually make sense in ARM servers. However, there is either no hardware available at present, or there may not even be a non-ARM implementation yet. Hence, they are not currently supported.}(hjf'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU'hhubh)}(h3The following classes of objects are not supported:h]h3The following classes of objects are not supported:}(hjt'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU'hhubh)}(hXd- Section 9.2: ambient light sensor devices - Section 9.3: battery devices - Section 9.4: lids (e.g., laptop lids) - Section 9.8.2: IDE controllers - Section 9.9: floppy controllers - Section 9.10: GPE block devices - Section 9.15: PC/AT RTC/CMOS devices - Section 9.16: user presence detection devices - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT - Section 9.18: time and alarm devices (see 9.15) - Section 10: power source and power meter devices - Section 11: thermal management - Section 12: embedded controllers interface - Section 13: SMBus interfaces h]h)}(hhh](h)}(h*Section 9.2: ambient light sensor devices h]h)}(h)Section 9.2: ambient light sensor devicesh]h)Section 9.2: ambient light sensor devices}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(hSection 9.3: battery devices h]h)}(hSection 9.3: battery devicesh]hSection 9.3: battery devices}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h&Section 9.4: lids (e.g., laptop lids) h]h)}(h%Section 9.4: lids (e.g., laptop lids)h]h%Section 9.4: lids (e.g., laptop lids)}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(hSection 9.8.2: IDE controllers h]h)}(hSection 9.8.2: IDE controllersh]hSection 9.8.2: IDE controllers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h Section 9.9: floppy controllers h]h)}(hSection 9.9: floppy controllersh]hSection 9.9: floppy controllers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h Section 9.10: GPE block devices h]h)}(hSection 9.10: GPE block devicesh]hSection 9.10: GPE block devices}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h%Section 9.15: PC/AT RTC/CMOS devices h]h)}(h$Section 9.15: PC/AT RTC/CMOS devicesh]h$Section 9.15: PC/AT RTC/CMOS devices}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h.Section 9.16: user presence detection devices h]h)}(h-Section 9.16: user presence detection devicesh]h-Section 9.16: user presence detection devices}(hj5(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(hESection 9.17: I/O APIC devices; all GICs must be enumerable via MADT h]h)}(hDSection 9.17: I/O APIC devices; all GICs must be enumerable via MADTh]hDSection 9.17: I/O APIC devices; all GICs must be enumerable via MADT}(hjM(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h0Section 9.18: time and alarm devices (see 9.15) h]h)}(h/Section 9.18: time and alarm devices (see 9.15)h]h/Section 9.18: time and alarm devices (see 9.15)}(hje(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhja(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h1Section 10: power source and power meter devices h]h)}(h0Section 10: power source and power meter devicesh]h0Section 10: power source and power meter devices}(hj}(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjy(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(hSection 11: thermal management h]h)}(hSection 11: thermal managementh]hSection 11: thermal management}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(h+Section 12: embedded controllers interface h]h)}(h*Section 12: embedded controllers interfaceh]h*Section 12: embedded controllers interface}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1hhj'ubh)}(hSection 13: SMBus interfaces h]h)}(hSection 13: SMBus interfacesh]hSection 13: SMBus interfaces}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]jVjWuh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhhhMhjU'hhubh)}(hCThis also means that there is no support for the following objects:h]hCThis also means that there is no support for the following objects:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU'hhubj_)}(hhh]jd)}(hhh](ji)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhhj(ubji)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhhj(ubji)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhhj(ubji)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhhj(ubj)}(hhh]j)}(hhh](j)}(hhh]h)}(hNameh]hName}(hj*)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj')ubah}(h]h ]h"]h$]h&]uh1jhj$)ubj)}(hhh]h)}(hSectionh]hSection}(hjA)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>)ubah}(h]h ]h"]h$]h&]uh1jhj$)ubj)}(hhh]h)}(hNameh]hName}(hjX)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU)ubah}(h]h ]h"]h$]h&]uh1jhj$)ubj)}(hhh]h)}(hSectionh]hSection}(hjo)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjl)ubah}(h]h ]h"]h$]h&]uh1jhj$)ubeh}(h]h ]h"]h$]h&]uh1jhj!)ubah}(h]h ]h"]h$]h&]uh1j~hj(ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h_ALCh]h_ALC}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubj)}(hhh]h)}(h9.3.4h]h9.3.4}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubj)}(hhh]h)}(h_FDMh]h_FDM}(hj)hhhNhNubah}(h]h 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