€•ç¨Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ$/translations/zh_CN/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ$/translations/zh_TW/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ$/translations/it_IT/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ$/translations/ja_JP/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ$/translations/ko_KR/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ$/translations/pt_BR/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ$/translations/sp_SP/arch/arm/pxa/mfp”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ.MFP Configuration for PXA2xx/PXA3xx Processors”h]”hŒ.MFP Configuration for PXA2xx/PXA3xx Processors”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³Œ>/var/lib/git/docbuild/linux/Documentation/arch/arm/pxa/mfp.rst”h´KubhŒ block_quote”“”)”}”(hŒ"Eric Miao ”h]”hŒ paragraph”“”)”}”(hŒ!Eric Miao ”h]”(hŒ Eric Miao <”…””}”(hhÓh²hh³Nh´NubhŒ reference”“”)”}”(hŒeric.miao@marvell.com”h]”hŒeric.miao@marvell.com”…””}”(hhÝh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:eric.miao@marvell.com”uh1hÛhhÓubhŒ>”…””}”(hhÓh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KhhÍubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhÒ)”}”(hŒÓMFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and later PXA series processors. This document describes the existing MFP API, and how board/platform driver authors could make use of it.”h]”hŒÓMFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and later PXA series processors. This document describes the existing MFP API, and how board/platform driver authors could make use of it.”…””}”(hhýh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Khh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒ Basic Concept”h]”hŒ Basic Concept”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj h²hh³hÊh´K ubhÒ)”}”(hX¬Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP mechanism is introduced from PXA3xx to completely move the pin-mux functions out of the GPIO controller. In addition to pin-mux configurations, the MFP also controls the low power state, driving strength, pull-up/down and event detection of each pin. Below is a diagram of internal connections between the MFP logic and the remaining SoC peripherals::”h]”hX«Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP mechanism is introduced from PXA3xx to completely move the pin-mux functions out of the GPIO controller. In addition to pin-mux configurations, the MFP also controls the low power state, driving strength, pull-up/down and event detection of each pin. Below is a diagram of internal connections between the MFP logic and the remaining SoC peripherals:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Khj h²hubhŒ literal_block”“”)”}”(hX“+--------+ | |--(GPIO19)--+ | GPIO | | | |--(GPIO...) | +--------+ | | +---------+ +--------+ +------>| | | PWM2 |--(PWM_OUT)-------->| MFP | +--------+ +------>| |-------> to external PAD | +---->| | +--------+ | | +-->| | | SSP2 |---(TXD)----+ | | +---------+ +--------+ | | | | +--------+ | | | Keypad |--(MKOUT4)----+ | +--------+ | | +--------+ | | UART2 |---(TXD)--------+ +--------+”h]”hX“+--------+ | |--(GPIO19)--+ | GPIO | | | |--(GPIO...) | +--------+ | | +---------+ +--------+ +------>| | | PWM2 |--(PWM_OUT)-------->| MFP | +--------+ +------>| |-------> to external PAD | +---->| | +--------+ | | +-->| | | SSP2 |---(TXD)----+ | | +---------+ +--------+ | | | | +--------+ | | | Keypad |--(MKOUT4)----+ | +--------+ | | +--------+ | | UART2 |---(TXD)--------+ +--------+”…””}”hj,sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1j*h³hÊh´Khj h²hubhÒ)”}”(hŒÃNOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily mean it's dedicated for GPIO19, only as a hint that internally this pin can be routed from GPIO19 of the GPIO controller.”h]”hŒÇNOTE: the external pad is named as MFP_PIN_GPIO19, it doesn’t necessarily mean it’s dedicated for GPIO19, only as a hint that internally this pin can be routed from GPIO19 of the GPIO controller.”…””}”(hj<h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K+hj h²hubhÒ)”}”(hŒ‚To better understand the change from PXA25x/PXA27x GPIO alternate function to this new MFP mechanism, here are several key points:”h]”hŒ‚To better understand the change from PXA25x/PXA27x GPIO alternate function to this new MFP mechanism, here are several key points:”…””}”(hjJh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K/hj h²hubhÌ)”}”(hX…1. GPIO controller on PXA3xx is now a dedicated controller, same as other internal controllers like PWM, SSP and UART, with 128 internal signals which can be routed to external through one or more MFPs (e.g. GPIO<0> can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2, see arch/arm/mach-pxa/mfp-pxa300.h) 2. Alternate function configuration is removed from this GPIO controller, the remaining functions are pure GPIO-specific, i.e. - GPIO signal level control - GPIO direction control - GPIO level change detection 3. Low power state for each pin is now controlled by MFP, this means the PGSRx registers on PXA2xx are now useless on PXA3xx 4. Wakeup detection is now controlled by MFP, PWER does not control the wakeup from GPIO(s) any more, depending on the sleeping state, ADxER (as defined in pxa3xx-regs.h) controls the wakeup from MFP ”h]”hŒenumerated_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hX@GPIO controller on PXA3xx is now a dedicated controller, same as other internal controllers like PWM, SSP and UART, with 128 internal signals which can be routed to external through one or more MFPs (e.g. GPIO<0> can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2, see arch/arm/mach-pxa/mfp-pxa300.h) ”h]”hÒ)”}”(hX?GPIO controller on PXA3xx is now a dedicated controller, same as other internal controllers like PWM, SSP and UART, with 128 internal signals which can be routed to external through one or more MFPs (e.g. GPIO<0> can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2, see arch/arm/mach-pxa/mfp-pxa300.h)”h]”hX?GPIO controller on PXA3xx is now a dedicated controller, same as other internal controllers like PWM, SSP and UART, with 128 internal signals which can be routed to external through one or more MFPs (e.g. GPIO<0> can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2, see arch/arm/mach-pxa/mfp-pxa300.h)”…””}”(hjgh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K2hjcubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj^ubjb)”}”(hŒÖAlternate function configuration is removed from this GPIO controller, the remaining functions are pure GPIO-specific, i.e. - GPIO signal level control - GPIO direction control - GPIO level change detection ”h]”(hÒ)”}”(hŒ{Alternate function configuration is removed from this GPIO controller, the remaining functions are pure GPIO-specific, i.e.”h]”hŒ{Alternate function configuration is removed from this GPIO controller, the remaining functions are pure GPIO-specific, i.e.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K8hj{ubhÌ)”}”(hŒS- GPIO signal level control - GPIO direction control - GPIO level change detection ”h]”hŒ bullet_list”“”)”}”(hhh]”(jb)”}”(hŒGPIO signal level control”h]”hÒ)”}”(hj˜h]”hŒGPIO signal level control”…””}”(hjšh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K;hj–ubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj“ubjb)”}”(hŒGPIO direction control”h]”hÒ)”}”(hj¯h]”hŒGPIO direction control”…””}”(hj±h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K we normally mean it is a GPIO signal, and by MFP or pin xxx, we mean a physical pad (or ball).”h]”hŒ£NOTE: with such a clear separation of MFP and GPIO, by GPIO we normally mean it is a GPIO signal, and by MFP or pin xxx, we mean a physical pad (or ball).”…””}”(hj1h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KFhj h²hubeh}”(h]”Œ basic-concept”ah ]”h"]”Œ basic concept”ah$]”h&]”uh1hµhh·h²hh³hÊh´K ubh¶)”}”(hhh]”(h»)”}”(hŒ MFP API Usage”h]”hŒ MFP API Usage”…””}”(hjJh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjGh²hh³hÊh´KKubhÒ)”}”(hŒ1For board code writers, here are some guidelines:”h]”hŒ1For board code writers, here are some guidelines:”…””}”(hjXh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KMhjGh²hubj])”}”(hhh]”(jb)”}”(hXZinclude ONE of the following header files in your .c: - #include "mfp-pxa25x.h" - #include "mfp-pxa27x.h" - #include "mfp-pxa300.h" - #include "mfp-pxa320.h" - #include "mfp-pxa930.h" NOTE: only one file in your .c, depending on the processors used, because pin configuration definitions may conflict in these file (i.e. same name, different meaning and settings on different processors). E.g. for zylonite platform, which support both PXA300/PXA310 and PXA320, two separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c (in addition to handle MFP configuration differences, they also handle the other differences between the two combinations). NOTE: PXA300 and PXA310 are almost identical in pin configurations (with PXA310 supporting some additional ones), thus the difference is actually covered in a single mfp-pxa300.h. ”h]”(hÒ)”}”(hŒ.c:”h]”hŒ.c:”…””}”(hjmh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KOhjiubj’)”}”(hhh]”(jb)”}”(hŒ#include "mfp-pxa25x.h"”h]”hÒ)”}”(hj€h]”hŒ#include “mfp-pxa25x.h—…””}”(hj‚h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KQhj~ubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj{ubjb)”}”(hŒ#include "mfp-pxa27x.h"”h]”hÒ)”}”(hj—h]”hŒ#include “mfp-pxa27x.h—…””}”(hj™h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KRhj•ubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj{ubjb)”}”(hŒ#include "mfp-pxa300.h"”h]”hÒ)”}”(hj®h]”hŒ#include “mfp-pxa300.h—…””}”(hj°h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KShj¬ubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj{ubjb)”}”(hŒ#include "mfp-pxa320.h"”h]”hÒ)”}”(hjÅh]”hŒ#include “mfp-pxa320.h—…””}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KThjÃubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj{ubjb)”}”(hŒ#include "mfp-pxa930.h" ”h]”hÒ)”}”(hŒ#include "mfp-pxa930.h"”h]”hŒ#include “mfp-pxa930.h—…””}”(hjÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KUhjÚubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj{ubeh}”(h]”h ]”h"]”h$]”h&]”jâjãuh1j‘h³hÊh´KQhjiubhÒ)”}”(hXãNOTE: only one file in your .c, depending on the processors used, because pin configuration definitions may conflict in these file (i.e. same name, different meaning and settings on different processors). E.g. for zylonite platform, which support both PXA300/PXA310 and PXA320, two separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c (in addition to handle MFP configuration differences, they also handle the other differences between the two combinations).”h]”hXãNOTE: only one file in your .c, depending on the processors used, because pin configuration definitions may conflict in these file (i.e. same name, different meaning and settings on different processors). E.g. for zylonite platform, which support both PXA300/PXA310 and PXA320, two separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c (in addition to handle MFP configuration differences, they also handle the other differences between the two combinations).”…””}”(hjøh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KWhjiubhÒ)”}”(hŒ³NOTE: PXA300 and PXA310 are almost identical in pin configurations (with PXA310 supporting some additional ones), thus the difference is actually covered in a single mfp-pxa300.h.”h]”hŒ³NOTE: PXA300 and PXA310 are almost identical in pin configurations (with PXA310 supporting some additional ones), thus the difference is actually covered in a single mfp-pxa300.h.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K_hjiubeh}”(h]”h ]”h"]”h$]”h&]”uh1jahjfh²hh³hÊh´Nubjb)”}”(hXòprepare an array for the initial pin configurations, e.g.:: static unsigned long mainstone_pin_config[] __initdata = { /* Chip Select */ GPIO15_nCS_1, /* LCD - 16bpp Active TFT */ GPIOxx_TFT_LCD_16BPP, GPIO16_PWM0_OUT, /* Backlight */ /* MMC */ GPIO32_MMC_CLK, GPIO112_MMC_CMD, GPIO92_MMC_DAT_0, GPIO109_MMC_DAT_1, GPIO110_MMC_DAT_2, GPIO111_MMC_DAT_3, ... /* GPIO */ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, }; a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(), and written to the actual registers, they are useless and may discard, adding '__initdata' will help save some additional bytes here. b) when there is only one possible pin configurations for a component, some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on PXA25x and PXA27x processors c) if by board design, a pin can be configured to wake up the system from low power state, it can be 'OR'ed with any of: WAKEUP_ON_EDGE_BOTH WAKEUP_ON_EDGE_RISE WAKEUP_ON_EDGE_FALL WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs, to indicate that this pin has the capability of wake-up the system, and on which edge(s). This, however, doesn't necessarily mean the pin _will_ wakeup the system, it will only when set_irq_wake() is invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq()) and eventually calls gpio_set_wake() for the actual register setting. d) although PXA3xx MFP supports edge detection on each pin, the internal logic will only wakeup the system when those specific bits in ADxER registers are set, which can be well mapped to the corresponding peripheral, thus set_irq_wake() can be called with the peripheral IRQ to enable the wakeup. ”h]”(hÒ)”}”(hŒ;prepare an array for the initial pin configurations, e.g.::”h]”hŒ:prepare an array for the initial pin configurations, e.g.:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Kchjubj+)”}”(hXstatic unsigned long mainstone_pin_config[] __initdata = { /* Chip Select */ GPIO15_nCS_1, /* LCD - 16bpp Active TFT */ GPIOxx_TFT_LCD_16BPP, GPIO16_PWM0_OUT, /* Backlight */ /* MMC */ GPIO32_MMC_CLK, GPIO112_MMC_CMD, GPIO92_MMC_DAT_0, GPIO109_MMC_DAT_1, GPIO110_MMC_DAT_2, GPIO111_MMC_DAT_3, ... /* GPIO */ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, };”h]”hXstatic unsigned long mainstone_pin_config[] __initdata = { /* Chip Select */ GPIO15_nCS_1, /* LCD - 16bpp Active TFT */ GPIOxx_TFT_LCD_16BPP, GPIO16_PWM0_OUT, /* Backlight */ /* MMC */ GPIO32_MMC_CLK, GPIO112_MMC_CMD, GPIO92_MMC_DAT_0, GPIO109_MMC_DAT_1, GPIO110_MMC_DAT_2, GPIO111_MMC_DAT_3, ... /* GPIO */ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, };”…””}”hj,sbah}”(h]”h ]”h"]”h$]”h&]”j:j;uh1j*h³hÊh´KehjubhÒ)”}”(hŒÍa) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(), and written to the actual registers, they are useless and may discard, adding '__initdata' will help save some additional bytes here.”h]”hŒÑa) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(), and written to the actual registers, they are useless and may discard, adding ‘__initdata’ will help save some additional bytes here.”…””}”(hj:h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K{hjubhÒ)”}”(hŒ©b) when there is only one possible pin configurations for a component, some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on PXA25x and PXA27x processors”h]”hŒ©b) when there is only one possible pin configurations for a component, some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on PXA25x and PXA27x processors”…””}”(hjHh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KhjubhÒ)”}”(hŒxc) if by board design, a pin can be configured to wake up the system from low power state, it can be 'OR'ed with any of:”h]”hŒ|c) if by board design, a pin can be configured to wake up the system from low power state, it can be ‘OR’ed with any of:”…””}”(hjVh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KƒhjubhÌ)”}”(hŒ~WAKEUP_ON_EDGE_BOTH WAKEUP_ON_EDGE_RISE WAKEUP_ON_EDGE_FALL WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs, ”h]”hÒ)”}”(hŒ}WAKEUP_ON_EDGE_BOTH WAKEUP_ON_EDGE_RISE WAKEUP_ON_EDGE_FALL WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,”h]”hŒ}WAKEUP_ON_EDGE_BOTH WAKEUP_ON_EDGE_RISE WAKEUP_ON_EDGE_FALL WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,”…””}”(hjhh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K†hjdubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K†hjubhÒ)”}”(hXUto indicate that this pin has the capability of wake-up the system, and on which edge(s). This, however, doesn't necessarily mean the pin _will_ wakeup the system, it will only when set_irq_wake() is invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq()) and eventually calls gpio_set_wake() for the actual register setting.”h]”hXWto indicate that this pin has the capability of wake-up the system, and on which edge(s). This, however, doesn’t necessarily mean the pin _will_ wakeup the system, it will only when set_irq_wake() is invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq()) and eventually calls gpio_set_wake() for the actual register setting.”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K‹hjubhÒ)”}”(hX)d) although PXA3xx MFP supports edge detection on each pin, the internal logic will only wakeup the system when those specific bits in ADxER registers are set, which can be well mapped to the corresponding peripheral, thus set_irq_wake() can be called with the peripheral IRQ to enable the wakeup.”h]”hX)d) although PXA3xx MFP supports edge detection on each pin, the internal logic will only wakeup the system when those specific bits in ADxER registers are set, which can be well mapped to the corresponding peripheral, thus set_irq_wake() can be called with the peripheral IRQ to enable the wakeup.”…””}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K‘hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jahjfh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j&j'j(hj)j*uh1j\hjGh²hh³hÊh´KOubeh}”(h]”Œ mfp-api-usage”ah ]”h"]”Œ mfp api usage”ah$]”h&]”uh1hµhh·h²hh³hÊh´KKubh¶)”}”(hhh]”(h»)”}”(hŒ MFP on PXA3xx”h]”hŒ MFP on PXA3xx”…””}”(hj¯h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj¬h²hh³hÊh´K™ubhÒ)”}”(hŒ’Every external I/O pad on PXA3xx (excluding those for special purpose) has one MFP logic associated, and is controlled by one MFP register (MFPR).”h]”hŒ’Every external I/O pad on PXA3xx (excluding those for special purpose) has one MFP logic associated, and is controlled by one MFP register (MFPR).”…””}”(hj½h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K›hj¬h²hubhÒ)”}”(hŒGThe MFPR has the following bit definitions (for PXA300/PXA310/PXA320)::”h]”hŒFThe MFPR has the following bit definitions (for PXA300/PXA310/PXA320):”…””}”(hjËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Kžhj¬h²hubj+)”}”(hX¾31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | RESERVED |PS|PU|PD| DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL | +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Bit 3: RESERVED Bit 4: EDGE_RISE_EN - enable detection of rising edge on this pin Bit 5: EDGE_FALL_EN - enable detection of falling edge on this pin Bit 6: EDGE_CLEAR - disable edge detection on this pin Bit 7: SLEEP_OE_N - enable outputs during low power modes Bit 8: SLEEP_DATA - output data on the pin during low power modes Bit 9: SLEEP_SEL - selection control for low power modes signals Bit 13: PULLDOWN_EN - enable the internal pull-down resistor on this pin Bit 14: PULLUP_EN - enable the internal pull-up resistor on this pin Bit 15: PULL_SEL - pull state controlled by selected alternate function (0) or by PULL{UP,DOWN}_EN bits (1) Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7 Bit 10-12: DRIVE - drive strength and slew rate 0b000 - fast 1mA 0b001 - fast 2mA 0b002 - fast 3mA 0b003 - fast 4mA 0b004 - slow 6mA 0b005 - fast 6mA 0b006 - slow 10mA 0b007 - fast 10mA”h]”hX¾31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | RESERVED |PS|PU|PD| DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL | +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Bit 3: RESERVED Bit 4: EDGE_RISE_EN - enable detection of rising edge on this pin Bit 5: EDGE_FALL_EN - enable detection of falling edge on this pin Bit 6: EDGE_CLEAR - disable edge detection on this pin Bit 7: SLEEP_OE_N - enable outputs during low power modes Bit 8: SLEEP_DATA - output data on the pin during low power modes Bit 9: SLEEP_SEL - selection control for low power modes signals Bit 13: PULLDOWN_EN - enable the internal pull-down resistor on this pin Bit 14: PULLUP_EN - enable the internal pull-up resistor on this pin Bit 15: PULL_SEL - pull state controlled by selected alternate function (0) or by PULL{UP,DOWN}_EN bits (1) Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7 Bit 10-12: DRIVE - drive strength and slew rate 0b000 - fast 1mA 0b001 - fast 2mA 0b002 - fast 3mA 0b003 - fast 4mA 0b004 - slow 6mA 0b005 - fast 6mA 0b006 - slow 10mA 0b007 - fast 10mA”…””}”hjÙsbah}”(h]”h ]”h"]”h$]”h&]”j:j;uh1j*h³hÊh´K hj¬h²hubeh}”(h]”Œ mfp-on-pxa3xx”ah ]”h"]”Œ mfp on pxa3xx”ah$]”h&]”uh1hµhh·h²hh³hÊh´K™ubh¶)”}”(hhh]”(h»)”}”(hŒMFP Design for PXA2xx/PXA3xx”h]”hŒMFP Design for PXA2xx/PXA3xx”…””}”(hjòh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjïh²hh³hÊh´K½ubhÒ)”}”(hŒˆDue to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified MFP API is introduced to cover both series of processors.”h]”hŒˆDue to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified MFP API is introduced to cover both series of processors.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K¿hjïh²hubhÒ)”}”(hX The basic idea of this design is to introduce definitions for all possible pin configurations, these definitions are processor and platform independent, and the actual API invoked to convert these definitions into register settings and make them effective there-after.”h]”hX The basic idea of this design is to introduce definitions for all possible pin configurations, these definitions are processor and platform independent, and the actual API invoked to convert these definitions into register settings and make them effective there-after.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÂhjïh²hubh¶)”}”(hhh]”(h»)”}”(hŒFiles Involved”h]”hŒFiles Involved”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjh²hh³hÊh´KÈubhÌ)”}”(hX- arch/arm/mach-pxa/include/mach/mfp.h for 1. Unified pin definitions - enum constants for all configurable pins 2. processor-neutral bit definitions for a possible MFP configuration - arch/arm/mach-pxa/mfp-pxa3xx.h for PXA3xx specific MFPR register bit definitions and PXA3xx common pin configurations - arch/arm/mach-pxa/mfp-pxa2xx.h for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations - arch/arm/mach-pxa/mfp-pxa25x.h arch/arm/mach-pxa/mfp-pxa27x.h arch/arm/mach-pxa/mfp-pxa300.h arch/arm/mach-pxa/mfp-pxa320.h arch/arm/mach-pxa/mfp-pxa930.h for processor specific definitions - arch/arm/mach-pxa/mfp-pxa3xx.c - arch/arm/mach-pxa/mfp-pxa2xx.c for implementation of the pin configuration to take effect for the actual processor. ”h]”(j’)”}”(hhh]”jb)”}”(hŒ%arch/arm/mach-pxa/include/mach/mfp.h ”h]”hÒ)”}”(hŒ$arch/arm/mach-pxa/include/mach/mfp.h”h]”hŒ$arch/arm/mach-pxa/include/mach/mfp.h”…””}”(hj8h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÊhj4ubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj1ubah}”(h]”h ]”h"]”h$]”h&]”jâjãuh1j‘h³hÊh´KÊhj-ubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒfor 1. Unified pin definitions - enum constants for all configurable pins 2. processor-neutral bit definitions for a possible MFP configuration ”h]”(hŒterm”“”)”}”(hŒfor”h]”hŒfor”…””}”(hj_h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j]h³hÊh´KÎhjYubhŒ definition”“”)”}”(hhh]”j])”}”(hhh]”(jb)”}”(hŒBUnified pin definitions - enum constants for all configurable pins”h]”hÒ)”}”(hjwh]”hŒBUnified pin definitions - enum constants for all configurable pins”…””}”(hjyh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÍhjuubah}”(h]”h ]”h"]”h$]”h&]”uh1jahjrubjb)”}”(hŒCprocessor-neutral bit definitions for a possible MFP configuration ”h]”hÒ)”}”(hŒBprocessor-neutral bit definitions for a possible MFP configuration”h]”hŒBprocessor-neutral bit definitions for a possible MFP configuration”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÎhjŒubah}”(h]”h ]”h"]”h$]”h&]”uh1jahjrubeh}”(h]”h ]”h"]”h$]”h&]”j&j'j(hj)j*uh1j\hjoubah}”(h]”h ]”h"]”h$]”h&]”uh1jmhjYubeh}”(h]”h ]”h"]”h$]”h&]”uh1jWh³hÊh´KÎhjTubah}”(h]”h ]”h"]”h$]”h&]”uh1jRhj-ubj’)”}”(hhh]”jb)”}”(hŒarch/arm/mach-pxa/mfp-pxa3xx.h ”h]”hÒ)”}”(hŒarch/arm/mach-pxa/mfp-pxa3xx.h”h]”hŒarch/arm/mach-pxa/mfp-pxa3xx.h”…””}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÐhj¿ubah}”(h]”h ]”h"]”h$]”h&]”uh1jahj¼ubah}”(h]”h ]”h"]”h$]”h&]”jâjãuh1j‘h³hÊh´KÐhj-ubhÒ)”}”(hŒVfor PXA3xx specific MFPR register bit definitions and PXA3xx common pin configurations”h]”hŒVfor PXA3xx specific MFPR register bit definitions and PXA3xx common pin configurations”…””}”(hjÝh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÒhj-ubj’)”}”(hhh]”jb)”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.h ”h]”hÒ)”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.h”h]”hŒarch/arm/mach-pxa/mfp-pxa2xx.h”…””}”(hjòh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÕhjîubah}”(h]”h ]”h"]”h$]”h&]”uh1jahjëubah}”(h]”h ]”h"]”h$]”h&]”jâjãuh1j‘h³hÊh´KÕhj-ubhÒ)”}”(hŒKfor PXA2xx specific definitions and PXA25x/PXA27x common pin configurations”h]”hŒKfor PXA2xx specific definitions and PXA25x/PXA27x common pin configurations”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´K×hj-ubj’)”}”(hhh]”jb)”}”(hŒ›arch/arm/mach-pxa/mfp-pxa25x.h arch/arm/mach-pxa/mfp-pxa27x.h arch/arm/mach-pxa/mfp-pxa300.h arch/arm/mach-pxa/mfp-pxa320.h arch/arm/mach-pxa/mfp-pxa930.h ”h]”hÒ)”}”(hŒšarch/arm/mach-pxa/mfp-pxa25x.h arch/arm/mach-pxa/mfp-pxa27x.h arch/arm/mach-pxa/mfp-pxa300.h arch/arm/mach-pxa/mfp-pxa320.h arch/arm/mach-pxa/mfp-pxa930.h”h]”hŒšarch/arm/mach-pxa/mfp-pxa25x.h arch/arm/mach-pxa/mfp-pxa27x.h arch/arm/mach-pxa/mfp-pxa300.h arch/arm/mach-pxa/mfp-pxa320.h arch/arm/mach-pxa/mfp-pxa930.h”…””}”(hj!h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KÙhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jahjubah}”(h]”h ]”h"]”h$]”h&]”jâjãuh1j‘h³hÊh´KÙhj-ubhÒ)”}”(hŒ"for processor specific definitions”h]”hŒ"for processor specific definitions”…””}”(hj;h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Kßhj-ubj’)”}”(hhh]”(jb)”}”(hŒarch/arm/mach-pxa/mfp-pxa3xx.c”h]”hÒ)”}”(hjNh]”hŒarch/arm/mach-pxa/mfp-pxa3xx.c”…””}”(hjPh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´KáhjLubah}”(h]”h ]”h"]”h$]”h&]”uh1jahjIubjb)”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.c ”h]”hÒ)”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.c”h]”hŒarch/arm/mach-pxa/mfp-pxa2xx.c”…””}”(hjgh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Kâhjcubah}”(h]”h ]”h"]”h$]”h&]”uh1jahjIubeh}”(h]”h ]”h"]”h$]”h&]”jâjãuh1j‘h³hÊh´Káhj-ubhÒ)”}”(hŒTfor implementation of the pin configuration to take effect for the actual processor.”h]”hŒTfor implementation of the pin configuration to take effect for the actual processor.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Kähj-ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÊhjh²hubeh}”(h]”Œfiles-involved”ah ]”h"]”Œfiles involved”ah$]”h&]”uh1hµhjïh²hh³hÊh´KÈubh¶)”}”(hhh]”(h»)”}”(hŒPin Configuration”h]”hŒPin Configuration”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjh²hh³hÊh´KèubhÌ)”}”(hXšThe following comments are copied from mfp.h (see the actual source code for most updated info):: /* * a possible MFP configuration is represented by a 32-bit integer * * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) * bit 10..12 - Alternate Function Selection * bit 13..15 - Drive Strength * bit 16..18 - Low Power Mode State * bit 19..20 - Low Power Mode Edge Detection * bit 21..22 - Run Mode Pull State * * to facilitate the definition, the following macros are provided * * MFP_CFG_DEFAULT - default MFP configuration value, with * alternate function = 0, * drive strength = fast 3mA (MFP_DS03X) * low power mode = default * edge detection = none * * MFP_CFG - default MFPR value with alternate function * MFP_CFG_DRV - default MFPR value with alternate function and * pin drive strength * MFP_CFG_LPM - default MFPR value with alternate function and * low power mode * MFP_CFG_X - default MFPR value with alternate function, * pin drive strength and low power mode */ Examples of pin configurations are:: #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) which reads GPIO94 can be configured as SSP3_RXD, with alternate function selection of 1, driving strength of 0b101, and a float state in low power modes. NOTE: this is the default setting of this pin being configured as SSP3_RXD which can be modified a bit in board code, though it is not recommended to do so, simply because this default setting is usually carefully encoded, and is supposed to work in most cases. ”h]”(hÒ)”}”(hŒaThe following comments are copied from mfp.h (see the actual source code for most updated info)::”h]”hŒ`The following comments are copied from mfp.h (see the actual source code for most updated info):”…””}”(hj²h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Kêhj®ubj+)”}”(hX /* * a possible MFP configuration is represented by a 32-bit integer * * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) * bit 10..12 - Alternate Function Selection * bit 13..15 - Drive Strength * bit 16..18 - Low Power Mode State * bit 19..20 - Low Power Mode Edge Detection * bit 21..22 - Run Mode Pull State * * to facilitate the definition, the following macros are provided * * MFP_CFG_DEFAULT - default MFP configuration value, with * alternate function = 0, * drive strength = fast 3mA (MFP_DS03X) * low power mode = default * edge detection = none * * MFP_CFG - default MFPR value with alternate function * MFP_CFG_DRV - default MFPR value with alternate function and * pin drive strength * MFP_CFG_LPM - default MFPR value with alternate function and * low power mode * MFP_CFG_X - default MFPR value with alternate function, * pin drive strength and low power mode */ Examples of pin configurations are:: #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) which reads GPIO94 can be configured as SSP3_RXD, with alternate function selection of 1, driving strength of 0b101, and a float state in low power modes. NOTE: this is the default setting of this pin being configured as SSP3_RXD which can be modified a bit in board code, though it is not recommended to do so, simply because this default setting is usually carefully encoded, and is supposed to work in most cases.”h]”hX /* * a possible MFP configuration is represented by a 32-bit integer * * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) * bit 10..12 - Alternate Function Selection * bit 13..15 - Drive Strength * bit 16..18 - Low Power Mode State * bit 19..20 - Low Power Mode Edge Detection * bit 21..22 - Run Mode Pull State * * to facilitate the definition, the following macros are provided * * MFP_CFG_DEFAULT - default MFP configuration value, with * alternate function = 0, * drive strength = fast 3mA (MFP_DS03X) * low power mode = default * edge detection = none * * MFP_CFG - default MFPR value with alternate function * MFP_CFG_DRV - default MFPR value with alternate function and * pin drive strength * MFP_CFG_LPM - default MFPR value with alternate function and * low power mode * MFP_CFG_X - default MFPR value with alternate function, * pin drive strength and low power mode */ Examples of pin configurations are:: #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) which reads GPIO94 can be configured as SSP3_RXD, with alternate function selection of 1, driving strength of 0b101, and a float state in low power modes. NOTE: this is the default setting of this pin being configured as SSP3_RXD which can be modified a bit in board code, though it is not recommended to do so, simply because this default setting is usually carefully encoded, and is supposed to work in most cases.”…””}”hjÀsbah}”(h]”h ]”h"]”h$]”h&]”j:j;uh1j*h³hÊh´Kíhj®ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kêhjh²hubeh}”(h]”Œpin-configuration”ah ]”h"]”Œpin configuration”ah$]”h&]”uh1hµhjïh²hh³hÊh´Kèubh¶)”}”(hhh]”(h»)”}”(hŒRegister Settings”h]”hŒRegister Settings”…””}”(hjßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÜh²hh³hÊh´MubhÌ)”}”(hXRegister settings on PXA3xx for a pin configuration is actually very straight-forward, most bits can be converted directly into MFPR value in a easier way. Two sets of MFPR values are calculated: the run-time ones and the low power mode ones, to allow different settings. The conversion from a generic pin configuration to the actual register settings on PXA2xx is a bit complicated: many registers are involved, including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see mfp-pxa2xx.c for how the conversion is made.”h]”(hÒ)”}”(hXRegister settings on PXA3xx for a pin configuration is actually very straight-forward, most bits can be converted directly into MFPR value in a easier way. Two sets of MFPR values are calculated: the run-time ones and the low power mode ones, to allow different settings.”h]”hXRegister settings on PXA3xx for a pin configuration is actually very straight-forward, most bits can be converted directly into MFPR value in a easier way. Two sets of MFPR values are calculated: the run-time ones and the low power mode ones, to allow different settings.”…””}”(hjñh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´MhjíubhÒ)”}”(hŒþThe conversion from a generic pin configuration to the actual register settings on PXA2xx is a bit complicated: many registers are involved, including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see mfp-pxa2xx.c for how the conversion is made.”h]”hŒþThe conversion from a generic pin configuration to the actual register settings on PXA2xx is a bit complicated: many registers are involved, including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see mfp-pxa2xx.c for how the conversion is made.”…””}”(hjÿh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÑh³hÊh´Mhjíubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MhjÜh²hubeh}”(h]”Œregister-settings”ah ]”h"]”Œregister settings”ah$]”h&]”uh1hµhjïh²hh³hÊh´Mubeh}”(h]”Œmfp-design-for-pxa2xx-pxa3xx”ah ]”h"]”Œmfp design for pxa2xx/pxa3xx”ah$]”h&]”uh1hµhh·h²hh³hÊh´K½ubeh}”(h]”Œ.mfp-configuration-for-pxa2xx-pxa3xx-processors”ah ]”h"]”Œ.mfp configuration for pxa2xx/pxa3xx processors”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jNŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j(j%jDjAj©j¦jìjéj jjšj—jÙjÖjjuŒ nametypes”}”(j(‰jD‰j©‰jì‰j ‰jš‰jÙ‰j‰uh}”(j%h·jAj j¦jGjéj¬jjïj—jjÖjjjÜuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.