€•ü§      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ$/translations/zh_CN/arch/arm/pxa/mfp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/zh_TW/arch/arm/pxa/mfp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/it_IT/arch/arm/pxa/mfp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/ja_JP/arch/arm/pxa/mfp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/ko_KR/arch/arm/pxa/mfp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ$/translations/sp_SP/arch/arm/pxa/mfp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ.MFP Configuration for PXA2xx/PXA3xx Processors”h]”hŒ.MFP Configuration for PXA2xx/PXA3xx Processors”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒ>/var/lib/git/docbuild/linux/Documentation/arch/arm/pxa/mfp.rst”h KubhŒblock_quote”“”)”}”(hŒ"Eric Miao <eric.miao@marvell.com>
”h]”hŒ	paragraph”“”)”}”(hŒ!Eric Miao <eric.miao@marvell.com>”h]”(hŒEric Miao <”…””}”(hh¿hžhhŸNh NubhŒ	reference”“”)”}”(hŒeric.miao@marvell.com”h]”hŒeric.miao@marvell.com”…””}”(hhÉhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:eric.miao@marvell.com”uh1hÇhh¿ubhŒ>”…””}”(hh¿hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Khh¹ubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¾)”}”(hŒÓMFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
later PXA series processors.  This document describes the existing MFP API,
and how board/platform driver authors could make use of it.”h]”hŒÓMFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
later PXA series processors.  This document describes the existing MFP API,
and how board/platform driver authors could make use of it.”…””}”(hhéhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒBasic Concept”h]”hŒBasic Concept”…””}”(hhúhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh÷hžhhŸh¶h Kubh¾)”}”(hX¬  Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
mechanism is introduced from PXA3xx to completely move the pin-mux functions
out of the GPIO controller. In addition to pin-mux configurations, the MFP
also controls the low power state, driving strength, pull-up/down and event
detection of each pin.  Below is a diagram of internal connections between
the MFP logic and the remaining SoC peripherals::”h]”hX«  Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
mechanism is introduced from PXA3xx to completely move the pin-mux functions
out of the GPIO controller. In addition to pin-mux configurations, the MFP
also controls the low power state, driving strength, pull-up/down and event
detection of each pin.  Below is a diagram of internal connections between
the MFP logic and the remaining SoC peripherals:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Khh÷hžhubhŒliteral_block”“”)”}”(hX“  +--------+
|        |--(GPIO19)--+
|  GPIO  |            |
|        |--(GPIO...) |
+--------+            |
                      |       +---------+
+--------+            +------>|         |
|  PWM2  |--(PWM_OUT)-------->|   MFP   |
+--------+            +------>|         |-------> to external PAD
                      | +---->|         |
+--------+            | | +-->|         |
|  SSP2  |---(TXD)----+ | |   +---------+
+--------+              | |
                        | |
+--------+              | |
| Keypad |--(MKOUT4)----+ |
+--------+                |
                          |
+--------+                |
|  UART2 |---(TXD)--------+
+--------+”h]”hX“  +--------+
|        |--(GPIO19)--+
|  GPIO  |            |
|        |--(GPIO...) |
+--------+            |
                      |       +---------+
+--------+            +------>|         |
|  PWM2  |--(PWM_OUT)-------->|   MFP   |
+--------+            +------>|         |-------> to external PAD
                      | +---->|         |
+--------+            | | +-->|         |
|  SSP2  |---(TXD)----+ | |   +---------+
+--------+              | |
                        | |
+--------+              | |
| Keypad |--(MKOUT4)----+ |
+--------+                |
                          |
+--------+                |
|  UART2 |---(TXD)--------+
+--------+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1j  hŸh¶h Khh÷hžhubh¾)”}”(hŒÃNOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily
mean it's dedicated for GPIO19, only as a hint that internally this pin
can be routed from GPIO19 of the GPIO controller.”h]”hŒÇNOTE: the external pad is named as MFP_PIN_GPIO19, it doesnâ€™t necessarily
mean itâ€™s dedicated for GPIO19, only as a hint that internally this pin
can be routed from GPIO19 of the GPIO controller.”…””}”(hj(  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K+hh÷hžhubh¾)”}”(hŒ‚To better understand the change from PXA25x/PXA27x GPIO alternate function
to this new MFP mechanism, here are several key points:”h]”hŒ‚To better understand the change from PXA25x/PXA27x GPIO alternate function
to this new MFP mechanism, here are several key points:”…””}”(hj6  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K/hh÷hžhubh¸)”}”(hX…  1. GPIO controller on PXA3xx is now a dedicated controller, same as other
   internal controllers like PWM, SSP and UART, with 128 internal signals
   which can be routed to external through one or more MFPs (e.g. GPIO<0>
   can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
   see arch/arm/mach-pxa/mfp-pxa300.h)

2. Alternate function configuration is removed from this GPIO controller,
   the remaining functions are pure GPIO-specific, i.e.

     - GPIO signal level control
     - GPIO direction control
     - GPIO level change detection

3. Low power state for each pin is now controlled by MFP, this means the
   PGSRx registers on PXA2xx are now useless on PXA3xx

4. Wakeup detection is now controlled by MFP, PWER does not control the
   wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
   (as defined in pxa3xx-regs.h) controls the wakeup from MFP
”h]”hŒenumerated_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX@  GPIO controller on PXA3xx is now a dedicated controller, same as other
internal controllers like PWM, SSP and UART, with 128 internal signals
which can be routed to external through one or more MFPs (e.g. GPIO<0>
can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
see arch/arm/mach-pxa/mfp-pxa300.h)
”h]”h¾)”}”(hX?  GPIO controller on PXA3xx is now a dedicated controller, same as other
internal controllers like PWM, SSP and UART, with 128 internal signals
which can be routed to external through one or more MFPs (e.g. GPIO<0>
can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
see arch/arm/mach-pxa/mfp-pxa300.h)”h]”hX?  GPIO controller on PXA3xx is now a dedicated controller, same as other
internal controllers like PWM, SSP and UART, with 128 internal signals
which can be routed to external through one or more MFPs (e.g. GPIO<0>
can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
see arch/arm/mach-pxa/mfp-pxa300.h)”…””}”(hjS  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K2hjO  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjJ  ubjN  )”}”(hŒÖAlternate function configuration is removed from this GPIO controller,
the remaining functions are pure GPIO-specific, i.e.

  - GPIO signal level control
  - GPIO direction control
  - GPIO level change detection
”h]”(h¾)”}”(hŒ{Alternate function configuration is removed from this GPIO controller,
the remaining functions are pure GPIO-specific, i.e.”h]”hŒ{Alternate function configuration is removed from this GPIO controller,
the remaining functions are pure GPIO-specific, i.e.”…””}”(hjk  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K8hjg  ubh¸)”}”(hŒS- GPIO signal level control
- GPIO direction control
- GPIO level change detection
”h]”hŒbullet_list”“”)”}”(hhh]”(jN  )”}”(hŒGPIO signal level control”h]”h¾)”}”(hj„  h]”hŒGPIO signal level control”…””}”(hj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K;hj‚  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj  ubjN  )”}”(hŒGPIO direction control”h]”h¾)”}”(hj›  h]”hŒGPIO direction control”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K<hj™  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj  ubjN  )”}”(hŒGPIO level change detection
”h]”h¾)”}”(hŒGPIO level change detection”h]”hŒGPIO level change detection”…””}”(hj´  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K=hj°  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j}  hŸh¶h K;hjy  ubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K;hjg  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjJ  ubjN  )”}”(hŒzLow power state for each pin is now controlled by MFP, this means the
PGSRx registers on PXA2xx are now useless on PXA3xx
”h]”h¾)”}”(hŒyLow power state for each pin is now controlled by MFP, this means the
PGSRx registers on PXA2xx are now useless on PXA3xx”h]”hŒyLow power state for each pin is now controlled by MFP, this means the
PGSRx registers on PXA2xx are now useless on PXA3xx”…””}”(hjà  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K?hjÜ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjJ  ubjN  )”}”(hŒÅWakeup detection is now controlled by MFP, PWER does not control the
wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
(as defined in pxa3xx-regs.h) controls the wakeup from MFP
”h]”h¾)”}”(hŒÄWakeup detection is now controlled by MFP, PWER does not control the
wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
(as defined in pxa3xx-regs.h) controls the wakeup from MFP”h]”hŒÄWakeup detection is now controlled by MFP, PWER does not control the
wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
(as defined in pxa3xx-regs.h) controls the wakeup from MFP”…””}”(hjø  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KBhjô  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjJ  ubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1jH  hjD  ubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K2hh÷hžhubh¾)”}”(hŒ£NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
pad (or ball).”h]”hŒ£NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
pad (or ball).”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KFhh÷hžhubeh}”(h]”Œbasic-concept”ah ]”h"]”Œbasic concept”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒMFP API Usage”h]”hŒMFP API Usage”…””}”(hj6  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj3  hžhhŸh¶h KKubh¾)”}”(hŒ1For board code writers, here are some guidelines:”h]”hŒ1For board code writers, here are some guidelines:”…””}”(hjD  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KMhj3  hžhubjI  )”}”(hhh]”(jN  )”}”(hXZ  include ONE of the following header files in your <board>.c:

- #include "mfp-pxa25x.h"
- #include "mfp-pxa27x.h"
- #include "mfp-pxa300.h"
- #include "mfp-pxa320.h"
- #include "mfp-pxa930.h"

NOTE: only one file in your <board>.c, depending on the processors used,
because pin configuration definitions may conflict in these file (i.e.
same name, different meaning and settings on different processors). E.g.
for zylonite platform, which support both PXA300/PXA310 and PXA320, two
separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
(in addition to handle MFP configuration differences, they also handle
the other differences between the two combinations).

NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
PXA310 supporting some additional ones), thus the difference is actually
covered in a single mfp-pxa300.h.
”h]”(h¾)”}”(hŒ<include ONE of the following header files in your <board>.c:”h]”hŒ<include ONE of the following header files in your <board>.c:”…””}”(hjY  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KOhjU  ubj~  )”}”(hhh]”(jN  )”}”(hŒ#include "mfp-pxa25x.h"”h]”h¾)”}”(hjl  h]”hŒ#include â€œmfp-pxa25x.hâ€”…””}”(hjn  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KQhjj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjg  ubjN  )”}”(hŒ#include "mfp-pxa27x.h"”h]”h¾)”}”(hjƒ  h]”hŒ#include â€œmfp-pxa27x.hâ€”…””}”(hj…  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KRhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjg  ubjN  )”}”(hŒ#include "mfp-pxa300.h"”h]”h¾)”}”(hjš  h]”hŒ#include â€œmfp-pxa300.hâ€”…””}”(hjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KShj˜  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjg  ubjN  )”}”(hŒ#include "mfp-pxa320.h"”h]”h¾)”}”(hj±  h]”hŒ#include â€œmfp-pxa320.hâ€”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KThj¯  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjg  ubjN  )”}”(hŒ#include "mfp-pxa930.h"
”h]”h¾)”}”(hŒ#include "mfp-pxa930.h"”h]”hŒ#include â€œmfp-pxa930.hâ€”…””}”(hjÊ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KUhjÆ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjg  ubeh}”(h]”h ]”h"]”h$]”h&]”jÎ  jÏ  uh1j}  hŸh¶h KQhjU  ubh¾)”}”(hXã  NOTE: only one file in your <board>.c, depending on the processors used,
because pin configuration definitions may conflict in these file (i.e.
same name, different meaning and settings on different processors). E.g.
for zylonite platform, which support both PXA300/PXA310 and PXA320, two
separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
(in addition to handle MFP configuration differences, they also handle
the other differences between the two combinations).”h]”hXã  NOTE: only one file in your <board>.c, depending on the processors used,
because pin configuration definitions may conflict in these file (i.e.
same name, different meaning and settings on different processors). E.g.
for zylonite platform, which support both PXA300/PXA310 and PXA320, two
separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
(in addition to handle MFP configuration differences, they also handle
the other differences between the two combinations).”…””}”(hjä  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KWhjU  ubh¾)”}”(hŒ³NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
PXA310 supporting some additional ones), thus the difference is actually
covered in a single mfp-pxa300.h.”h]”hŒ³NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
PXA310 supporting some additional ones), thus the difference is actually
covered in a single mfp-pxa300.h.”…””}”(hjò  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K_hjU  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjR  hžhhŸh¶h NubjN  )”}”(hXò  prepare an array for the initial pin configurations, e.g.::

  static unsigned long mainstone_pin_config[] __initdata = {
     /* Chip Select */
     GPIO15_nCS_1,

     /* LCD - 16bpp Active TFT */
     GPIOxx_TFT_LCD_16BPP,
     GPIO16_PWM0_OUT,        /* Backlight */

     /* MMC */
     GPIO32_MMC_CLK,
     GPIO112_MMC_CMD,
     GPIO92_MMC_DAT_0,
     GPIO109_MMC_DAT_1,
     GPIO110_MMC_DAT_2,
     GPIO111_MMC_DAT_3,

     ...

     /* GPIO */
     GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  };

a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
and written to the actual registers, they are useless and may discard,
adding '__initdata' will help save some additional bytes here.

b) when there is only one possible pin configurations for a component,
some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
PXA25x and PXA27x processors

c) if by board design, a pin can be configured to wake up the system
from low power state, it can be 'OR'ed with any of:

   WAKEUP_ON_EDGE_BOTH
   WAKEUP_ON_EDGE_RISE
   WAKEUP_ON_EDGE_FALL
   WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,

to indicate that this pin has the capability of wake-up the system,
and on which edge(s). This, however, doesn't necessarily mean the
pin _will_ wakeup the system, it will only when set_irq_wake() is
invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
and eventually calls gpio_set_wake() for the actual register setting.

d) although PXA3xx MFP supports edge detection on each pin, the
internal logic will only wakeup the system when those specific bits
in ADxER registers are set, which can be well mapped to the
corresponding peripheral, thus set_irq_wake() can be called with
the peripheral IRQ to enable the wakeup.

”h]”(h¾)”}”(hŒ;prepare an array for the initial pin configurations, e.g.::”h]”hŒ:prepare an array for the initial pin configurations, e.g.:”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Kchj  ubj  )”}”(hX  static unsigned long mainstone_pin_config[] __initdata = {
   /* Chip Select */
   GPIO15_nCS_1,

   /* LCD - 16bpp Active TFT */
   GPIOxx_TFT_LCD_16BPP,
   GPIO16_PWM0_OUT,        /* Backlight */

   /* MMC */
   GPIO32_MMC_CLK,
   GPIO112_MMC_CMD,
   GPIO92_MMC_DAT_0,
   GPIO109_MMC_DAT_1,
   GPIO110_MMC_DAT_2,
   GPIO111_MMC_DAT_3,

   ...

   /* GPIO */
   GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};”h]”hX  static unsigned long mainstone_pin_config[] __initdata = {
   /* Chip Select */
   GPIO15_nCS_1,

   /* LCD - 16bpp Active TFT */
   GPIOxx_TFT_LCD_16BPP,
   GPIO16_PWM0_OUT,        /* Backlight */

   /* MMC */
   GPIO32_MMC_CLK,
   GPIO112_MMC_CMD,
   GPIO92_MMC_DAT_0,
   GPIO109_MMC_DAT_1,
   GPIO110_MMC_DAT_2,
   GPIO111_MMC_DAT_3,

   ...

   /* GPIO */
   GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j&  j'  uh1j  hŸh¶h Kehj  ubh¾)”}”(hŒÍa) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
and written to the actual registers, they are useless and may discard,
adding '__initdata' will help save some additional bytes here.”h]”hŒÑa) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
and written to the actual registers, they are useless and may discard,
adding â€˜__initdataâ€™ will help save some additional bytes here.”…””}”(hj&  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K{hj  ubh¾)”}”(hŒ©b) when there is only one possible pin configurations for a component,
some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
PXA25x and PXA27x processors”h]”hŒ©b) when there is only one possible pin configurations for a component,
some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
PXA25x and PXA27x processors”…””}”(hj4  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Khj  ubh¾)”}”(hŒxc) if by board design, a pin can be configured to wake up the system
from low power state, it can be 'OR'ed with any of:”h]”hŒ|c) if by board design, a pin can be configured to wake up the system
from low power state, it can be â€˜ORâ€™ed with any of:”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Kƒhj  ubh¸)”}”(hŒ~WAKEUP_ON_EDGE_BOTH
WAKEUP_ON_EDGE_RISE
WAKEUP_ON_EDGE_FALL
WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,
”h]”h¾)”}”(hŒ}WAKEUP_ON_EDGE_BOTH
WAKEUP_ON_EDGE_RISE
WAKEUP_ON_EDGE_FALL
WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,”h]”hŒ}WAKEUP_ON_EDGE_BOTH
WAKEUP_ON_EDGE_RISE
WAKEUP_ON_EDGE_FALL
WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,”…””}”(hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K†hjP  ubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K†hj  ubh¾)”}”(hXU  to indicate that this pin has the capability of wake-up the system,
and on which edge(s). This, however, doesn't necessarily mean the
pin _will_ wakeup the system, it will only when set_irq_wake() is
invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
and eventually calls gpio_set_wake() for the actual register setting.”h]”hXW  to indicate that this pin has the capability of wake-up the system,
and on which edge(s). This, however, doesnâ€™t necessarily mean the
pin _will_ wakeup the system, it will only when set_irq_wake() is
invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
and eventually calls gpio_set_wake() for the actual register setting.”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K‹hj  ubh¾)”}”(hX)  d) although PXA3xx MFP supports edge detection on each pin, the
internal logic will only wakeup the system when those specific bits
in ADxER registers are set, which can be well mapped to the
corresponding peripheral, thus set_irq_wake() can be called with
the peripheral IRQ to enable the wakeup.”h]”hX)  d) although PXA3xx MFP supports edge detection on each pin, the
internal logic will only wakeup the system when those specific bits
in ADxER registers are set, which can be well mapped to the
corresponding peripheral, thus set_irq_wake() can be called with
the peripheral IRQ to enable the wakeup.”…””}”(hjv  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K‘hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jM  hjR  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  uh1jH  hj3  hžhhŸh¶h KOubeh}”(h]”Œmfp-api-usage”ah ]”h"]”Œmfp api usage”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KKubh¢)”}”(hhh]”(h§)”}”(hŒMFP on PXA3xx”h]”hŒMFP on PXA3xx”…””}”(hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj˜  hžhhŸh¶h K™ubh¾)”}”(hŒ’Every external I/O pad on PXA3xx (excluding those for special purpose) has
one MFP logic associated, and is controlled by one MFP register (MFPR).”h]”hŒ’Every external I/O pad on PXA3xx (excluding those for special purpose) has
one MFP logic associated, and is controlled by one MFP register (MFPR).”…””}”(hj©  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K›hj˜  hžhubh¾)”}”(hŒGThe MFPR has the following bit definitions (for PXA300/PXA310/PXA320)::”h]”hŒFThe MFPR has the following bit definitions (for PXA300/PXA310/PXA320):”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Kžhj˜  hžhubj  )”}”(hX¾  31                        16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
 |         RESERVED        |PS|PU|PD|  DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL |
 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

 Bit 3:   RESERVED
 Bit 4:   EDGE_RISE_EN - enable detection of rising edge on this pin
 Bit 5:   EDGE_FALL_EN - enable detection of falling edge on this pin
 Bit 6:   EDGE_CLEAR   - disable edge detection on this pin
 Bit 7:   SLEEP_OE_N   - enable outputs during low power modes
 Bit 8:   SLEEP_DATA   - output data on the pin during low power modes
 Bit 9:   SLEEP_SEL    - selection control for low power modes signals
 Bit 13:  PULLDOWN_EN  - enable the internal pull-down resistor on this pin
 Bit 14:  PULLUP_EN    - enable the internal pull-up resistor on this pin
 Bit 15:  PULL_SEL     - pull state controlled by selected alternate function
                         (0) or by PULL{UP,DOWN}_EN bits (1)

 Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
 Bit 10-12: DRIVE  - drive strength and slew rate
                       0b000 - fast 1mA
                       0b001 - fast 2mA
                       0b002 - fast 3mA
                       0b003 - fast 4mA
                       0b004 - slow 6mA
                       0b005 - fast 6mA
                       0b006 - slow 10mA
                       0b007 - fast 10mA”h]”hX¾  31                        16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
 |         RESERVED        |PS|PU|PD|  DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL |
 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

 Bit 3:   RESERVED
 Bit 4:   EDGE_RISE_EN - enable detection of rising edge on this pin
 Bit 5:   EDGE_FALL_EN - enable detection of falling edge on this pin
 Bit 6:   EDGE_CLEAR   - disable edge detection on this pin
 Bit 7:   SLEEP_OE_N   - enable outputs during low power modes
 Bit 8:   SLEEP_DATA   - output data on the pin during low power modes
 Bit 9:   SLEEP_SEL    - selection control for low power modes signals
 Bit 13:  PULLDOWN_EN  - enable the internal pull-down resistor on this pin
 Bit 14:  PULLUP_EN    - enable the internal pull-up resistor on this pin
 Bit 15:  PULL_SEL     - pull state controlled by selected alternate function
                         (0) or by PULL{UP,DOWN}_EN bits (1)

 Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
 Bit 10-12: DRIVE  - drive strength and slew rate
                       0b000 - fast 1mA
                       0b001 - fast 2mA
                       0b002 - fast 3mA
                       0b003 - fast 4mA
                       0b004 - slow 6mA
                       0b005 - fast 6mA
                       0b006 - slow 10mA
                       0b007 - fast 10mA”…””}”hjÅ  sbah}”(h]”h ]”h"]”h$]”h&]”j&  j'  uh1j  hŸh¶h K hj˜  hžhubeh}”(h]”Œmfp-on-pxa3xx”ah ]”h"]”Œmfp on pxa3xx”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K™ubh¢)”}”(hhh]”(h§)”}”(hŒMFP Design for PXA2xx/PXA3xx”h]”hŒMFP Design for PXA2xx/PXA3xx”…””}”(hjÞ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÛ  hžhhŸh¶h K½ubh¾)”}”(hŒˆDue to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
MFP API is introduced to cover both series of processors.”h]”hŒˆDue to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
MFP API is introduced to cover both series of processors.”…””}”(hjì  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K¿hjÛ  hžhubh¾)”}”(hX  The basic idea of this design is to introduce definitions for all possible pin
configurations, these definitions are processor and platform independent, and
the actual API invoked to convert these definitions into register settings and
make them effective there-after.”h]”hX  The basic idea of this design is to introduce definitions for all possible pin
configurations, these definitions are processor and platform independent, and
the actual API invoked to convert these definitions into register settings and
make them effective there-after.”…””}”(hjú  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÂhjÛ  hžhubh¢)”}”(hhh]”(h§)”}”(hŒFiles Involved”h]”hŒFiles Involved”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h KÈubh¸)”}”(hX  - arch/arm/mach-pxa/include/mach/mfp.h

for
  1. Unified pin definitions - enum constants for all configurable pins
  2. processor-neutral bit definitions for a possible MFP configuration

- arch/arm/mach-pxa/mfp-pxa3xx.h

for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
configurations

- arch/arm/mach-pxa/mfp-pxa2xx.h

for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations

- arch/arm/mach-pxa/mfp-pxa25x.h
  arch/arm/mach-pxa/mfp-pxa27x.h
  arch/arm/mach-pxa/mfp-pxa300.h
  arch/arm/mach-pxa/mfp-pxa320.h
  arch/arm/mach-pxa/mfp-pxa930.h

for processor specific definitions

- arch/arm/mach-pxa/mfp-pxa3xx.c
- arch/arm/mach-pxa/mfp-pxa2xx.c

for implementation of the pin configuration to take effect for the actual
processor.
”h]”(j~  )”}”(hhh]”jN  )”}”(hŒ%arch/arm/mach-pxa/include/mach/mfp.h
”h]”h¾)”}”(hŒ$arch/arm/mach-pxa/include/mach/mfp.h”h]”hŒ$arch/arm/mach-pxa/include/mach/mfp.h”…””}”(hj$  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÊhj   ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj  ubah}”(h]”h ]”h"]”h$]”h&]”jÎ  jÏ  uh1j}  hŸh¶h KÊhj  ubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒfor
1. Unified pin definitions - enum constants for all configurable pins
2. processor-neutral bit definitions for a possible MFP configuration
”h]”(hŒterm”“”)”}”(hŒfor”h]”hŒfor”…””}”(hjK  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jI  hŸh¶h KÎhjE  ubhŒ
definition”“”)”}”(hhh]”jI  )”}”(hhh]”(jN  )”}”(hŒBUnified pin definitions - enum constants for all configurable pins”h]”h¾)”}”(hjc  h]”hŒBUnified pin definitions - enum constants for all configurable pins”…””}”(hje  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÍhja  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj^  ubjN  )”}”(hŒCprocessor-neutral bit definitions for a possible MFP configuration
”h]”h¾)”}”(hŒBprocessor-neutral bit definitions for a possible MFP configuration”h]”hŒBprocessor-neutral bit definitions for a possible MFP configuration”…””}”(hj|  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÎhjx  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj^  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  uh1jH  hj[  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjE  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jC  hŸh¶h KÎhj@  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j>  hj  ubj~  )”}”(hhh]”jN  )”}”(hŒarch/arm/mach-pxa/mfp-pxa3xx.h
”h]”h¾)”}”(hŒarch/arm/mach-pxa/mfp-pxa3xx.h”h]”hŒarch/arm/mach-pxa/mfp-pxa3xx.h”…””}”(hj¯  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÐhj«  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj¨  ubah}”(h]”h ]”h"]”h$]”h&]”jÎ  jÏ  uh1j}  hŸh¶h KÐhj  ubh¾)”}”(hŒVfor PXA3xx specific MFPR register bit definitions and PXA3xx common pin
configurations”h]”hŒVfor PXA3xx specific MFPR register bit definitions and PXA3xx common pin
configurations”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÒhj  ubj~  )”}”(hhh]”jN  )”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.h
”h]”h¾)”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.h”h]”hŒarch/arm/mach-pxa/mfp-pxa2xx.h”…””}”(hjÞ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÕhjÚ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj×  ubah}”(h]”h ]”h"]”h$]”h&]”jÎ  jÏ  uh1j}  hŸh¶h KÕhj  ubh¾)”}”(hŒKfor PXA2xx specific definitions and PXA25x/PXA27x common pin configurations”h]”hŒKfor PXA2xx specific definitions and PXA25x/PXA27x common pin configurations”…””}”(hjø  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h K×hj  ubj~  )”}”(hhh]”jN  )”}”(hŒ›arch/arm/mach-pxa/mfp-pxa25x.h
arch/arm/mach-pxa/mfp-pxa27x.h
arch/arm/mach-pxa/mfp-pxa300.h
arch/arm/mach-pxa/mfp-pxa320.h
arch/arm/mach-pxa/mfp-pxa930.h
”h]”h¾)”}”(hŒšarch/arm/mach-pxa/mfp-pxa25x.h
arch/arm/mach-pxa/mfp-pxa27x.h
arch/arm/mach-pxa/mfp-pxa300.h
arch/arm/mach-pxa/mfp-pxa320.h
arch/arm/mach-pxa/mfp-pxa930.h”h]”hŒšarch/arm/mach-pxa/mfp-pxa25x.h
arch/arm/mach-pxa/mfp-pxa27x.h
arch/arm/mach-pxa/mfp-pxa300.h
arch/arm/mach-pxa/mfp-pxa320.h
arch/arm/mach-pxa/mfp-pxa930.h”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KÙhj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj  ubah}”(h]”h ]”h"]”h$]”h&]”jÎ  jÏ  uh1j}  hŸh¶h KÙhj  ubh¾)”}”(hŒ"for processor specific definitions”h]”hŒ"for processor specific definitions”…””}”(hj'  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Kßhj  ubj~  )”}”(hhh]”(jN  )”}”(hŒarch/arm/mach-pxa/mfp-pxa3xx.c”h]”h¾)”}”(hj:  h]”hŒarch/arm/mach-pxa/mfp-pxa3xx.c”…””}”(hj<  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Káhj8  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj5  ubjN  )”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.c
”h]”h¾)”}”(hŒarch/arm/mach-pxa/mfp-pxa2xx.c”h]”hŒarch/arm/mach-pxa/mfp-pxa2xx.c”…””}”(hjS  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h KâhjO  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jM  hj5  ubeh}”(h]”h ]”h"]”h$]”h&]”jÎ  jÏ  uh1j}  hŸh¶h Káhj  ubh¾)”}”(hŒTfor implementation of the pin configuration to take effect for the actual
processor.”h]”hŒTfor implementation of the pin configuration to take effect for the actual
processor.”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Kähj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÊhj  hžhubeh}”(h]”Œfiles-involved”ah ]”h"]”Œfiles involved”ah$]”h&]”uh1h¡hjÛ  hžhhŸh¶h KÈubh¢)”}”(hhh]”(h§)”}”(hŒPin Configuration”h]”hŒPin Configuration”…””}”(hjŒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj‰  hžhhŸh¶h Kèubh¸)”}”(hXš  The following comments are copied from mfp.h (see the actual source code
for most updated info)::

  /*
   * a possible MFP configuration is represented by a 32-bit integer
   *
   * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
   * bit 10..12 - Alternate Function Selection
   * bit 13..15 - Drive Strength
   * bit 16..18 - Low Power Mode State
   * bit 19..20 - Low Power Mode Edge Detection
   * bit 21..22 - Run Mode Pull State
   *
   * to facilitate the definition, the following macros are provided
   *
   * MFP_CFG_DEFAULT - default MFP configuration value, with
   *            alternate function = 0,
   *            drive strength = fast 3mA (MFP_DS03X)
   *            low power mode = default
   *            edge detection = none
   *
   * MFP_CFG  - default MFPR value with alternate function
   * MFP_CFG_DRV      - default MFPR value with alternate function and
   *            pin drive strength
   * MFP_CFG_LPM      - default MFPR value with alternate function and
   *            low power mode
   * MFP_CFG_X        - default MFPR value with alternate function,
   *            pin drive strength and low power mode
   */

 Examples of pin configurations are::

   #define GPIO94_SSP3_RXD            MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)

 which reads GPIO94 can be configured as SSP3_RXD, with alternate function
 selection of 1, driving strength of 0b101, and a float state in low power
 modes.

 NOTE: this is the default setting of this pin being configured as SSP3_RXD
 which can be modified a bit in board code, though it is not recommended to
 do so, simply because this default setting is usually carefully encoded,
 and is supposed to work in most cases.
”h]”(h¾)”}”(hŒaThe following comments are copied from mfp.h (see the actual source code
for most updated info)::”h]”hŒ`The following comments are copied from mfp.h (see the actual source code
for most updated info):”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h Kêhjš  ubj  )”}”(hX   /*
  * a possible MFP configuration is represented by a 32-bit integer
  *
  * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
  * bit 10..12 - Alternate Function Selection
  * bit 13..15 - Drive Strength
  * bit 16..18 - Low Power Mode State
  * bit 19..20 - Low Power Mode Edge Detection
  * bit 21..22 - Run Mode Pull State
  *
  * to facilitate the definition, the following macros are provided
  *
  * MFP_CFG_DEFAULT - default MFP configuration value, with
  *            alternate function = 0,
  *            drive strength = fast 3mA (MFP_DS03X)
  *            low power mode = default
  *            edge detection = none
  *
  * MFP_CFG  - default MFPR value with alternate function
  * MFP_CFG_DRV      - default MFPR value with alternate function and
  *            pin drive strength
  * MFP_CFG_LPM      - default MFPR value with alternate function and
  *            low power mode
  * MFP_CFG_X        - default MFPR value with alternate function,
  *            pin drive strength and low power mode
  */

Examples of pin configurations are::

  #define GPIO94_SSP3_RXD            MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)

which reads GPIO94 can be configured as SSP3_RXD, with alternate function
selection of 1, driving strength of 0b101, and a float state in low power
modes.

NOTE: this is the default setting of this pin being configured as SSP3_RXD
which can be modified a bit in board code, though it is not recommended to
do so, simply because this default setting is usually carefully encoded,
and is supposed to work in most cases.”h]”hX   /*
  * a possible MFP configuration is represented by a 32-bit integer
  *
  * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
  * bit 10..12 - Alternate Function Selection
  * bit 13..15 - Drive Strength
  * bit 16..18 - Low Power Mode State
  * bit 19..20 - Low Power Mode Edge Detection
  * bit 21..22 - Run Mode Pull State
  *
  * to facilitate the definition, the following macros are provided
  *
  * MFP_CFG_DEFAULT - default MFP configuration value, with
  *            alternate function = 0,
  *            drive strength = fast 3mA (MFP_DS03X)
  *            low power mode = default
  *            edge detection = none
  *
  * MFP_CFG  - default MFPR value with alternate function
  * MFP_CFG_DRV      - default MFPR value with alternate function and
  *            pin drive strength
  * MFP_CFG_LPM      - default MFPR value with alternate function and
  *            low power mode
  * MFP_CFG_X        - default MFPR value with alternate function,
  *            pin drive strength and low power mode
  */

Examples of pin configurations are::

  #define GPIO94_SSP3_RXD            MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)

which reads GPIO94 can be configured as SSP3_RXD, with alternate function
selection of 1, driving strength of 0b101, and a float state in low power
modes.

NOTE: this is the default setting of this pin being configured as SSP3_RXD
which can be modified a bit in board code, though it is not recommended to
do so, simply because this default setting is usually carefully encoded,
and is supposed to work in most cases.”…””}”hj¬  sbah}”(h]”h ]”h"]”h$]”h&]”j&  j'  uh1j  hŸh¶h Kíhjš  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kêhj‰  hžhubeh}”(h]”Œpin-configuration”ah ]”h"]”Œpin configuration”ah$]”h&]”uh1h¡hjÛ  hžhhŸh¶h Kèubh¢)”}”(hhh]”(h§)”}”(hŒRegister Settings”h]”hŒRegister Settings”…””}”(hjË  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÈ  hžhhŸh¶h Mubh¸)”}”(hX  Register settings on PXA3xx for a pin configuration is actually very
straight-forward, most bits can be converted directly into MFPR value
in a easier way. Two sets of MFPR values are calculated: the run-time
ones and the low power mode ones, to allow different settings.

The conversion from a generic pin configuration to the actual register
settings on PXA2xx is a bit complicated: many registers are involved,
including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
mfp-pxa2xx.c for how the conversion is made.”h]”(h¾)”}”(hX  Register settings on PXA3xx for a pin configuration is actually very
straight-forward, most bits can be converted directly into MFPR value
in a easier way. Two sets of MFPR values are calculated: the run-time
ones and the low power mode ones, to allow different settings.”h]”hX  Register settings on PXA3xx for a pin configuration is actually very
straight-forward, most bits can be converted directly into MFPR value
in a easier way. Two sets of MFPR values are calculated: the run-time
ones and the low power mode ones, to allow different settings.”…””}”(hjÝ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h MhjÙ  ubh¾)”}”(hŒþThe conversion from a generic pin configuration to the actual register
settings on PXA2xx is a bit complicated: many registers are involved,
including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
mfp-pxa2xx.c for how the conversion is made.”h]”hŒþThe conversion from a generic pin configuration to the actual register
settings on PXA2xx is a bit complicated: many registers are involved,
including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
mfp-pxa2xx.c for how the conversion is made.”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h½hŸh¶h MhjÙ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjÈ  hžhubeh}”(h]”Œregister-settings”ah ]”h"]”Œregister settings”ah$]”h&]”uh1h¡hjÛ  hžhhŸh¶h Mubeh}”(h]”Œmfp-design-for-pxa2xx-pxa3xx”ah ]”h"]”Œmfp design for pxa2xx/pxa3xx”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K½ubeh}”(h]”Œ.mfp-configuration-for-pxa2xx-pxa3xx-processors”ah ]”h"]”Œ.mfp configuration for pxa2xx/pxa3xx processors”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j:  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j  j  j0  j-  j•  j’  jØ  jÕ  j  j	  j†  jƒ  jÅ  jÂ  j  j  uŒ	nametypes”}”(j  ‰j0  ‰j•  ‰jØ  ‰j  ‰j†  ‰jÅ  ‰j  ‰uh}”(j  h£j-  h÷j’  j3  jÕ  j˜  j	  jÛ  jƒ  j  jÂ  j‰  j  jÈ  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
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