Vsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/arch/arm/memorymodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/arch/arm/memorymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/arch/arm/memorymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/arch/arm/memorymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/arch/arm/memorymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/pt_BR/arch/arm/memorymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/arch/arm/memorymodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h!Kernel Memory Layout on ARM Linuxh]h!Kernel Memory Layout on ARM Linux}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/arch/arm/memory.rsthKubh block_quote)}(hERussell King November 17, 2005 (2.6.15) h](h paragraph)}(h#Russell King h](hRussell King <}(hhhhhNhNubh reference)}(hrmk@arm.linux.org.ukh]hrmk@arm.linux.org.uk}(hhhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:rmk@arm.linux.org.ukuh1hhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(hNovember 17, 2005 (2.6.15) h]h)}(hNovember 17, 2005 (2.6.15)h]hNovember 17, 2005 (2.6.15)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThis document describes the virtual memory layout which the Linux kernel uses for ARM processors. It indicates which regions are free for platforms to use, and which are used by generic code.h]hThis document describes the virtual memory layout which the Linux kernel uses for ARM processors. It indicates which regions are free for platforms to use, and which are used by generic code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hThe ARM CPU is capable of addressing a maximum of 4GB virtual memory space, and this must be shared between user space processes, the kernel, and hardware devices.h]hThe ARM CPU is capable of addressing a maximum of 4GB virtual memory space, and this must be shared between user space processes, the kernel, and hardware devices.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hAs the ARM architecture matures, it becomes necessary to reserve certain regions of VM space for use for new facilities; therefore this document may reserve more VM space over time.h]hAs the ARM architecture matures, it becomes necessary to reserve certain regions of VM space for use for new facilities; therefore this document may reserve more VM space over time.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jIhjFubjJ)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jIhjFubjJ)}(hhh]h}(h]h ]h"]h$]h&]colwidthK/uh1jIhjFubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hStarth]hStart}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjuubah}(h]h ]h"]h$]h&]uh1jshjpubjt)}(hhh]h)}(hEndh]hEnd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjpubjt)}(hhh]h)}(hUseh]hUse}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjpubeh}(h]h ]h"]h$]h&]uh1jnhjkubah}(h]h ]h"]h$]h&]uh1jihjFubhtbody)}(hhh](jo)}(hhh](jt)}(hhh]h)}(hffff8000h]hffff8000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hffffffffh]hffffffff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hgcopy_user_page / clear_user_page use. For SA11xx and Xscale, this is used to setup a minicache mapping.h]hgcopy_user_page / clear_user_page use. For SA11xx and Xscale, this is used to setup a minicache mapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hffff4000h]hffff4000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hffffffffh]hffffffff}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj3ubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(h'cache aliasing on ARMv6 and later CPUs.h]h'cache aliasing on ARMv6 and later CPUs.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hffff1000h]hffff1000}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjjubah}(h]h ]h"]h$]h&]uh1jshjgubjt)}(hhh]h)}(hffff7fffh]hffff7fff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjgubjt)}(hhh]h)}(h4Reserved. Platforms must not use this address range.h]h4Reserved. Platforms must not use this address range.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjgubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hffff0000h]hffff0000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hffff0fffh]hffff0fff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hpCPU vector page. The CPU vectors are mapped here if the CPU supports vector relocation (control register V bit.)h]hpCPU vector page. The CPU vectors are mapped here if the CPU supports vector relocation (control register V bit.)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hfffe0000h]hfffe0000}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hfffeffffh]hfffeffff}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hrXScale cache flush area. This is used in proc-xscale.S to flush the whole data cache. (XScale does not have TCM.)h]hrXScale cache flush area. This is used in proc-xscale.S to flush the whole data cache. (XScale does not have TCM.)}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hj4ubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hfffe8000h]hfffe8000}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjTubah}(h]h ]h"]h$]h&]uh1jshjQubjt)}(hhh]h)}(hfffeffffh]hfffeffff}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjkubah}(h]h ]h"]h$]h&]uh1jshjQubjt)}(hhh]h)}(hADTCM mapping area for platforms with DTCM mounted inside the CPU.h]hADTCM mapping area for platforms with DTCM mounted inside the CPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jshjQubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hfffe0000h]hfffe0000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hfffe7fffh]hfffe7fff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hAITCM mapping area for platforms with ITCM mounted inside the CPU.h]hAITCM mapping area for platforms with ITCM mounted inside the CPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hffc80000h]hffc80000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hffefffffh]hffefffff}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hQFixmap mapping region. Addresses provided by fix_to_virt() will be located here.h]hQFixmap mapping region. Addresses provided by fix_to_virt() will be located here.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hffc00000h]hffc00000}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hj>ubah}(h]h ]h"]h$]h&]uh1jshj;ubjt)}(hhh]h)}(hffc7ffffh]hffc7ffff}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjUubah}(h]h ]h"]h$]h&]uh1jshj;ubjt)}(hhh]h)}(h Guard regionh]h Guard region}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjlubah}(h]h ]h"]h$]h&]uh1jshj;ubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hff800000h]hff800000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hffbfffffh]hffbfffff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hCPermanent, fixed read-only mapping of the firmware provided DT blobh]hCPermanent, fixed read-only mapping of the firmware provided DT blob}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hfee00000h]hfee00000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hfeffffffh]hfeffffff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hLMapping of PCI I/O space. This is a static mapping within the vmalloc space.h]hLMapping of PCI I/O space. This is a static mapping within the vmalloc space.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h VMALLOC_STARTh]h VMALLOC_START}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj(ubah}(h]h ]h"]h$]h&]uh1jshj%ubjt)}(hhh]h)}(h VMALLOC_END-1h]h VMALLOC_END-1}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj?ubah}(h]h ]h"]h$]h&]uh1jshj%ubjt)}(hhh]h)}(hX$vmalloc() / ioremap() space. Memory returned by vmalloc/ioremap will be dynamically placed in this region. Machine specific static mappings are also located here through iotable_init(). VMALLOC_START is based upon the value of the high_memory variable, and VMALLOC_END is equal to 0xff800000.h]hX$vmalloc() / ioremap() space. Memory returned by vmalloc/ioremap will be dynamically placed in this region. Machine specific static mappings are also located here through iotable_init(). VMALLOC_START is based upon the value of the high_memory variable, and VMALLOC_END is equal to 0xff800000.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjVubah}(h]h ]h"]h$]h&]uh1jshj%ubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h PAGE_OFFSETh]h PAGE_OFFSET}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjvubah}(h]h ]h"]h$]h&]uh1jshjsubjt)}(hhh]h)}(h high_memory-1h]h high_memory-1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1jshjsubjt)}(hhh]h)}(hxKernel direct-mapped RAM region. This maps the platforms RAM, and typically maps all platform RAM in a 1:1 relationship.h]hxKernel direct-mapped RAM region. This maps the platforms RAM, and typically maps all platform RAM in a 1:1 relationship.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1jshjsubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h PKMAP_BASEh]h PKMAP_BASE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(h PAGE_OFFSET-1h]h PAGE_OFFSET-1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hMPermanent kernel mappings One way of mapping HIGHMEM pages into kernel space.h]hMPermanent kernel mappings One way of mapping HIGHMEM pages into kernel space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h MODULES_VADDRh]h MODULES_VADDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(h MODULES_END-1h]h MODULES_END-1}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj)ubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(h^Kernel module space Kernel modules inserted via insmod are placed here using dynamic mappings.h]h^Kernel module space Kernel modules inserted via insmod are placed here using dynamic mappings.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj@ubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h TASK_SIZEh]h TASK_SIZE}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhj`ubah}(h]h ]h"]h$]h&]uh1jshj]ubjt)}(hhh]h)}(hMODULES_VADDR-1h]hMODULES_VADDR-1}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjwubah}(h]h ]h"]h$]h&]uh1jshj]ubjt)}(hhh]h)}(hKASAn shadow memory when KASan is in use. The range from MODULES_VADDR to the top of the memory is shadowed here with 1 bit per byte of memory.h]hKASAn shadow memory when KASan is in use. The range from MODULES_VADDR to the top of the memory is shadowed here with 1 bit per byte of memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjubah}(h]h ]h"]h$]h&]uh1jshj]ubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h00001000h]h00001000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(h TASK_SIZE-1h]h TASK_SIZE-1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hSUser space mappings Per-thread mappings are placed here via the mmap() system call.h]hSUser space mappings Per-thread mappings are placed here via the mmap() system call.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(h00000000h]h00000000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(h00000fffh]h00000fff}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hCPU vector page / null pointer trap CPUs which do not support vector remapping place their vector page here. NULL pointer dereferences by both the kernel and user space are also caught via this mapping.h]hCPU vector page / null pointer trap CPUs which do not support vector remapping place their vector page here. NULL pointer dereferences by both the kernel and user space are also caught via this mapping.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhj*ubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]colsKuh1jDhjAubah}(h]h ]h"]h$]h&]uh1j?hhhhhhhNubh)}(hPlease note that mappings which collide with the above areas may result in a non-bootable kernel, or may cause the kernel to (eventually) panic at run time.h]hPlease note that mappings which collide with the above areas may result in a non-bootable kernel, or may cause the kernel to (eventually) panic at run time.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hhhhubh)}(hX Since future CPUs may impact the kernel mapping layout, user programs must not access any memory which is not mapped inside their 0x0001000 to TASK_SIZE address range. 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