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YEN SIGN h]h¥}hjLsbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h'Intel thermal throttle events reportingh]h'Intel thermal throttle events reporting}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj]hhhhhKubh field_list)}(hhh]hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jzhjwhhhKubh field_body)}(h:Srinivas Pandruvada h]h paragraph)}(h9Srinivas Pandruvada h](hSrinivas Pandruvada <}(hjhhhNhNubh reference)}(h#srinivas.pandruvada@linux.intel.comh]h#srinivas.pandruvada@linux.intel.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refuri*mailto:srinivas.pandruvada@linux.intel.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1juhhhKhjrhhubah}(h]h ]h"]h$]h&]uh1jphj]hhhhhKubj\)}(hhh](ja)}(h Introductionh]h Introduction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK ubj)}(hIntel processors have built in automatic and adaptive thermal monitoring mechanisms that force the processor to reduce its power consumption in order to operate within predetermined temperature limits.h]hIntel processors have built in automatic and adaptive thermal monitoring mechanisms that force the processor to reduce its power consumption in order to operate within predetermined temperature limits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK hjhhubj)}(hRefer to section "THERMAL MONITORING AND PROTECTION" in the "Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C, & 3D): System Programming Guide" for more details.h]hRefer to section “THERMAL MONITORING AND PROTECTION” in the “Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C, & 3D): System Programming Guide” for more details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hIn general, there are two mechanisms to control the core temperature of the processor. They are called "Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2)".h]hIn general, there are two mechanisms to control the core temperature of the processor. They are called “Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2)”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hThe status of the temperature sensor that triggers the thermal monitor (TM1/TM2) is indicated through the "thermal status flag" and "thermal status log flag" in MSR_IA32_THERM_STATUS for core level and MSR_IA32_PACKAGE_THERM_STATUS for package level.h]hXThe status of the temperature sensor that triggers the thermal monitor (TM1/TM2) is indicated through the “thermal status flag” and “thermal status log flag” in MSR_IA32_THERM_STATUS for core level and MSR_IA32_PACKAGE_THERM_STATUS for package level.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXThermal Status flag, bit 0 — When set, indicates that the processor core temperature is currently at the trip temperature of the thermal monitor and that the processor power consumption is being reduced via either TM1 or TM2, depending on which is enabled. When clear, the flag indicates that the core temperature is below the thermal monitor trip temperature. This flag is read only.h]hXThermal Status flag, bit 0 — When set, indicates that the processor core temperature is currently at the trip temperature of the thermal monitor and that the processor power consumption is being reduced via either TM1 or TM2, depending on which is enabled. When clear, the flag indicates that the core temperature is below the thermal monitor trip temperature. This flag is read only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXKThermal Status Log flag, bit 1 — When set, indicates that the thermal sensor has tripped since the last power-up or reset or since the last time that software cleared this flag. This flag is a sticky bit; once set it remains set until cleared by software or until a power-up or reset of the processor. The default state is clear.h]hXKThermal Status Log flag, bit 1 — When set, indicates that the thermal sensor has tripped since the last power-up or reset or since the last time that software cleared this flag. This flag is a sticky bit; once set it remains set until cleared by software or until a power-up or reset of the processor. The default state is clear.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK#hjhhubj)}(hXqIt is possible that when user reads MSR_IA32_THERM_STATUS or MSR_IA32_PACKAGE_THERM_STATUS, TM1/TM2 is not active. In this case, "Thermal Status flag" will read "0" and the "Thermal Status Log flag" will be set to show any previous "TM1/TM2" activation. But since it needs to be cleared by the software, it can't show the number of occurrences of "TM1/TM2" activations.h]hXIt is possible that when user reads MSR_IA32_THERM_STATUS or MSR_IA32_PACKAGE_THERM_STATUS, TM1/TM2 is not active. In this case, “Thermal Status flag” will read “0” and the “Thermal Status Log flag” will be set to show any previous “TM1/TM2” activation. But since it needs to be cleared by the software, it can’t show the number of occurrences of “TM1/TM2” activations.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK)hjhhubj)}(hXHence, Linux provides counters of how many times the "Thermal Status flag" was set. Also presents how long the "Thermal Status flag" was active in milliseconds. Using these counters, users can check if the performance was limited because of thermal events. It is recommended to read from sysfs instead of directly reading MSRs as the "Thermal Status Log flag" is reset by the driver to implement rate control.h]hXHence, Linux provides counters of how many times the “Thermal Status flag” was set. Also presents how long the “Thermal Status flag” was active in milliseconds. Using these counters, users can check if the performance was limited because of thermal events. It is recommended to read from sysfs instead of directly reading MSRs as the “Thermal Status Log flag” is reset by the driver to implement rate control.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK/hjhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1j[hj]hhhhhK ubj\)}(hhh](ja)}(hSysfs Interfaceh]hSysfs Interface}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjQhhhhhK7ubj)}(hThermal throttling events are presented for each CPU under "/sys/devices/system/cpu/cpuX/thermal_throttle/", where "X" is the CPU number.h]hThermal throttling events are presented for each CPU under “/sys/devices/system/cpu/cpuX/thermal_throttle/”, where “X” is the CPU number.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK9hjQhhubj)}(hAll these counters are read-only. They can't be reset to 0. So, they can potentially overflow after reaching the maximum 64 bit unsigned integer.h]hAll these counters are read-only. They can’t be reset to 0. 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