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YEN SIGN h]h¥}hjLsbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h.``intel_idle`` CPU Idle Time Management Driverh](hliteral)}(h``intel_idle``h]h intel_idle}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjbubh CPU Idle Time Management Driver}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1j`hj]hhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubh field_body)}(h|copy| 2020 Intel Corporation h]h paragraph)}(h|copy| 2020 Intel Corporationh](h©}(hjhhhNhNubh 2020 Intel Corporation}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hhh](j)}(hAuthorh]hAuthor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj)}(h0Rafael J. Wysocki h]j)}(h.Rafael J. Wysocki h](hRafael J. Wysocki <}(hjhhhNhNubh reference)}(hrafael.j.wysocki@intel.comh]hrafael.j.wysocki@intel.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refuri!mailto:rafael.j.wysocki@intel.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK hjhhubeh}(h]h ]h"]h$]h&]uh1jhj]hhhhhKubj\)}(hhh](ja)}(hGeneral Informationh]hGeneral Information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hXr``intel_idle`` is a part of the :doc:`CPU idle time management subsystem ` in the Linux kernel (``CPUIdle``). It is the default CPU idle time management driver for the Nehalem and later generations of Intel processors, but the level of support for a particular processor model in it depends on whether or not it recognizes that processor model and may also depend on information coming from the platform firmware. [To understand ``intel_idle`` it is necessary to know how ``CPUIdle`` works in general, so this is the time to get familiar with Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]h](jg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh is a part of the }(hjhhhNhNubh)}(h3:doc:`CPU idle time management subsystem `h]hinline)}(hj4h]h"CPU idle time management subsystem}(hj8hhhNhNubah}(h]h ](xrefstdstd-doceh"]h$]h&]uh1j6hj2ubah}(h]h ]h"]h$]h&]refdocadmin-guide/pm/intel_idle refdomainjCreftypedoc refexplicitrefwarn reftargetcpuidleuh1hhhhKhjubh in the Linux kernel (}(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhXD). It is the default CPU idle time management driver for the Nehalem and later generations of Intel processors, but the level of support for a particular processor model in it depends on whether or not it recognizes that processor model and may also depend on information coming from the platform firmware. [To understand }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh it is necessary to know how }(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh works in general, so this is the time to get familiar with Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hX``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the logical CPU executing it is idle and so it may be possible to put some of the processor's functional blocks into low-power states. That instruction takes two arguments (passed in the ``EAX`` and ``ECX`` registers of the target CPU), the first of which, referred to as a *hint*, can be used by the processor to determine what can be done (for details refer to Intel Software Developer’s Manual [1]_). Accordingly, ``intel_idle`` refuses to work with processors in which the support for the ``MWAIT`` instruction has been disabled (for example, via the platform firmware configuration menu) or which do not support that instruction at all.h](jg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh uses the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh instruction to inform the processor that the logical CPU executing it is idle and so it may be possible to put some of the processor’s functional blocks into low-power states. That instruction takes two arguments (passed in the }(hjhhhNhNubjg)}(h``EAX``h]hEAX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh and }(hjhhhNhNubjg)}(h``ECX``h]hECX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhD registers of the target CPU), the first of which, referred to as a }(hjhhhNhNubhemphasis)}(h*hint*h]hhint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhw, can be used by the processor to determine what can be done (for details refer to Intel Software Developer’s Manual }(hjhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hjhhhNhNubah}(h]id1ah ]h"]h$]h&]refidid3docnamejOuh1jhjresolvedKubh). Accordingly, }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh> refuses to work with processors in which the support for the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh instruction has been disabled (for example, via the platform firmware configuration menu) or which do not support that instruction at all.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(h``intel_idle`` is not modular, so it cannot be unloaded, which means that the only way to pass early-configuration-time parameters to it is via the kernel command line.h](jg)}(h``intel_idle``h]h intel_idle}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj:ubh is not modular, so it cannot be unloaded, which means that the only way to pass early-configuration-time parameters to it is via the kernel command line.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK%hj hhubeh}(h]general-informationah ]h"]general informationah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(hSysfs Interfaceh]hSysfs Interface}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj^hhhhhK*ubj)}(hmThe ``intel_idle`` driver exposes the following ``sysfs`` attributes in ``/sys/devices/system/cpu/cpuidle/``:h](hThe }(hjohhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjoubh driver exposes the following }(hjohhhNhNubjg)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjoubh attributes in }(hjohhhNhNubjg)}(h$``/sys/devices/system/cpu/cpuidle/``h]h /sys/devices/system/cpu/cpuidle/}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjoubh:}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK,hj^hhubhdefinition_list)}(hhh]hdefinition_list_item)}(hXp``intel_c1_demotion`` Enable or disable C1 demotion for all CPUs in the system. This file is only exposed on platforms that support the C1 demotion feature and where it was tested. Value 0 means that C1 demotion is disabled, value 1 means that it is enabled. Write 0 or 1 to disable or enable C1 demotion for all CPUs. The C1 demotion feature involves the platform firmware demoting deep C-state requests from the OS (e.g., C6 requests) to C1. The idea is that firmware monitors CPU wake-up rate, and if it is higher than a platform-specific threshold, the firmware demotes deep C-state requests to C1. For example, Linux requests C6, but firmware noticed too many wake-ups per second, and it keeps the CPU in C1. When the CPU stays in C1 long enough, the platform promotes it back to C6. This may improve some workloads' performance, but it may also increase power consumption. h](hterm)}(h``intel_c1_demotion``h]jg)}(hjh]hintel_c1_demotion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&]uh1jhhhK=hjubh definition)}(hhh](j)}(hX(Enable or disable C1 demotion for all CPUs in the system. This file is only exposed on platforms that support the C1 demotion feature and where it was tested. Value 0 means that C1 demotion is disabled, value 1 means that it is enabled. Write 0 or 1 to disable or enable C1 demotion for all CPUs.h]hX(Enable or disable C1 demotion for all CPUs in the system. This file is only exposed on platforms that support the C1 demotion feature and where it was tested. Value 0 means that C1 demotion is disabled, value 1 means that it is enabled. Write 0 or 1 to disable or enable C1 demotion for all CPUs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK0hjubj)}(hX/The C1 demotion feature involves the platform firmware demoting deep C-state requests from the OS (e.g., C6 requests) to C1. The idea is that firmware monitors CPU wake-up rate, and if it is higher than a platform-specific threshold, the firmware demotes deep C-state requests to C1. For example, Linux requests C6, but firmware noticed too many wake-ups per second, and it keeps the CPU in C1. When the CPU stays in C1 long enough, the platform promotes it back to C6. This may improve some workloads' performance, but it may also increase power consumption.h]hX1The C1 demotion feature involves the platform firmware demoting deep C-state requests from the OS (e.g., C6 requests) to C1. The idea is that firmware monitors CPU wake-up rate, and if it is higher than a platform-specific threshold, the firmware demotes deep C-state requests to C1. For example, Linux requests C6, but firmware noticed too many wake-ups per second, and it keeps the CPU in C1. When the CPU stays in C1 long enough, the platform promotes it back to C6. This may improve some workloads’ performance, but it may also increase power consumption.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK6hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK=hjubah}(h]h ]h"]h$]h&]uh1jhj^hhhhhNubhtarget)}(h%.. _intel-idle-enumeration-of-states:h]h}(h]h ]h"]h$]h&]j intel-idle-enumeration-of-statesuh1j hKhj^hhhhnj referencedKubeh}(h]sysfs-interfaceah ]h"]sysfs interfaceah$]h&]uh1j[hj]hhhhhK*ubj\)}(hhh](ja)}(hEnumeration of Idle Statesh]hEnumeration of Idle States}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKBubj)}(hXEach ``MWAIT`` hint value is interpreted by the processor as a license to reconfigure itself in a certain way in order to save energy. The processor configurations (with reduced power draw) resulting from that are referred to as C-states (in the ACPI terminology) or idle states. The list of meaningful ``MWAIT`` hint values and idle states (i.e. low-power configurations of the processor) corresponding to them depends on the processor model and it may also depend on the configuration of the platform.h](hEach }(hj1hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj1ubhX# hint value is interpreted by the processor as a license to reconfigure itself in a certain way in order to save energy. The processor configurations (with reduced power draw) resulting from that are referred to as C-states (in the ACPI terminology) or idle states. The list of meaningful }(hj1hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj1ubh hint values and idle states (i.e. low-power configurations of the processor) corresponding to them depends on the processor model and it may also depend on the configuration of the platform.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKDhj hhubj)}(hX(In order to create a list of available idle states required by the ``CPUIdle`` subsystem (see :ref:`idle-states-representation` in Documentation/admin-guide/pm/cpuidle.rst), ``intel_idle`` can use two sources of information: static tables of idle states for different processor models included in the driver itself and the ACPI tables of the system. The former are always used if the processor model at hand is recognized by ``intel_idle`` and the latter are used if that is required for the given processor model (which is the case for all server processor models recognized by ``intel_idle``) or if the processor model is not recognized. [There is a module parameter that can be used to make the driver use the ACPI tables with any processor model recognized by it; see `below `_.]h](hCIn order to create a list of available idle states required by the }(hjchhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjcubh subsystem (see }(hjchhhNhNubh)}(h!:ref:`idle-states-representation`h]j7)}(hjh]hidle-states-representation}(hjhhhNhNubah}(h]h ](jBstdstd-refeh"]h$]h&]uh1j6hj}ubah}(h]h ]h"]h$]h&]refdocjO refdomainjreftyperef refexplicitrefwarnjUidle-states-representationuh1hhhhKLhjcubh/ in Documentation/admin-guide/pm/cpuidle.rst), }(hjchhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjcubh can use two sources of information: static tables of idle states for different processor models included in the driver itself and the ACPI tables of the system. The former are always used if the processor model at hand is recognized by }(hjchhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjcubh and the latter are used if that is required for the given processor model (which is the case for all server processor models recognized by }(hjchhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjcubh) or if the processor model is not recognized. [There is a module parameter that can be used to make the driver use the ACPI tables with any processor model recognized by it; see }(hjchhhNhNubj)}(h!`below `_h]hbelow}(hjhhhNhNubah}(h]h ]h"]h$]h&]namebelowjintel-idle-parametersuh1jhjcj Kubj )}(h h]h}(h]h ]h"]belowah$]h&]jjuh1j indirect_reference_nameintel-idle-parametershjcj Kubh.]}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKLhj hhubj)}(hXVIf the ACPI tables are going to be used for building the list of available idle states, ``intel_idle`` will be looking for ``_LPI`` or ``_CST`` objects in them (refer to the ACPI specification [2]_ for the definitions of the ``_LPI`` and ``_CST`` objects). If ``_LPI`` is present under at least one of the ACPI objects representing the CPUs in the system and ``_LPI`` processing produces a non-empty list of valid idle states, it will be used. Otherwise, ``_CST`` will be used so long as it is present under at least one of the ACPI objects representing the CPUs in the system and it returns a non-empty list of valid idle states. In either case, since the ``CPUIdle`` subsystem expects that the list of idle states supplied by the driver will be suitable for all of the CPUs handled by it and ``intel_idle`` is registered as the ``CPUIdle`` driver for all of the CPUs in the system, ``intel_idle`` looks for the first CPU where the ACPI-supplied list of idle states (coming from either ``_LPI`` or ``_CST``) is not empty. Moreover, all of the states in that list need to be of the FFH (Functional Fixed Hardware) type, which means that the ``MWAIT`` instruction is expected to be used to tell the processor that the given idle state may be entered. If that expectation is met, the list of idle states is assumed to be applicable to all of the other CPUs in the system and the idle state descriptions extracted from it are stored in a preliminary list of idle states coming from the ACPI tables. [This step is skipped if ``intel_idle`` is configured to ignore the ACPI tables; see `below `_.]h](hXIf the ACPI tables are going to be used for building the list of available idle states, }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh will be looking for }(hjhhhNhNubjg)}(h``_LPI``h]h_LPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh or }(hjhhhNhNubjg)}(h``_CST``h]h_CST}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh2 objects in them (refer to the ACPI specification }(hjhhhNhNubj)}(h[2]_h]h2}(hj= hhhNhNubah}(h]id2ah ]h"]h$]h&]jid4j jOuh1jhjj Kubh for the definitions of the }(hjhhhNhNubjg)}(h``_LPI``h]h_LPI}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh and }(hjhhhNhNubjg)}(h``_CST``h]h_CST}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh objects). If }(hjhhhNhNubjg)}(h``_LPI``h]h_LPI}(hju hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh[ is present under at least one of the ACPI objects representing the CPUs in the system and }(hjhhhNhNubjg)}(h``_LPI``h]h_LPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhY processing produces a non-empty list of valid idle states, it will be used. Otherwise, }(hjhhhNhNubjg)}(h``_CST``h]h_CST}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh will be used so long as it is present under at least one of the ACPI objects representing the CPUs in the system and it returns a non-empty list of valid idle states. In either case, since the }(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh~ subsystem expects that the list of idle states supplied by the driver will be suitable for all of the CPUs handled by it and }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh is registered as the }(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh+ driver for all of the CPUs in the system, }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhY looks for the first CPU where the ACPI-supplied list of idle states (coming from either }(hjhhhNhNubjg)}(h``_LPI``h]h_LPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh or }hjsbjg)}(h``_CST``h]h_CST}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh) is not empty. Moreover, all of the states in that list need to be of the FFH (Functional Fixed Hardware) type, which means that the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhXu instruction is expected to be used to tell the processor that the given idle state may be entered. If that expectation is met, the list of idle states is assumed to be applicable to all of the other CPUs in the system and the idle state descriptions extracted from it are stored in a preliminary list of idle states coming from the ACPI tables. [This step is skipped if }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh. is configured to ignore the ACPI tables; see }(hjhhhNhNubj)}(h!`below `_h]hbelow}(hj; hhhNhNubah}(h]h ]h"]h$]h&]namebelowjjuh1jhjj Kubj )}(h h]h}(h]h ]h"]belowah$]h&]jjuh1j jintel-idle-parametershjj Kubh.]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKYhj hhubj)}(hXNext, the first (index 0) entry in the list of available idle states is initialized to represent a "polling idle state" (a pseudo-idle state in which the target CPU continuously fetches and executes instructions), and the subsequent (real) idle state entries are populated as follows.h]hX Next, the first (index 0) entry in the list of available idle states is initialized to represent a “polling idle state” (a pseudo-idle state in which the target CPU continuously fetches and executes instructions), and the subsequent (real) idle state entries are populated as follows.}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKohj hhubj)}(hXIf the processor model at hand is recognized by ``intel_idle``, there is a (static) table of idle state descriptions for it in the driver. In that case, the "internal" table is the primary source of information on idle states and the information from it is copied to the final list of available idle states. If using the ACPI tables for the enumeration of idle states is not required (depending on the processor model), all of the listed idle state are enabled by default (so all of them will be taken into consideration by ``CPUIdle`` governors during CPU idle state selection). Otherwise, some of the listed idle states may not be enabled by default if there are no matching entries in the preliminary list of idle states coming from the ACPI tables. In that case user space still can enable them later (on a per-CPU basis) with the help of the ``disable`` idle state attribute in ``sysfs`` (see :ref:`idle-states-representation` in Documentation/admin-guide/pm/cpuidle.rst). This basically means that the idle states "known" to the driver may not be enabled by default if they have not been exposed by the platform firmware (through the ACPI tables).h](h0If the processor model at hand is recognized by }(hjo hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjo ubhX, there is a (static) table of idle state descriptions for it in the driver. In that case, the “internal” table is the primary source of information on idle states and the information from it is copied to the final list of available idle states. If using the ACPI tables for the enumeration of idle states is not required (depending on the processor model), all of the listed idle state are enabled by default (so all of them will be taken into consideration by }(hjo hhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjo ubhX: governors during CPU idle state selection). Otherwise, some of the listed idle states may not be enabled by default if there are no matching entries in the preliminary list of idle states coming from the ACPI tables. In that case user space still can enable them later (on a per-CPU basis) with the help of the }(hjo hhhNhNubjg)}(h ``disable``h]hdisable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjo ubh idle state attribute in }(hjo hhhNhNubjg)}(h ``sysfs``h]hsysfs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjo ubh (see }(hjo hhhNhNubh)}(h!:ref:`idle-states-representation`h]j7)}(hj h]hidle-states-representation}(hj hhhNhNubah}(h]h ](jBstdstd-refeh"]h$]h&]uh1j6hj ubah}(h]h ]h"]h$]h&]refdocjO refdomainj reftyperef refexplicitrefwarnjUidle-states-representationuh1hhhhKthjo ubh in Documentation/admin-guide/pm/cpuidle.rst). This basically means that the idle states “known” to the driver may not be enabled by default if they have not been exposed by the platform firmware (through the ACPI tables).}(hjo hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKthj hhubj)}(hXIf the given processor model is not recognized by ``intel_idle``, but it supports ``MWAIT``, the preliminary list of idle states coming from the ACPI tables is used for building the final list that will be supplied to the ``CPUIdle`` core during driver registration. For each idle state in that list, the description, ``MWAIT`` hint and exit (wake) latency are copied to the corresponding entry in the final list of idle states. If the preliminary list of idle states has been obtained through ``_LPI`` processing, the minimum residency parameter of the given idle state is taken as its target residency. Otherwise, for C1-type idle states, the exit latency value is also used as the target residency (for compatibility with the majority of the "internal" tables of idle states for various processor models recognized by ``intel_idle``), and for the other idle state types (C2 and C3) the target residency value is 3 times the exit latency (again, that is because it reflects the target residency to exit latency ratio in the majority of cases for the processor models recognized by ``intel_idle``). The name of the idle state (to be returned by the ``name`` idle state attribute in ``sysfs``) is either "Cx_LPI" (if it comes from ``_LPI`` processing) or "Cx_ACPI", where x is the index of that idle state in the final list (note that the minimum value of x is 1, because 0 is reserved for the "polling" state), and its target residency is based on the exit latency value. All of the idle states in the final list are enabled by default in this case.h](h2If the given processor model is not recognized by }(hj hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh, but it supports }(hj hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh, the preliminary list of idle states coming from the ACPI tables is used for building the final list that will be supplied to the }(hj hhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhV core during driver registration. For each idle state in that list, the description, }(hj hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh hint and exit (wake) latency are copied to the corresponding entry in the final list of idle states. If the preliminary list of idle states has been obtained through }(hj hhhNhNubjg)}(h``_LPI``h]h_LPI}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhXC processing, the minimum residency parameter of the given idle state is taken as its target residency. Otherwise, for C1-type idle states, the exit latency value is also used as the target residency (for compatibility with the majority of the “internal” tables of idle states for various processor models recognized by }(hj hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh), and for the other idle state types (C2 and C3) the target residency value is 3 times the exit latency (again, that is because it reflects the target residency to exit latency ratio in the majority of cases for the processor models recognized by }(hj hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh6). The name of the idle state (to be returned by the }(hj hhhNhNubjg)}(h``name``h]hname}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh idle state attribute in }(hj hhhNhNubjg)}(h ``sysfs``h]hsysfs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh+) is either “Cx_LPI” (if it comes from }(hj hhhNhNubjg)}(h``_LPI``h]h_LPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhX? processing) or “Cx_ACPI”, where x is the index of that idle state in the final list (note that the minimum value of x is 1, because 0 is reserved for the “polling” state), and its target residency is based on the exit latency value. All of the idle states in the final list are enabled by default in this case.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj )}(h.. _intel-idle-initialization:h]h}(h]h ]h"]h$]h&]jintel-idle-initializationuh1j hKhj hhhhubeh}(h](enumeration-of-idle-statesjeh ]h"](enumeration of idle states intel-idle-enumeration-of-stateseh$]h&]uh1j[hj]hhhhhKBexpect_referenced_by_name}j j sexpect_referenced_by_id}jj sjKubj\)}(hhh](ja)}(hInitializationh]hInitialization}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hThe initialization of ``intel_idle`` starts with checking if the kernel command line options forbid the use of the ``MWAIT`` instruction. If that is the case, an error code is returned right away.h](hThe initialization of }(hj hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhO starts with checking if the kernel command line options forbid the use of the }(hj hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhI instruction. If that is the case, an error code is returned right away.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hX The next step is to check whether or not the processor model is known to the driver, which determines the idle states enumeration method (see `above `_), and whether or not the processor supports ``MWAIT`` (the initialization fails if that is not the case). Then, the ``MWAIT`` support in the processor is enumerated through ``CPUID`` and the driver initialization fails if the level of support is not as expected (for example, if the total number of ``MWAIT`` substates returned is 0).h](hThe next step is to check whether or not the processor model is known to the driver, which determines the idle states enumeration method (see }(hj hhhNhNubj)}(h,`above `_h]habove}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameabovejjuh1jhj j Kubj )}(h$ h]h}(h]h ]h"]aboveah$]h&]jjuh1j j intel-idle-enumeration-of-stateshj j Kubh-), and whether or not the processor supports }(hj hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh@ (the initialization fails if that is not the case). Then, the }(hj hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh0 support in the processor is enumerated through }(hj hhhNhNubjg)}(h ``CPUID``h]hCPUID}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhu and the driver initialization fails if the level of support is not as expected (for example, if the total number of }(hj hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh substates returned is 0).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hNext, if the driver is not configured to ignore the ACPI tables (see `below `_), the idle states information provided by the platform firmware is extracted from them.h](hENext, if the driver is not configured to ignore the ACPI tables (see }(hj| hhhNhNubj)}(h!`below `_h]hbelow}(hj hhhNhNubah}(h]h ]h"]h$]h&]namebelowjjuh1jhj| j Kubj )}(h h]h}(h]h ]h"]belowah$]h&]jjuh1j jintel-idle-parametershj| j KubhX), the idle states information provided by the platform firmware is extracted from them.}(hj| hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hThen, ``CPUIdle`` device objects are allocated for all CPUs and the list of available idle states is created as explained `above `_.h](hThen, }(hj hhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhi device objects are allocated for all CPUs and the list of available idle states is created as explained }(hj hhhNhNubj)}(h,`above `_h]habove}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameabovejjuh1jhj j Kubj )}(h$ h]h}(h]h ]h"]aboveah$]h&]jjuh1j j intel-idle-enumeration-of-stateshj j Kubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hXFinally, ``intel_idle`` is registered with the help of cpuidle_register_driver() as the ``CPUIdle`` driver for all CPUs in the system and a CPU online callback for configuring individual CPUs is registered via cpuhp_setup_state(), which (among other things) causes the callback routine to be invoked for all of the CPUs present in the system at that time (each CPU executes its own instance of the callback routine). That routine registers a ``CPUIdle`` device for the CPU running it (which enables the ``CPUIdle`` subsystem to operate that CPU) and optionally performs some CPU-specific initialization actions that may be required for the given processor model.h](h Finally, }(hj hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhA is registered with the help of cpuidle_register_driver() as the }(hj hhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubhXX driver for all CPUs in the system and a CPU online callback for configuring individual CPUs is registered via cpuhp_setup_state(), which (among other things) causes the callback routine to be invoked for all of the CPUs present in the system at that time (each CPU executes its own instance of the callback routine). That routine registers a }(hj hhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh2 device for the CPU running it (which enables the }(hj hhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh subsystem to operate that CPU) and optionally performs some CPU-specific initialization actions that may be required for the given processor model.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj )}(h.. _intel-idle-parameters:h]h}(h]h ]h"]h$]h&]jjuh1j hMhj hhhhjKubeh}(h](initializationj eh ]h"](initializationintel-idle-initializationeh$]h&]uh1j[hj]hhhhhKj }jP j sj }j j subj\)}(hhh](ja)}(h1Kernel Command Line Options and Module Parametersh]h1Kernel Command Line Options and Module Parameters}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjU hhhhhKubj)}(hXHThe *x86* architecture support code recognizes three kernel command line options related to CPU idle time management: ``idle=poll``, ``idle=halt``, and ``idle=nomwait``. If any of them is present in the kernel command line, the ``MWAIT`` instruction is not allowed to be used, so the initialization of ``intel_idle`` will fail.h](hThe }(hjf hhhNhNubj)}(h*x86*h]hx86}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf ubhm architecture support code recognizes three kernel command line options related to CPU idle time management: }(hjf hhhNhNubjg)}(h ``idle=poll``h]h idle=poll}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjf ubh, }(hjf hhhNhNubjg)}(h ``idle=halt``h]h idle=halt}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjf ubh, and }(hjf hhhNhNubjg)}(h``idle=nomwait``h]h idle=nomwait}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjf ubh=. If any of them is present in the kernel command line, the }(hjf hhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjf ubhA instruction is not allowed to be used, so the initialization of }(hjf hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjf ubh will fail.}(hjf hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hApart from that there are five module parameters recognized by ``intel_idle`` itself that can be set via the kernel command line (they cannot be updated via sysfs, so that is the only way to change their values).h](h?Apart from that there are five module parameters recognized by }(hj hhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj ubh itself that can be set via the kernel command line (they cannot be updated via sysfs, so that is the only way to change their values).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hXThe ``max_cstate`` parameter value is the maximum idle state index in the list of idle states supplied to the ``CPUIdle`` core during the registration of the driver. It is also the maximum number of regular (non-polling) idle states that can be used by ``intel_idle``, so the enumeration of idle states is terminated after finding that number of usable idle states (the other idle states that potentially might have been used if ``max_cstate`` had been greater are not taken into consideration at all). Setting ``max_cstate`` can prevent ``intel_idle`` from exposing idle states that are regarded as "too deep" for some reason to the ``CPUIdle`` core, but it does so by making them effectively invisible until the system is shut down and started again which may not always be desirable. In practice, it is only really necessary to do that if the idle states in question cannot be enabled during system startup, because in the working state of the system the CPU power management quality of service (PM QoS) feature can be used to prevent ``CPUIdle`` from touching those idle states even if they have been enumerated (see :ref:`cpu-pm-qos` in Documentation/admin-guide/pm/cpuidle.rst). Setting ``max_cstate`` to 0 causes the ``intel_idle`` initialization to fail.h](hThe }(hjhhhNhNubjg)}(h``max_cstate``h]h max_cstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh\ parameter value is the maximum idle state index in the list of idle states supplied to the }(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh core during the registration of the driver. It is also the maximum number of regular (non-polling) idle states that can be used by }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh, so the enumeration of idle states is terminated after finding that number of usable idle states (the other idle states that potentially might have been used if }(hjhhhNhNubjg)}(h``max_cstate``h]h max_cstate}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhE had been greater are not taken into consideration at all). Setting }(hjhhhNhNubjg)}(h``max_cstate``h]h max_cstate}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh can prevent }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhV from exposing idle states that are regarded as “too deep” for some reason to the }(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhX core, but it does so by making them effectively invisible until the system is shut down and started again which may not always be desirable. In practice, it is only really necessary to do that if the idle states in question cannot be enabled during system startup, because in the working state of the system the CPU power management quality of service (PM QoS) feature can be used to prevent }(hjhhhNhNubjg)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhH from touching those idle states even if they have been enumerated (see }(hjhhhNhNubh)}(h:ref:`cpu-pm-qos`h]j7)}(hjh]h cpu-pm-qos}(hjhhhNhNubah}(h]h ](jBstdstd-refeh"]h$]h&]uh1j6hjubah}(h]h ]h"]h$]h&]refdocjO refdomainjreftyperef refexplicitrefwarnjU cpu-pm-qosuh1hhhhKhjubh7 in Documentation/admin-guide/pm/cpuidle.rst). Setting }(hjhhhNhNubjg)}(h``max_cstate``h]h max_cstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh to 0 causes the }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh initialization to fail.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hThe ``no_acpi``, ``use_acpi`` and ``no_native`` module parameters are recognized by ``intel_idle`` if the kernel has been configured with ACPI support. In the case that ACPI is not configured these flags have no impact on functionality.h](hThe }(hjhhhNhNubjg)}(h ``no_acpi``h]hno_acpi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh, }(hjhhhNhNubjg)}(h ``use_acpi``h]huse_acpi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh and }(hjhhhNhNubjg)}(h ``no_native``h]h no_native}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh% module parameters are recognized by }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh if the kernel has been configured with ACPI support. In the case that ACPI is not configured these flags have no impact on functionality.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hS``no_acpi`` - Do not use ACPI at all. Only native mode is available, no ACPI mode.h](jg)}(h ``no_acpi``h]hno_acpi}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj<ubhH - Do not use ACPI at all. Only native mode is available, no ACPI mode.}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hq``use_acpi`` - No-op in ACPI mode, the driver will consult ACPI tables for C-states on/off status in native mode.h](jg)}(h ``use_acpi``h]huse_acpi}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjXubhe - No-op in ACPI mode, the driver will consult ACPI tables for C-states on/off status in native mode.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(h\``no_native`` - Work only in ACPI mode, no native mode available (ignore all custom tables).h](jg)}(h ``no_native``h]h no_native}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjtubhO - Work only in ACPI mode, no native mode available (ignore all custom tables).}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hThe value of the ``states_off`` module parameter (0 by default) represents a list of idle states to be disabled by default in the form of a bitmask.h](hThe value of the }(hjhhhNhNubjg)}(h``states_off``h]h states_off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhu module parameter (0 by default) represents a list of idle states to be disabled by default in the form of a bitmask.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hXNamely, the positions of the bits that are set in the ``states_off`` value are the indices of idle states to be disabled by default (as reflected by the names of the corresponding idle state directories in ``sysfs``, :file:`state0`, :file:`state1` ... :file:`state` ..., where ```` is the index of the given idle state; see :ref:`idle-states-representation` in Documentation/admin-guide/pm/cpuidle.rst).h](h6Namely, the positions of the bits that are set in the }(hjhhhNhNubjg)}(h``states_off``h]h states_off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh value are the indices of idle states to be disabled by default (as reflected by the names of the corresponding idle state directories in }(hjhhhNhNubjg)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh, }(hjhhhNhNubjg)}(h:file:`state0`h]hstate0}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jfhjubh, }(hjhhhNhNubjg)}(h:file:`state1`h]hstate1}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jfhjubh ... }(hjhhhNhNubjg)}(h:file:`state`h]hstate}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jfhjubh ..., where }(hjhhhNhNubjg)}(h````h]h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh+ is the index of the given idle state; see }(hjhhhNhNubh)}(h!:ref:`idle-states-representation`h]j7)}(hj/h]hidle-states-representation}(hj1hhhNhNubah}(h]h ](jBstdstd-refeh"]h$]h&]uh1j6hj-ubah}(h]h ]h"]h$]h&]refdocjO refdomainj;reftyperef refexplicitrefwarnjUidle-states-representationuh1hhhhKhjubh. in Documentation/admin-guide/pm/cpuidle.rst).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hFor example, if ``states_off`` is equal to 3, the driver will disable idle states 0 and 1 by default, and if it is equal to 8, idle state 3 will be disabled by default and so on (bit positions beyond the maximum idle state index are ignored).h](hFor example, if }(hjWhhhNhNubjg)}(h``states_off``h]h states_off}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjWubh is equal to 3, the driver will disable idle states 0 and 1 by default, and if it is equal to 8, idle state 3 will be disabled by default and so on (bit positions beyond the maximum idle state index are ignored).}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hdThe idle states disabled this way can be enabled (on a per-CPU basis) from user space via ``sysfs``.h](hZThe idle states disabled this way can be enabled (on a per-CPU basis) from user space via }(hjwhhhNhNubjg)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjwubh.}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjU hhubj)}(hX9The ``ibrs_off`` module parameter is a boolean flag (defaults to false). If set, it is used to control if IBRS (Indirect Branch Restricted Speculation) should be turned off when the CPU enters an idle state. This flag does not affect CPUs that use Enhanced IBRS which can remain on with little performance impact.h](hThe }(hjhhhNhNubjg)}(h ``ibrs_off``h]hibrs_off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhX) module parameter is a boolean flag (defaults to false). If set, it is used to control if IBRS (Indirect Branch Restricted Speculation) should be turned off when the CPU enters an idle state. This flag does not affect CPUs that use Enhanced IBRS which can remain on with little performance impact.Z}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjU hhubj)}(hX:For some CPUs, IBRS will be selected as mitigation for Spectre v2 and Retbleed security vulnerabilities by default. Leaving the IBRS mode on while idling may have a performance impact on its sibling CPU. The IBRS mode will be turned off by default when the CPU enters into a deep idle state, but not in some shallower ones. Setting the ``ibrs_off`` module parameter will force the IBRS mode to off when the CPU is in any one of the available idle states. This may help performance of a sibling CPU at the expense of a slightly higher wakeup latency for the idle CPU.h](hXSFor some CPUs, IBRS will be selected as mitigation for Spectre v2 and Retbleed security vulnerabilities by default. Leaving the IBRS mode on while idling may have a performance impact on its sibling CPU. The IBRS mode will be turned off by default when the CPU enters into a deep idle state, but not in some shallower ones. Setting the }(hjhhhNhNubjg)}(h ``ibrs_off``h]hibrs_off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh module parameter will force the IBRS mode to off when the CPU is in any one of the available idle states. This may help performance of a sibling CPU at the expense of a slightly higher wakeup latency for the idle CPU.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjU hhubj)}(hX=The ``table`` argument allows customization of idle state latency and target residency. The syntax is a comma-separated list of ``name:latency:residency`` entries, where ``name`` is the idle state name, ``latency`` is the exit latency in microseconds, and ``residency`` is the target residency in microseconds. It is not necessary to specify all idle states; only those to be customized. For example, ``C1:1:3,C6:50:100`` sets the exit latency and target residency for C1 and C6 to 1/3 and 50/100 microseconds, respectively. Remaining idle states keep their default values. The driver verifies that deeper idle states have higher latency and target residency than shallower ones. Also, target residency cannot be smaller than exit latency. If any of these conditions is not met, the driver ignores the entire ``table`` parameter.h](hThe }(hjhhhNhNubjg)}(h ``table``h]htable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhs argument allows customization of idle state latency and target residency. The syntax is a comma-separated list of }(hjhhhNhNubjg)}(h``name:latency:residency``h]hname:latency:residency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh entries, where }(hjhhhNhNubjg)}(h``name``h]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh is the idle state name, }(hjhhhNhNubjg)}(h ``latency``h]hlatency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh* is the exit latency in microseconds, and }(hjhhhNhNubjg)}(h ``residency``h]h residency}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh is the target residency in microseconds. It is not necessary to specify all idle states; only those to be customized. For example, }(hjhhhNhNubjg)}(h``C1:1:3,C6:50:100``h]hC1:1:3,C6:50:100}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhX sets the exit latency and target residency for C1 and C6 to 1/3 and 50/100 microseconds, respectively. Remaining idle states keep their default values. The driver verifies that deeper idle states have higher latency and target residency than shallower ones. Also, target residency cannot be smaller than exit latency. If any of these conditions is not met, the driver ignores the entire }(hjhhhNhNubjg)}(h ``table``h]htable}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh parameter.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjU hhubj )}(h,.. _intel-idle-core-and-package-idle-states:h]h}(h]h ]h"]h$]h&]j'intel-idle-core-and-package-idle-statesuh1j hMqhjU hhhhubeh}(h](1kernel-command-line-options-and-module-parametersjeh ]h"](1kernel command line options and module parametersintel-idle-parameterseh$]h&]uh1j[hj]hhhhhKj }jtj@ sj }jj@ sjKubj\)}(hhh](ja)}(h&Core and Package Levels of Idle Statesh]h&Core and Package Levels of Idle States}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjyhhhhhMubj)}(hXTypically, in a processor supporting the ``MWAIT`` instruction there are (at least) two levels of idle states (or C-states). One level, referred to as "core C-states", covers individual cores in the processor, whereas the other level, referred to as "package C-states", covers the entire processor package and it may also involve other components of the system (GPUs, memory controllers, I/O hubs etc.).h](h)Typically, in a processor supporting the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhXj instruction there are (at least) two levels of idle states (or C-states). One level, referred to as “core C-states”, covers individual cores in the processor, whereas the other level, referred to as “package C-states”, covers the entire processor package and it may also involve other components of the system (GPUs, memory controllers, I/O hubs etc.).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM hjyhhubj)}(hX@Some of the ``MWAIT`` hint values allow the processor to use core C-states only (most importantly, that is the case for the ``MWAIT`` hint value corresponding to the ``C1`` idle state), but the majority of them give it a license to put the target core (i.e. the core containing the logical CPU executing ``MWAIT`` with the given hint value) into a specific core C-state and then (if possible) to enter a specific package C-state at the deeper level. For example, the ``MWAIT`` hint value representing the ``C3`` idle state allows the processor to put the target core into the low-power state referred to as "core ``C3``" (or ``CC3``), which happens if all of the logical CPUs (SMT siblings) in that core have executed ``MWAIT`` with the ``C3`` hint value (or with a hint value representing a deeper idle state), and in addition to that (in the majority of cases) it gives the processor a license to put the entire package (possibly including some non-CPU components such as a GPU or a memory controller) into the low-power state referred to as "package ``C3``" (or ``PC3``), which happens if all of the cores have gone into the ``CC3`` state and (possibly) some additional conditions are satisfied (for instance, if the GPU is covered by ``PC3``, it may be required to be in a certain GPU-specific low-power state for ``PC3`` to be reachable).h](h Some of the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhg hint values allow the processor to use core C-states only (most importantly, that is the case for the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh! hint value corresponding to the }(hjhhhNhNubjg)}(h``C1``h]hC1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh idle state), but the majority of them give it a license to put the target core (i.e. the core containing the logical CPU executing }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh with the given hint value) into a specific core C-state and then (if possible) to enter a specific package C-state at the deeper level. For example, the }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh hint value representing the }(hjhhhNhNubjg)}(h``C3``h]hC3}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhh idle state allows the processor to put the target core into the low-power state referred to as “core }(hjhhhNhNubjg)}(h``C3``h]hC3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh” (or }(hjhhhNhNubjg)}(h``CC3``h]hCC3}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhV), which happens if all of the logical CPUs (SMT siblings) in that core have executed }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh with the }(hjhhhNhNubjg)}(h``C3``h]hC3}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhX8 hint value (or with a hint value representing a deeper idle state), and in addition to that (in the majority of cases) it gives the processor a license to put the entire package (possibly including some non-CPU components such as a GPU or a memory controller) into the low-power state referred to as “package }(hjhhhNhNubjg)}(h``C3``h]hC3}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh” (or }(hjhhhNhNubjg)}(h``PC3``h]hPC3}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh8), which happens if all of the cores have gone into the }(hjhhhNhNubjg)}(h``CC3``h]hCC3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhg state and (possibly) some additional conditions are satisfied (for instance, if the GPU is covered by }(hjhhhNhNubjg)}(h``PC3``h]hPC3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhI, it may be required to be in a certain GPU-specific low-power state for }(hjhhhNhNubjg)}(h``PC3``h]hPC3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh to be reachable).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM'hjyhhubj)}(hXiAs a rule, there is no simple way to make the processor use core C-states only if the conditions for entering the corresponding package C-states are met, so the logical CPU executing ``MWAIT`` with a hint value that is not core-level only (like for ``C1``) must always assume that this may cause the processor to enter a package C-state. [That is why the exit latency and target residency values corresponding to the majority of ``MWAIT`` hint values in the "internal" tables of idle states in ``intel_idle`` reflect the properties of package C-states.] If using package C-states is not desirable at all, either :ref:`PM QoS ` or the ``max_cstate`` module parameter of ``intel_idle`` described `above `_ must be used to restrict the range of permissible idle states to the ones with core-level only ``MWAIT`` hint values (like ``C1``).h](hAs a rule, there is no simple way to make the processor use core C-states only if the conditions for entering the corresponding package C-states are met, so the logical CPU executing }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh9 with a hint value that is not core-level only (like for }(hjhhhNhNubjg)}(h``C1``h]hC1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh) must always assume that this may cause the processor to enter a package C-state. [That is why the exit latency and target residency values corresponding to the majority of }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh< hint values in the “internal” tables of idle states in }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubhi reflect the properties of package C-states.] If using package C-states is not desirable at all, either }(hjhhhNhNubh)}(h:ref:`PM QoS `h]j7)}(hjh]hPM QoS}(hjhhhNhNubah}(h]h ](jBstdstd-refeh"]h$]h&]uh1j6hjubah}(h]h ]h"]h$]h&]refdocjO refdomainj$reftyperef refexplicitrefwarnjU cpu-pm-qosuh1hhhhM:hjubh or the }(hjhhhNhNubjg)}(h``max_cstate``h]h max_cstate}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh module parameter of }(hjhhhNhNubjg)}(h``intel_idle``h]h intel_idle}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh described }(hjhhhNhNubj)}(h!`above `_h]habove}(hj^hhhNhNubah}(h]h ]h"]h$]h&]nameabovejjuh1jhjj Kubj )}(h h]h}(h]h ]h"]aboveah$]h&]jjuh1j jintel-idle-parametershjj Kubh` must be used to restrict the range of permissible idle states to the ones with core-level only }(hjhhhNhNubjg)}(h ``MWAIT``h]hMWAIT}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh hint values (like }(hjhhhNhNubjg)}(h``C1``h]hC1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM:hjyhhubeh}(h](&core-and-package-levels-of-idle-statesjmeh ]h"](&core and package levels of idle states'intel-idle-core-and-package-idle-stateseh$]h&]uh1j[hj]hhhhhMj }jjcsj }jmjcsubj\)}(hhh](ja)}(h Referencesh]h References}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhMIubhfootnote)}(h*Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*, https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.html h](hlabel)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h*Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*, https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.htmlh](j)}(hL*Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*h]hJIntel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, }(hjhhhNhNubj)}(hhttps://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.htmlh]hhttps://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.html}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMKhjubeh}(h]j ah ]h"]1ah$]h&]jaj jOuh1jhhhMKhjhhj Kubj)}(hb*Advanced Configuration and Power Interface (ACPI) Specification*, https://uefi.org/specificationsh](j)}(h2h]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hb*Advanced Configuration and Power Interface (ACPI) Specification*, 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