msphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/admin-guide/pm/cpuidlemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/admin-guide/pm/cpuidlemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/admin-guide/pm/cpuidlemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/admin-guide/pm/cpuidlemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/admin-guide/pm/cpuidlemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/admin-guide/pm/cpuidlemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle.rsthKubh)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from . Processed by unicode2rstsubs.py, part of Docutils: .h]hDerived from the Unicode character mappings available from . Processed by unicode2rstsubs.py, part of Docutils: .}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsubstitution_definition)}(h*.. |amp| unicode:: U+00026 .. AMPERSANDh]h&}hhsbah}(h]h ]h"]ampah$]h&]uh1hhhhKhhhhubh)}(h+.. |apos| unicode:: U+00027 .. APOSTROPHEh]h'}hhsbah}(h]h ]h"]aposah$]h&]uh1hhhhKhhhhubh)}(h).. |ast| unicode:: U+0002A .. ASTERISKh]h*}hhsbah}(h]h ]h"]astah$]h&]uh1hhhhK hhhhubh)}(h+.. |brvbar| unicode:: U+000A6 .. BROKEN BARh]h¦}hjsbah}(h]h ]h"]brvbarah$]h&]uh1hhhhK hhhhubh)}(h0.. |bsol| unicode:: U+0005C .. REVERSE SOLIDUSh]h\}hjsbah}(h]h ]h"]bsolah$]h&]uh1hhhhK hhhhubh)}(h*.. |cent| unicode:: U+000A2 .. CENT SIGNh]h¢}hjsbah}(h]h ]h"]centah$]h&]uh1hhhhK hhhhubh)}(h&.. |colon| unicode:: U+0003A .. COLONh]h:}hj-sbah}(h]h ]h"]colonah$]h&]uh1hhhhK hhhhubh)}(h&.. |comma| unicode:: U+0002C .. COMMAh]h,}hj<sbah}(h]h ]h"]commaah$]h&]uh1hhhhKhhhhubh)}(h... |commat| unicode:: U+00040 .. COMMERCIAL ATh]h@}hjKsbah}(h]h ]h"]commatah$]h&]uh1hhhhKhhhhubh)}(h/.. |copy| unicode:: U+000A9 .. COPYRIGHT SIGNh]h©}hjZsbah}(h]h ]h"]copyah$]h&]uh1hhhhKhhhhubh)}(h... |curren| unicode:: U+000A4 .. CURRENCY SIGNh]h¤}hjisbah}(h]h ]h"]currenah$]h&]uh1hhhhKhhhhubh)}(h0.. |darr| unicode:: U+02193 .. DOWNWARDS ARROWh]h↓}hjxsbah}(h]h ]h"]darrah$]h&]uh1hhhhKhhhhubh)}(h,.. |deg| unicode:: U+000B0 .. DEGREE SIGNh]h°}hjsbah}(h]h ]h"]degah$]h&]uh1hhhhKhhhhubh)}(h... |divide| unicode:: U+000F7 .. DIVISION SIGNh]h÷}hjsbah}(h]h ]h"]divideah$]h&]uh1hhhhKhhhhubh)}(h,.. |dollar| unicode:: U+00024 .. DOLLAR SIGNh]h$}hjsbah}(h]h ]h"]dollarah$]h&]uh1hhhhKhhhhubh)}(h,.. |equals| unicode:: U+0003D .. EQUALS SIGNh]h=}hjsbah}(h]h ]h"]equalsah$]h&]uh1hhhhKhhhhubh)}(h1.. |excl| unicode:: U+00021 .. EXCLAMATION MARKh]h!}hjsbah}(h]h ]h"]exclah$]h&]uh1hhhhKhhhhubh)}(h9.. |frac12| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjsbah}(h]h ]h"]frac12ah$]h&]uh1hhhhKhhhhubh)}(h<.. |frac14| unicode:: U+000BC .. VULGAR FRACTION ONE QUARTERh]h¼}hjsbah}(h]h ]h"]frac14ah$]h&]uh1hhhhKhhhhubh)}(h;.. |frac18| unicode:: U+0215B .. VULGAR FRACTION ONE EIGHTHh]h⅛}hjsbah}(h]h ]h"]frac18ah$]h&]uh1hhhhKhhhhubh)}(h?.. |frac34| unicode:: U+000BE .. VULGAR FRACTION THREE QUARTERSh]h¾}hjsbah}(h]h ]h"]frac34ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac38| unicode:: U+0215C .. VULGAR FRACTION THREE EIGHTHSh]h⅜}hjsbah}(h]h ]h"]frac38ah$]h&]uh1hhhhKhhhhubh)}(h=.. |frac58| unicode:: U+0215D .. VULGAR FRACTION FIVE EIGHTHSh]h⅝}hjsbah}(h]h ]h"]frac58ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac78| unicode:: U+0215E .. VULGAR FRACTION SEVEN EIGHTHSh]h⅞}hj,sbah}(h]h ]h"]frac78ah$]h&]uh1hhhhKhhhhubh)}(h2.. |gt| unicode:: U+0003E .. GREATER-THAN SIGNh]h>}hj;sbah}(h]h ]h"]gtah$]h&]uh1hhhhKhhhhubh)}(h9.. |half| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjJsbah}(h]h ]h"]halfah$]h&]uh1hhhhK hhhhubh)}(h/.. |horbar| unicode:: U+02015 .. HORIZONTAL BARh]h―}hjYsbah}(h]h ]h"]horbarah$]h&]uh1hhhhK!hhhhubh)}(h'.. |hyphen| unicode:: U+02010 .. HYPHENh]h‐}hjhsbah}(h]h ]h"]hyphenah$]h&]uh1hhhhK"hhhhubh)}(h:.. |iexcl| unicode:: U+000A1 .. INVERTED EXCLAMATION MARKh]h¡}hjwsbah}(h]h ]h"]iexclah$]h&]uh1hhhhK#hhhhubh)}(h7.. |iquest| unicode:: U+000BF .. INVERTED QUESTION MARKh]h¿}hjsbah}(h]h ]h"]iquestah$]h&]uh1hhhhK$hhhhubh)}(hJ.. |laquo| unicode:: U+000AB .. LEFT-POINTING DOUBLE ANGLE QUOTATION MARKh]h«}hjsbah}(h]h ]h"]laquoah$]h&]uh1hhhhK%hhhhubh)}(h0.. |larr| unicode:: U+02190 .. LEFTWARDS ARROWh]h←}hjsbah}(h]h ]h"]larrah$]h&]uh1hhhhK&hhhhubh)}(h3.. |lcub| unicode:: U+0007B .. LEFT CURLY BRACKETh]h{}hjsbah}(h]h ]h"]lcubah$]h&]uh1hhhhK'hhhhubh)}(h;.. |ldquo| unicode:: U+0201C .. LEFT DOUBLE QUOTATION MARKh]h“}hjsbah}(h]h ]h"]ldquoah$]h&]uh1hhhhK(hhhhubh)}(h).. |lowbar| unicode:: U+0005F .. LOW LINEh]h_}hjsbah}(h]h ]h"]lowbarah$]h&]uh1hhhhK)hhhhubh)}(h1.. |lpar| unicode:: U+00028 .. LEFT PARENTHESISh]h(}hjsbah}(h]h ]h"]lparah$]h&]uh1hhhhK*hhhhubh)}(h4.. |lsqb| unicode:: U+0005B .. LEFT SQUARE BRACKETh]h[}hjsbah}(h]h ]h"]lsqbah$]h&]uh1hhhhK+hhhhubh)}(h;.. |lsquo| unicode:: U+02018 .. LEFT SINGLE QUOTATION MARKh]h‘}hjsbah}(h]h ]h"]lsquoah$]h&]uh1hhhhK,hhhhubh)}(h/.. |lt| unicode:: U+0003C .. LESS-THAN SIGNh]h<}hj sbah}(h]h ]h"]ltah$]h&]uh1hhhhK-hhhhubh)}(h+.. |micro| unicode:: U+000B5 .. MICRO SIGNh]hµ}hjsbah}(h]h ]h"]microah$]h&]uh1hhhhK.hhhhubh)}(h+.. |middot| unicode:: U+000B7 .. MIDDLE DOTh]h·}hj+sbah}(h]h ]h"]middotah$]h&]uh1hhhhK/hhhhubh)}(h/.. |nbsp| unicode:: U+000A0 .. NO-BREAK SPACEh]h }hj:sbah}(h]h ]h"]nbspah$]h&]uh1hhhhK0hhhhubh)}(h).. |not| unicode:: U+000AC .. NOT SIGNh]h¬}hjIsbah}(h]h ]h"]notah$]h&]uh1hhhhK1hhhhubh)}(h,.. |num| unicode:: U+00023 .. NUMBER SIGNh]h#}hjXsbah}(h]h ]h"]numah$]h&]uh1hhhhK2hhhhubh)}(h).. |ohm| unicode:: U+02126 .. OHM SIGNh]hΩ}hjgsbah}(h]h ]h"]ohmah$]h&]uh1hhhhK3hhhhubh)}(h;.. |ordf| unicode:: U+000AA .. FEMININE ORDINAL INDICATORh]hª}hjvsbah}(h]h ]h"]ordfah$]h&]uh1hhhhK4hhhhubh)}(h<.. |ordm| unicode:: U+000BA .. MASCULINE ORDINAL INDICATORh]hº}hjsbah}(h]h ]h"]ordmah$]h&]uh1hhhhK5hhhhubh)}(h-.. |para| unicode:: U+000B6 .. PILCROW SIGNh]h¶}hjsbah}(h]h ]h"]paraah$]h&]uh1hhhhK6hhhhubh)}(h-.. |percnt| unicode:: U+00025 .. PERCENT SIGNh]h%}hjsbah}(h]h ]h"]percntah$]h&]uh1hhhhK7hhhhubh)}(h*.. |period| unicode:: U+0002E .. FULL STOPh]h.}hjsbah}(h]h ]h"]periodah$]h&]uh1hhhhK8hhhhubh)}(h*.. |plus| unicode:: U+0002B .. PLUS SIGNh]h+}hjsbah}(h]h ]h"]plusah$]h&]uh1hhhhK9hhhhubh)}(h0.. |plusmn| unicode:: U+000B1 .. PLUS-MINUS SIGNh]h±}hjsbah}(h]h ]h"]plusmnah$]h&]uh1hhhhK:hhhhubh)}(h+.. |pound| unicode:: U+000A3 .. POUND SIGNh]h£}hjsbah}(h]h ]h"]poundah$]h&]uh1hhhhK;hhhhubh)}(h... |quest| unicode:: U+0003F .. QUESTION MARKh]h?}hjsbah}(h]h ]h"]questah$]h&]uh1hhhhKhhhhubh)}(h1.. |rarr| unicode:: U+02192 .. RIGHTWARDS ARROWh]h→}hjsbah}(h]h ]h"]rarrah$]h&]uh1hhhhK?hhhhubh)}(h4.. |rcub| unicode:: U+0007D .. RIGHT CURLY BRACKETh]h}}hj*sbah}(h]h ]h"]rcubah$]h&]uh1hhhhK@hhhhubh)}(h<.. |rdquo| unicode:: U+0201D .. RIGHT DOUBLE QUOTATION MARKh]h”}hj9sbah}(h]h ]h"]rdquoah$]h&]uh1hhhhKAhhhhubh)}(h0.. |reg| unicode:: U+000AE .. REGISTERED SIGNh]h®}hjHsbah}(h]h ]h"]regah$]h&]uh1hhhhKBhhhhubh)}(h2.. |rpar| unicode:: U+00029 .. RIGHT PARENTHESISh]h)}hjWsbah}(h]h ]h"]rparah$]h&]uh1hhhhKChhhhubh)}(h5.. |rsqb| unicode:: U+0005D .. RIGHT SQUARE BRACKETh]h]}hjfsbah}(h]h ]h"]rsqbah$]h&]uh1hhhhKDhhhhubh)}(h<.. |rsquo| unicode:: U+02019 .. RIGHT SINGLE QUOTATION MARKh]h’}hjusbah}(h]h ]h"]rsquoah$]h&]uh1hhhhKEhhhhubh)}(h-.. |sect| unicode:: U+000A7 .. SECTION SIGNh]h§}hjsbah}(h]h ]h"]sectah$]h&]uh1hhhhKFhhhhubh)}(h*.. |semi| unicode:: U+0003B .. SEMICOLONh]h;}hjsbah}(h]h ]h"]semiah$]h&]uh1hhhhKGhhhhubh)}(h,.. |shy| unicode:: U+000AD .. SOFT HYPHENh]h­}hjsbah}(h]h ]h"]shyah$]h&]uh1hhhhKHhhhhubh)}(h(.. |sol| unicode:: U+0002F .. SOLIDUSh]h/}hjsbah}(h]h ]h"]solah$]h&]uh1hhhhKIhhhhubh)}(h,.. |sung| unicode:: U+0266A .. EIGHTH NOTEh]h♪}hjsbah}(h]h ]h"]sungah$]h&]uh1hhhhKJhhhhubh)}(h0.. |sup1| unicode:: U+000B9 .. SUPERSCRIPT ONEh]h¹}hjsbah}(h]h ]h"]sup1ah$]h&]uh1hhhhKKhhhhubh)}(h0.. |sup2| unicode:: U+000B2 .. SUPERSCRIPT TWOh]h²}hjsbah}(h]h ]h"]sup2ah$]h&]uh1hhhhKLhhhhubh)}(h2.. |sup3| unicode:: U+000B3 .. SUPERSCRIPT THREEh]h³}hjsbah}(h]h ]h"]sup3ah$]h&]uh1hhhhKMhhhhubh)}(h4.. |times| unicode:: U+000D7 .. MULTIPLICATION SIGNh]h×}hjsbah}(h]h ]h"]timesah$]h&]uh1hhhhKNhhhhubh)}(h0.. |trade| unicode:: U+02122 .. TRADE MARK SIGNh]h™}hj sbah}(h]h ]h"]tradeah$]h&]uh1hhhhKOhhhhubh)}(h... |uarr| unicode:: U+02191 .. UPWARDS ARROWh]h↑}hjsbah}(h]h ]h"]uarrah$]h&]uh1hhhhKPhhhhubh)}(h... |verbar| unicode:: U+0007C .. VERTICAL LINEh]h|}hj)sbah}(h]h ]h"]verbarah$]h&]uh1hhhhKQhhhhubh)}(h*.. |yen| unicode:: U+000A5 .. YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubh)}(hR.. |struct cpuidle_state| replace:: :c:type:`struct cpuidle_state `h]h)}(h.:c:type:`struct cpuidle_state `h]hliteral)}(hjMh]hstruct cpuidle_state}(hjQhhhNhNubah}(h]h ](xrefcc-typeeh"]h$]h&]uh1jOhjKubah}(h]h ]h"]h$]h&]refdocadmin-guide/pm/cpuidle refdomainj\reftypetype refexplicitrefwarn reftarget cpuidle_stateuh1hhhhKhjGubah}(h]h ]h"]struct cpuidle_stateah$]h&]uh1hhhhKhhhhubh)}(h@.. |cpufreq| replace:: :doc:`CPU Performance Scaling ` h]h)}(h(:doc:`CPU Performance Scaling `h]hinline)}(hj}h]hCPU Performance Scaling}(hjhhhNhNubah}(h]h ](j[stdstd-doceh"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]refdocjh refdomainjreftypedoc refexplicitrefwarnjncpufrequh1hhhhKhjwubah}(h]h ]h"]cpufreqah$]h&]uh1hhhhKhhhhubhsection)}(hhh](htitle)}(hCPU Idle Time Managementh]hCPU Idle Time Management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhK ubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubh field_body)}(h|copy| 2018 Intel Corporation h]h paragraph)}(h|copy| 2018 Intel Corporationh](h©}(hjhhhNhNubh 2018 Intel Corporation}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK hjhhubj)}(hhh](j)}(hAuthorh]hAuthor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj)}(h0Rafael J. Wysocki h]j)}(h.Rafael J. Wysocki h](hRafael J. Wysocki <}(hjhhhNhNubh reference)}(hrafael.j.wysocki@intel.comh]hrafael.j.wysocki@intel.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refuri!mailto:rafael.j.wysocki@intel.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK hjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhK ubj)}(hhh](j)}(hConceptsh]hConcepts}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDhhhhhKubj)}(hModern processors are generally able to enter states in which the execution of a program is suspended and instructions belonging to it are not fetched from memory or executed. Those states are the *idle* states of the processor.h](hModern processors are generally able to enter states in which the execution of a program is suspended and instructions belonging to it are not fetched from memory or executed. Those states are the }(hjUhhhNhNubhemphasis)}(h*idle*h]hidle}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjUubh states of the processor.}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjDhhubj)}(hSince part of the processor hardware is not used in idle states, entering them generally allows power drawn by the processor to be reduced and, in consequence, it is an opportunity to save energy.h]hSince part of the processor hardware is not used in idle states, entering them generally allows power drawn by the processor to be reduced and, in consequence, it is an opportunity to save energy.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjDhhubj)}(h~CPU idle time management is an energy-efficiency feature concerned about using the idle states of processors for this purpose.h]h~CPU idle time management is an energy-efficiency feature concerned about using the idle states of processors for this purpose.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjDhhubj)}(hhh](j)}(h Logical CPUsh]h Logical CPUs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKubj)}(hXZCPU idle time management operates on CPUs as seen by the *CPU scheduler* (that is the part of the kernel responsible for the distribution of computational work in the system). In its view, CPUs are *logical* units. That is, they need not be separate physical entities and may just be interfaces appearing to software as individual single-core processors. In other words, a CPU is an entity which appears to be fetching instructions that belong to one sequence (program) from memory and executing them, but it need not work this way physically. Generally, three different cases can be consider here.h](h9CPU idle time management operates on CPUs as seen by the }(hjhhhNhNubj^)}(h*CPU scheduler*h]h CPU scheduler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubh (that is the part of the kernel responsible for the distribution of computational work in the system). In its view, CPUs are }(hjhhhNhNubj^)}(h *logical*h]hlogical}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubhX units. That is, they need not be separate physical entities and may just be interfaces appearing to software as individual single-core processors. In other words, a CPU is an entity which appears to be fetching instructions that belong to one sequence (program) from memory and executing them, but it need not work this way physically. Generally, three different cases can be consider here.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK!hjhhubj)}(hFirst, if the whole processor can only follow one sequence of instructions (one program) at a time, it is a CPU. In that case, if the hardware is asked to enter an idle state, that applies to the processor as a whole.h]hFirst, if the whole processor can only follow one sequence of instructions (one program) at a time, it is a CPU. In that case, if the hardware is asked to enter an idle state, that applies to the processor as a whole.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK*hjhhubj)}(hX Second, if the processor is multi-core, each core in it is able to follow at least one program at a time. The cores need not be entirely independent of each other (for example, they may share caches), but still most of the time they work physically in parallel with each other, so if each of them executes only one program, those programs run mostly independently of each other at the same time. The entire cores are CPUs in that case and if the hardware is asked to enter an idle state, that applies to the core that asked for it in the first place, but it also may apply to a larger unit (say a "package" or a "cluster") that the core belongs to (in fact, it may apply to an entire hierarchy of larger units containing the core). Namely, if all of the cores in the larger unit except for one have been put into idle states at the "core level" and the remaining core asks the processor to enter an idle state, that may trigger it to put the whole larger unit into an idle state which also will affect the other cores in that unit.h]hXSecond, if the processor is multi-core, each core in it is able to follow at least one program at a time. The cores need not be entirely independent of each other (for example, they may share caches), but still most of the time they work physically in parallel with each other, so if each of them executes only one program, those programs run mostly independently of each other at the same time. The entire cores are CPUs in that case and if the hardware is asked to enter an idle state, that applies to the core that asked for it in the first place, but it also may apply to a larger unit (say a “package” or a “cluster”) that the core belongs to (in fact, it may apply to an entire hierarchy of larger units containing the core). Namely, if all of the cores in the larger unit except for one have been put into idle states at the “core level” and the remaining core asks the processor to enter an idle state, that may trigger it to put the whole larger unit into an idle state which also will affect the other cores in that unit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK.hjhhubj)}(hXqFinally, each core in a multi-core processor may be able to follow more than one program in the same time frame (that is, each core may be able to fetch instructions from multiple locations in memory and execute them in the same time frame, but not necessarily entirely in parallel with each other). In that case the cores present themselves to software as "bundles" each consisting of multiple individual single-core "processors", referred to as *hardware threads* (or hyper-threads specifically on Intel hardware), that each can follow one sequence of instructions. Then, the hardware threads are CPUs from the CPU idle time management perspective and if the processor is asked to enter an idle state by one of them, the hardware thread (or CPU) that asked for it is stopped, but nothing more happens, unless all of the other hardware threads within the same core also have asked the processor to enter an idle state. In that situation, the core may be put into an idle state individually or a larger unit containing it may be put into an idle state as a whole (if the other cores within the larger unit are in idle states already).h](hXFinally, each core in a multi-core processor may be able to follow more than one program in the same time frame (that is, each core may be able to fetch instructions from multiple locations in memory and execute them in the same time frame, but not necessarily entirely in parallel with each other). In that case the cores present themselves to software as “bundles” each consisting of multiple individual single-core “processors”, referred to as }(hjhhhNhNubj^)}(h*hardware threads*h]hhardware threads}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubhX (or hyper-threads specifically on Intel hardware), that each can follow one sequence of instructions. Then, the hardware threads are CPUs from the CPU idle time management perspective and if the processor is asked to enter an idle state by one of them, the hardware thread (or CPU) that asked for it is stopped, but nothing more happens, unless all of the other hardware threads within the same core also have asked the processor to enter an idle state. In that situation, the core may be put into an idle state individually or a larger unit containing it may be put into an idle state as a whole (if the other cores within the larger unit are in idle states already).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK=hjhhubeh}(h] logical-cpusah ]h"] logical cpusah$]h&]uh1jhjDhhhhhKubj)}(hhh](j)}(h Idle CPUsh]h Idle CPUs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKNubj)}(hLogical CPUs, simply referred to as "CPUs" in what follows, are regarded as *idle* by the Linux kernel when there are no tasks to run on them except for the special "idle" task.h](hPLogical CPUs, simply referred to as “CPUs” in what follows, are regarded as }(hj+hhhNhNubj^)}(h*idle*h]hidle}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j]hj+ubhc by the Linux kernel when there are no tasks to run on them except for the special “idle” task.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKPhjhhubj)}(hXTasks are the CPU scheduler's representation of work. Each task consists of a sequence of instructions to execute, or code, data to be manipulated while running that code, and some context information that needs to be loaded into the processor every time the task's code is run by a CPU. The CPU scheduler distributes work by assigning tasks to run to the CPUs present in the system.h]hXTasks are the CPU scheduler’s representation of work. Each task consists of a sequence of instructions to execute, or code, data to be manipulated while running that code, and some context information that needs to be loaded into the processor every time the task’s code is run by a CPU. The CPU scheduler distributes work by assigning tasks to run to the CPUs present in the system.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKThjhhubj)}(hXTasks can be in various states. In particular, they are *runnable* if there are no specific conditions preventing their code from being run by a CPU as long as there is a CPU available for that (for example, they are not waiting for any events to occur or similar). When a task becomes runnable, the CPU scheduler assigns it to one of the available CPUs to run and if there are no more runnable tasks assigned to it, the CPU will load the given task's context and run its code (from the instruction following the last one executed so far, possibly by another CPU). [If there are multiple runnable tasks assigned to one CPU simultaneously, they will be subject to prioritization and time sharing in order to allow them to make some progress over time.]h](h9Tasks can be in various states. In particular, they are }(hjYhhhNhNubj^)}(h *runnable*h]hrunnable}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjYubhX if there are no specific conditions preventing their code from being run by a CPU as long as there is a CPU available for that (for example, they are not waiting for any events to occur or similar). When a task becomes runnable, the CPU scheduler assigns it to one of the available CPUs to run and if there are no more runnable tasks assigned to it, the CPU will load the given task’s context and run its code (from the instruction following the last one executed so far, possibly by another CPU). [If there are multiple runnable tasks assigned to one CPU simultaneously, they will be subject to prioritization and time sharing in order to allow them to make some progress over time.]}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKZhjhhubj)}(hXThe special "idle" task becomes runnable if there are no other runnable tasks assigned to the given CPU and the CPU is then regarded as idle. In other words, in Linux idle CPUs run the code of the "idle" task called *the idle loop*. That code may cause the processor to be put into one of its idle states, if they are supported, in order to save energy, but if the processor does not support any idle states, or there is not enough time to spend in an idle state before the next wakeup event, or there are strict latency constraints preventing any of the available idle states from being used, the CPU will simply execute more or less useless instructions in a loop until it is assigned a new task to run.h](hThe special “idle” task becomes runnable if there are no other runnable tasks assigned to the given CPU and the CPU is then regarded as idle. In other words, in Linux idle CPUs run the code of the “idle” task called }(hjyhhhNhNubj^)}(h*the idle loop*h]h the idle loop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjyubhX. That code may cause the processor to be put into one of its idle states, if they are supported, in order to save energy, but if the processor does not support any idle states, or there is not enough time to spend in an idle state before the next wakeup event, or there are strict latency constraints preventing any of the available idle states from being used, the CPU will simply execute more or less useless instructions in a loop until it is assigned a new task to run.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKehjhhubhtarget)}(h.. _idle-loop:h]h}(h]h ]h"]h$]h&]refid idle-loopuh1jhKhjhhhh referencedKubeh}(h] idle-cpusah ]h"] idle cpusah$]h&]uh1jhjDhhhhhKNubeh}(h]conceptsah ]h"]conceptsah$]h&]uh1jhjhhhhhKubj)}(hhh](j)}(h The Idle Looph]h The Idle Loop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhKsubj)}(hXThe idle loop code takes two major steps in every iteration of it. First, it calls into a code module referred to as the *governor* that belongs to the CPU idle time management subsystem called ``CPUIdle`` to select an idle state for the CPU to ask the hardware to enter. Second, it invokes another code module from the ``CPUIdle`` subsystem, called the *driver*, to actually ask the processor hardware to enter the idle state selected by the governor.h](hzThe idle loop code takes two major steps in every iteration of it. First, it calls into a code module referred to as the }(hjhhhNhNubj^)}(h *governor*h]hgovernor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubh? that belongs to the CPU idle time management subsystem called }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubht to select an idle state for the CPU to ask the hardware to enter. Second, it invokes another code module from the }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh subsystem, called the }(hjhhhNhNubj^)}(h*driver*h]hdriver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubhZ, to actually ask the processor hardware to enter the idle state selected by the governor.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKuhjhhubj)}(hXdThe role of the governor is to find an idle state most suitable for the conditions at hand. For this purpose, idle states that the hardware can be asked to enter by logical CPUs are represented in an abstract way independent of the platform or the processor architecture and organized in a one-dimensional (linear) array. That array has to be prepared and supplied by the ``CPUIdle`` driver matching the platform the kernel is running on at the initialization time. This allows ``CPUIdle`` governors to be independent of the underlying hardware and to work with any platforms that the Linux kernel can run on.h](hXvThe role of the governor is to find an idle state most suitable for the conditions at hand. For this purpose, idle states that the hardware can be asked to enter by logical CPUs are represented in an abstract way independent of the platform or the processor architecture and organized in a one-dimensional (linear) array. That array has to be prepared and supplied by the }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh` driver matching the platform the kernel is running on at the initialization time. This allows }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhx governors to be independent of the underlying hardware and to work with any platforms that the Linux kernel can run on.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK|hjhhubj)}(hXEach idle state present in that array is characterized by two parameters to be taken into account by the governor, the *target residency* and the (worst-case) *exit latency*. The target residency is the minimum time the hardware must spend in the given state, including the time needed to enter it (which may be substantial), in order to save more energy than it would save by entering one of the shallower idle states instead. [The "depth" of an idle state roughly corresponds to the power drawn by the processor in that state.] The exit latency, in turn, is the maximum time it will take a CPU asking the processor hardware to enter an idle state to start executing the first instruction after a wakeup from that state. Note that in general the exit latency also must cover the time needed to enter the given state in case the wakeup occurs when the hardware is entering it and it must be entered completely to be exited in an ordered manner.h](hwEach idle state present in that array is characterized by two parameters to be taken into account by the governor, the }(hjQhhhNhNubj^)}(h*target residency*h]htarget residency}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjQubh and the (worst-case) }(hjQhhhNhNubj^)}(h*exit latency*h]h exit latency}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjQubhX . The target residency is the minimum time the hardware must spend in the given state, including the time needed to enter it (which may be substantial), in order to save more energy than it would save by entering one of the shallower idle states instead. [The “depth” of an idle state roughly corresponds to the power drawn by the processor in that state.] The exit latency, in turn, is the maximum time it will take a CPU asking the processor hardware to enter an idle state to start executing the first instruction after a wakeup from that state. Note that in general the exit latency also must cover the time needed to enter the given state in case the wakeup occurs when the hardware is entering it and it must be entered completely to be exited in an ordered manner.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXThere are two types of information that can influence the governor's decisions. First of all, the governor knows the time until the closest timer event. That time is known exactly, because the kernel programs timers and it knows exactly when they will trigger, and it is the maximum time the hardware that the given CPU depends on can spend in an idle state, including the time necessary to enter and exit it. However, the CPU may be woken up by a non-timer event at any time (in particular, before the closest timer triggers) and it generally is not known when that may happen. The governor can only see how much time the CPU actually was idle after it has been woken up (that time will be referred to as the *idle duration* from now on) and it can use that information somehow along with the time until the closest timer to estimate the idle duration in future. How the governor uses that information depends on what algorithm is implemented by it and that is the primary reason for having more than one governor in the ``CPUIdle`` subsystem.h](hXThere are two types of information that can influence the governor’s decisions. First of all, the governor knows the time until the closest timer event. That time is known exactly, because the kernel programs timers and it knows exactly when they will trigger, and it is the maximum time the hardware that the given CPU depends on can spend in an idle state, including the time necessary to enter and exit it. However, the CPU may be woken up by a non-timer event at any time (in particular, before the closest timer triggers) and it generally is not known when that may happen. The governor can only see how much time the CPU actually was idle after it has been woken up (that time will be referred to as the }(hjhhhNhNubj^)}(h*idle duration*h]h idle duration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubhX* from now on) and it can use that information somehow along with the time until the closest timer to estimate the idle duration in future. How the governor uses that information depends on what algorithm is implemented by it and that is the primary reason for having more than one governor in the }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh subsystem.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXlThere are four ``CPUIdle`` governors available, ``menu``, `TEO `_, ``ladder`` and ``haltpoll``. Which of them is used by default depends on the configuration of the kernel and in particular on whether or not the scheduler tick can be `stopped by the idle loop `_. Available governors can be read from the :file:`available_governors`, and the governor can be changed at runtime. The name of the ``CPUIdle`` governor currently used by the kernel can be read from the :file:`current_governor_ro` or :file:`current_governor` file under :file:`/sys/devices/system/cpu/cpuidle/` in ``sysfs``.h](hThere are four }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh governors available, }(hjhhhNhNubjP)}(h``menu``h]hmenu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh, }(hjhhhNhNubj)}(h`TEO `_h]hTEO}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameTEOjteo-govuh1jhjresolvedKubj)}(h h]h}(h]h ]h"]teoah$]h&]jjuh1jindirect_reference_nameteo-govhjjKubh, }(hjhhhNhNubjP)}(h ``ladder``h]hladder}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh and }(hjhhhNhNubjP)}(h ``haltpoll``h]hhaltpoll}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh. Which of them is used by default depends on the configuration of the kernel and in particular on whether or not the scheduler tick can be }(hjhhhNhNubj)}(h1`stopped by the idle loop `_h]hstopped by the idle loop}(hj( hhhNhNubah}(h]h ]h"]h$]h&]namestopped by the idle loopjidle-cpus-and-tickuh1jhjjKubj)}(h h]h}(h]h ]h"]stopped by the idle loopah$]h&]jj8 uh1jjidle-cpus-and-tickhjjKubh,. Available governors can be read from the }(hjhhhNhNubjP)}(h:file:`available_governors`h]havailable_governors}(hjI hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh?, and the governor can be changed at runtime. The name of the }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh< governor currently used by the kernel can be read from the }(hjhhhNhNubjP)}(h:file:`current_governor_ro`h]hcurrent_governor_ro}(hjp hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh or }(hjhhhNhNubjP)}(h:file:`current_governor`h]hcurrent_governor}(hj hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh file under }(hjhhhNhNubjP)}(h(:file:`/sys/devices/system/cpu/cpuidle/`h]h /sys/devices/system/cpu/cpuidle/}(hj hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh in }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXWhich ``CPUIdle`` driver is used, on the other hand, usually depends on the platform the kernel is running on, but there are platforms with more than one matching driver. For example, there are two drivers that can work with the majority of Intel platforms, ``intel_idle`` and ``acpi_idle``, one with hardcoded idle states information and the other able to read that information from the system's ACPI tables, respectively. Still, even in those cases, the driver chosen at the system initialization time cannot be replaced later, so the decision on which one of them to use has to be made early (on Intel platforms the ``acpi_idle`` driver will be used if ``intel_idle`` is disabled for some reason or if it does not recognize the processor). The name of the ``CPUIdle`` driver currently used by the kernel can be read from the :file:`current_driver` file under :file:`/sys/devices/system/cpu/cpuidle/` in ``sysfs``.h](hWhich }(hj hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh driver is used, on the other hand, usually depends on the platform the kernel is running on, but there are platforms with more than one matching driver. For example, there are two drivers that can work with the majority of Intel platforms, }(hj hhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh and }(hj hhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubhXL, one with hardcoded idle states information and the other able to read that information from the system’s ACPI tables, respectively. Still, even in those cases, the driver chosen at the system initialization time cannot be replaced later, so the decision on which one of them to use has to be made early (on Intel platforms the }(hj hhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh driver will be used if }(hj hhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubhZ is disabled for some reason or if it does not recognize the processor). The name of the }(hj hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh: driver currently used by the kernel can be read from the }(hj hhhNhNubjP)}(h:file:`current_driver`h]hcurrent_driver}(hj; hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj ubh file under }(hj hhhNhNubjP)}(h(:file:`/sys/devices/system/cpu/cpuidle/`h]h /sys/devices/system/cpu/cpuidle/}(hjP hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj ubh in }(hj hhhNhNubjP)}(h ``sysfs``h]hsysfs}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(h.. _idle-cpus-and-tick:h]h}(h]h ]h"]h$]h&]jj8 uh1jhMhjhhhhjKubeh}(h]( the-idle-loopjeh ]h"]( the idle loop idle-loopeh$]h&]uh1jhjhhhhhKsexpect_referenced_by_name}j jsexpect_referenced_by_id}jjsjKubj)}(hhh](j)}(h Idle CPUs and The Scheduler Tickh]h Idle CPUs and The Scheduler Tick}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hhhhhKubj)}(hX@The scheduler tick is a timer that triggers periodically in order to implement the time sharing strategy of the CPU scheduler. Of course, if there are multiple runnable tasks assigned to one CPU at the same time, the only way to allow them to make reasonable progress in a given time frame is to make them share the available CPU time. Namely, in rough approximation, each task is given a slice of the CPU time to run its code, subject to the scheduling class, prioritization and so on and when that time slice is used up, the CPU should be switched over to running (the code of) another task. The currently running task may not want to give the CPU away voluntarily, however, and the scheduler tick is there to make the switch happen regardless. That is not the only role of the tick, but it is the primary reason for using it.h]hX@The scheduler tick is a timer that triggers periodically in order to implement the time sharing strategy of the CPU scheduler. Of course, if there are multiple runnable tasks assigned to one CPU at the same time, the only way to allow them to make reasonable progress in a given time frame is to make them share the available CPU time. Namely, in rough approximation, each task is given a slice of the CPU time to run its code, subject to the scheduling class, prioritization and so on and when that time slice is used up, the CPU should be switched over to running (the code of) another task. The currently running task may not want to give the CPU away voluntarily, however, and the scheduler tick is there to make the switch happen regardless. That is not the only role of the tick, but it is the primary reason for using it.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hXiThe scheduler tick is problematic from the CPU idle time management perspective, because it triggers periodically and relatively often (depending on the kernel configuration, the length of the tick period is between 1 ms and 10 ms). Thus, if the tick is allowed to trigger on idle CPUs, it will not make sense for them to ask the hardware to enter idle states with target residencies above the tick period length. Moreover, in that case the idle duration of any CPU will never exceed the tick period length and the energy used for entering and exiting idle states due to the tick wakeups on idle CPUs will be wasted.h]hXiThe scheduler tick is problematic from the CPU idle time management perspective, because it triggers periodically and relatively often (depending on the kernel configuration, the length of the tick period is between 1 ms and 10 ms). Thus, if the tick is allowed to trigger on idle CPUs, it will not make sense for them to ask the hardware to enter idle states with target residencies above the tick period length. Moreover, in that case the idle duration of any CPU will never exceed the tick period length and the energy used for entering and exiting idle states due to the tick wakeups on idle CPUs will be wasted.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hXCFortunately, it is not really necessary to allow the tick to trigger on idle CPUs, because (by definition) they have no tasks to run except for the special "idle" one. In other words, from the CPU scheduler perspective, the only user of the CPU time on them is the idle loop. Since the time of an idle CPU need not be shared between multiple runnable tasks, the primary reason for using the tick goes away if the given CPU is idle. Consequently, it is possible to stop the scheduler tick entirely on idle CPUs in principle, even though that may not always be worth the effort.h]hXGFortunately, it is not really necessary to allow the tick to trigger on idle CPUs, because (by definition) they have no tasks to run except for the special “idle” one. In other words, from the CPU scheduler perspective, the only user of the CPU time on them is the idle loop. Since the time of an idle CPU need not be shared between multiple runnable tasks, the primary reason for using the tick goes away if the given CPU is idle. Consequently, it is possible to stop the scheduler tick entirely on idle CPUs in principle, even though that may not always be worth the effort.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hXWhether or not it makes sense to stop the scheduler tick in the idle loop depends on what is expected by the governor. First, if there is another (non-tick) timer due to trigger within the tick range, stopping the tick clearly would be a waste of time, even though the timer hardware may not need to be reprogrammed in that case. Second, if the governor is expecting a non-timer wakeup within the tick range, stopping the tick is not necessary and it may even be harmful. Namely, in that case the governor will select an idle state with the target residency within the time until the expected wakeup, so that state is going to be relatively shallow. The governor really cannot select a deep idle state then, as that would contradict its own expectation of a wakeup in short order. Now, if the wakeup really occurs shortly, stopping the tick would be a waste of time and in this case the timer hardware would need to be reprogrammed, which is expensive. On the other hand, if the tick is stopped and the wakeup does not occur any time soon, the hardware may spend indefinite amount of time in the shallow idle state selected by the governor, which will be a waste of energy. Hence, if the governor is expecting a wakeup of any kind within the tick range, it is better to allow the tick trigger. Otherwise, however, the governor will select a relatively deep idle state, so the tick should be stopped so that it does not wake up the CPU too early.h]hXWhether or not it makes sense to stop the scheduler tick in the idle loop depends on what is expected by the governor. First, if there is another (non-tick) timer due to trigger within the tick range, stopping the tick clearly would be a waste of time, even though the timer hardware may not need to be reprogrammed in that case. Second, if the governor is expecting a non-timer wakeup within the tick range, stopping the tick is not necessary and it may even be harmful. Namely, in that case the governor will select an idle state with the target residency within the time until the expected wakeup, so that state is going to be relatively shallow. The governor really cannot select a deep idle state then, as that would contradict its own expectation of a wakeup in short order. Now, if the wakeup really occurs shortly, stopping the tick would be a waste of time and in this case the timer hardware would need to be reprogrammed, which is expensive. On the other hand, if the tick is stopped and the wakeup does not occur any time soon, the hardware may spend indefinite amount of time in the shallow idle state selected by the governor, which will be a waste of energy. Hence, if the governor is expecting a wakeup of any kind within the tick range, it is better to allow the tick trigger. Otherwise, however, the governor will select a relatively deep idle state, so the tick should be stopped so that it does not wake up the CPU too early.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hX0In any case, the governor knows what it is expecting and the decision on whether or not to stop the scheduler tick belongs to it. Still, if the tick has been stopped already (in one of the previous iterations of the loop), it is better to leave it as is and the governor needs to take that into account.h]hX0In any case, the governor knows what it is expecting and the decision on whether or not to stop the scheduler tick belongs to it. Still, if the tick has been stopped already (in one of the previous iterations of the loop), it is better to leave it as is and the governor needs to take that into account.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hXThe kernel can be configured to disable stopping the scheduler tick in the idle loop altogether. That can be done through the build-time configuration of it (by unsetting the ``CONFIG_NO_HZ_IDLE`` configuration option) or by passing ``nohz=off`` to it in the command line. In both cases, as the stopping of the scheduler tick is disabled, the governor's decisions regarding it are simply ignored by the idle loop code and the tick is never stopped.h](hThe kernel can be configured to disable stopping the scheduler tick in the idle loop altogether. That can be done through the build-time configuration of it (by unsetting the }(hj hhhNhNubjP)}(h``CONFIG_NO_HZ_IDLE``h]hCONFIG_NO_HZ_IDLE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh% configuration option) or by passing }(hj hhhNhNubjP)}(h ``nohz=off``h]hnohz=off}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh to it in the command line. In both cases, as the stopping of the scheduler tick is disabled, the governor’s decisions regarding it are simply ignored by the idle loop code and the tick is never stopped.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hXThe systems that run kernels configured to allow the scheduler tick to be stopped on idle CPUs are referred to as *tickless* systems and they are generally regarded as more energy-efficient than the systems running kernels in which the tick cannot be stopped. If the given system is tickless, it will use the ``menu`` governor by default and if it is not tickless, the default ``CPUIdle`` governor on it will be ``ladder``.h](hrThe systems that run kernels configured to allow the scheduler tick to be stopped on idle CPUs are referred to as }(hj hhhNhNubj^)}(h *tickless*h]htickless}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1j]hj ubh systems and they are generally regarded as more energy-efficient than the systems running kernels in which the tick cannot be stopped. If the given system is tickless, it will use the }(hj hhhNhNubjP)}(h``menu``h]hmenu}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh< governor by default and if it is not tickless, the default }(hj hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh governor on it will be }(hj hhhNhNubjP)}(h ``ladder``h]hladder}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(h .. _menu-gov:h]h}(h]h ]h"]h$]h&]jmenu-govuh1jhM[hj hhhhjKubeh}(h](j8 idle-cpus-and-the-scheduler-tickeh ]h"]( idle cpus and the scheduler tickidle-cpus-and-tickeh$]h&]uh1jhjhhhhhKj }j j} sj }j8 j} sjKubj)}(hhh](j)}(hThe ``menu`` Governorh](hThe }(hj hhhNhNubjP)}(h``menu``h]hmenu}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh Governor}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhMubj)}(hXThe ``menu`` governor is the default ``CPUIdle`` governor for tickless systems. It is quite complex, but the basic principle of its design is straightforward. Namely, when invoked to select an idle state for a CPU (i.e. an idle state that the CPU will ask the processor hardware to enter), it attempts to predict the idle duration and uses the predicted value for idle state selection.h](hThe }(hj hhhNhNubjP)}(h``menu``h]hmenu}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh governor is the default }(hj hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubhXQ governor for tickless systems. It is quite complex, but the basic principle of its design is straightforward. Namely, when invoked to select an idle state for a CPU (i.e. an idle state that the CPU will ask the processor hardware to enter), it attempts to predict the idle duration and uses the predicted value for idle state selection.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM hj hhubj)}(hXIt first uses a simple pattern recognition algorithm to obtain a preliminary idle duration prediction. Namely, it saves the last 8 observed idle duration values and, when predicting the idle duration next time, it computes the average and variance of them. If the variance is small (smaller than 400 square milliseconds) or it is small relative to the average (the average is greater that 6 times the standard deviation), the average is regarded as the "typical interval" value. Otherwise, either the longest or the shortest (depending on which one is farther from the average) of the saved observed idle duration values is discarded and the computation is repeated for the remaining ones.h]hXIt first uses a simple pattern recognition algorithm to obtain a preliminary idle duration prediction. Namely, it saves the last 8 observed idle duration values and, when predicting the idle duration next time, it computes the average and variance of them. If the variance is small (smaller than 400 square milliseconds) or it is small relative to the average (the average is greater that 6 times the standard deviation), the average is regarded as the “typical interval” value. Otherwise, either the longest or the shortest (depending on which one is farther from the average) of the saved observed idle duration values is discarded and the computation is repeated for the remaining ones.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hXGAgain, if the variance of them is small (in the above sense), the average is taken as the "typical interval" value and so on, until either the "typical interval" is determined or too many data points are disregarded. In the latter case, if the size of the set of data points still under consideration is sufficiently large, the next idle duration is not likely to be above the largest idle duration value still in that set, so that value is taken as the predicted next idle duration. Finally, if the set of data points still under consideration is too small, no prediction is made.h]hXOAgain, if the variance of them is small (in the above sense), the average is taken as the “typical interval” value and so on, until either the “typical interval” is determined or too many data points are disregarded. In the latter case, if the size of the set of data points still under consideration is sufficiently large, the next idle duration is not likely to be above the largest idle duration value still in that set, so that value is taken as the predicted next idle duration. Finally, if the set of data points still under consideration is too small, no prediction is made.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hXIf the preliminary prediction of the next idle duration computed this way is long enough, the governor obtains the time until the closest timer event with the assumption that the scheduler tick will be stopped. That time, referred to as the *sleep length* in what follows, is the upper bound on the time before the next CPU wakeup. It is used to determine the sleep length range, which in turn is needed to get the sleep length correction factor.h](hIf the preliminary prediction of the next idle duration computed this way is long enough, the governor obtains the time until the closest timer event with the assumption that the scheduler tick will be stopped. That time, referred to as the }(hj hhhNhNubj^)}(h*sleep length*h]h sleep length}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j]hj ubh in what follows, is the upper bound on the time before the next CPU wakeup. It is used to determine the sleep length range, which in turn is needed to get the sleep length correction factor.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM#hj hhubj)}(hThe ``menu`` governor maintains an array containing several correction factor values that correspond to different sleep length ranges organized so that each range represented in the array is approximately 10 times wider than the previous one.h](hThe }(hj hhhNhNubjP)}(h``menu``h]hmenu}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh governor maintains an array containing several correction factor values that correspond to different sleep length ranges organized so that each range represented in the array is approximately 10 times wider than the previous one.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM*hj hhubj)}(hXSThe correction factor for the given sleep length range (determined before selecting the idle state for the CPU) is updated after the CPU has been woken up and the closer the sleep length is to the observed idle duration, the closer to 1 the correction factor becomes (it must fall between 0 and 1 inclusive). The sleep length is multiplied by the correction factor for the range that it falls into to obtain an approximation of the predicted idle duration that is compared to the "typical interval" determined previously and the minimum of the two is taken as the final idle duration prediction.h]hXWThe correction factor for the given sleep length range (determined before selecting the idle state for the CPU) is updated after the CPU has been woken up and the closer the sleep length is to the observed idle duration, the closer to 1 the correction factor becomes (it must fall between 0 and 1 inclusive). The sleep length is multiplied by the correction factor for the range that it falls into to obtain an approximation of the predicted idle duration that is compared to the “typical interval” determined previously and the minimum of the two is taken as the final idle duration prediction.}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM/hj hhubj)}(hIf the "typical interval" value is small, which means that the CPU is likely to be woken up soon enough, the sleep length computation is skipped as it may be costly and the idle duration is simply predicted to equal the "typical interval" value.h]hIf the “typical interval” value is small, which means that the CPU is likely to be woken up soon enough, the sleep length computation is skipped as it may be costly and the idle duration is simply predicted to equal the “typical interval” value.}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM8hj hhubj)}(hXNow, the governor is ready to walk the list of idle states and choose one of them. For this purpose, it compares the target residency of each state with the predicted idle duration and the exit latency of it with the with the latency limit coming from the power management quality of service, or `PM QoS `_, framework. It selects the state with the target residency closest to the predicted idle duration, but still below it, and exit latency that does not exceed the limit.h](hX)Now, the governor is ready to walk the list of idle states and choose one of them. For this purpose, it compares the target residency of each state with the predicted idle duration and the exit latency of it with the with the latency limit coming from the power management quality of service, or }(hjV hhhNhNubj)}(h`PM QoS `_h]hPM QoS}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]namePM QoSj cpu-pm-qosuh1jhjV jKubj)}(h h]h}(h]h ]h"]pm qosah$]h&]jjn uh1jj cpu-pm-qoshjV jKubh, framework. It selects the state with the target residency closest to the predicted idle duration, but still below it, and exit latency that does not exceed the limit.}(hjV hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM=hj hhubj)}(hX7In the final step the governor may still need to refine the idle state selection if it has not decided to `stop the scheduler tick `_. That happens if the idle duration predicted by it is less than the tick period and the tick has not been stopped already (in a previous iteration of the idle loop). Then, the sleep length used in the previous computations may not reflect the real time until the closest timer event and if it really is greater than that time, the governor may need to select a shallower state with a suitable target residency.h](hjIn the final step the governor may still need to refine the idle state selection if it has not decided to }(hj hhhNhNubj)}(h0`stop the scheduler tick `_h]hstop the scheduler tick}(hj hhhNhNubah}(h]h ]h"]h$]h&]namestop the scheduler tickjj8 uh1jhj jKubj)}(h h]h}(h]h ]h"]stop the scheduler tickah$]h&]jj8 uh1jjidle-cpus-and-tickhj jKubhX. That happens if the idle duration predicted by it is less than the tick period and the tick has not been stopped already (in a previous iteration of the idle loop). Then, the sleep length used in the previous computations may not reflect the real time until the closest timer event and if it really is greater than that time, the governor may need to select a shallower state with a suitable target residency.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMEhj hhubj)}(h .. _teo-gov:h]h}(h]h ]h"]h$]h&]jjuh1jhMhj hhhhjKubeh}(h](the-menu-governorj} eh ]h"](the menu governormenu-goveh$]h&]uh1jhjhhhhhMj }j js sj }j} js sjKubj)}(hhh](j)}(h(The Timer Events Oriented (TEO) Governorh]h(The Timer Events Oriented (TEO) Governor}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hhhhhMRubj)}(hX:The timer events oriented (TEO) governor is an alternative ``CPUIdle`` governor for tickless systems. It follows the same basic strategy as the ``menu`` `one `_: it always tries to find the deepest idle state suitable for the given conditions. However, it applies a different approach to that problem.h](h;The timer events oriented (TEO) governor is an alternative }(hj hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubhK governor for tickless systems. It follows the same basic strategy as the }(hj hhhNhNubjP)}(h``menu``h]hmenu}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubh }(hj hhhNhNubj)}(h`one `_h]hone}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameonejj} uh1jhj jKubj)}(h h]h}(h]h ]h"]oneah$]h&]jj} uh1jjmenu-govhj jKubh: it always tries to find the deepest idle state suitable for the given conditions. However, it applies a different approach to that problem.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMThj hhubj)}(hXThe idea of this governor is based on the observation that on many systems timer interrupts are two or more orders of magnitude more frequent than any other interrupt types, so they are likely to dominate CPU wakeup patterns. Moreover, in principle, the time when the next timer event is going to occur can be determined at the idle state selection time, although doing that may be costly, so it can be regarded as the most reliable source of information for idle state selection.h]hXThe idea of this governor is based on the observation that on many systems timer interrupts are two or more orders of magnitude more frequent than any other interrupt types, so they are likely to dominate CPU wakeup patterns. Moreover, in principle, the time when the next timer event is going to occur can be determined at the idle state selection time, although doing that may be costly, so it can be regarded as the most reliable source of information for idle state selection.}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK hj hhubj)}(hXXOf course, non-timer wakeup sources are more important in some use cases, but even then it is generally unnecessary to consider idle duration values greater than the time time till the next timer event, referred as the sleep length in what follows, because the closest timer will ultimately wake up the CPU anyway unless it is woken up earlier.h]hXXOf course, non-timer wakeup sources are more important in some use cases, but even then it is generally unnecessary to consider idle duration values greater than the time time till the next timer event, referred as the sleep length in what follows, because the closest timer will ultimately wake up the CPU anyway unless it is woken up earlier.}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKhj hhubj)}(hX3However, since obtaining the sleep length may be costly, the governor first checks if it can select a shallow idle state using wakeup pattern information from recent times, in which case it can do without knowing the sleep length at all. For this purpose, it counts CPU wakeup events and looks for an idle state whose target residency has not exceeded the idle duration (measured after wakeup) in the majority of relevant recent cases. If the target residency of that state is small enough, it may be used right away and the sleep length need not be determined.h]hX3However, since obtaining the sleep length may be costly, the governor first checks if it can select a shallow idle state using wakeup pattern information from recent times, in which case it can do without knowing the sleep length at all. For this purpose, it counts CPU wakeup events and looks for an idle state whose target residency has not exceeded the idle duration (measured after wakeup) in the majority of relevant recent cases. If the target residency of that state is small enough, it may be used right away and the sleep length need not be determined.}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKhj hhubj)}(hXThe computations carried out by this governor are based on using bins whose boundaries are aligned with the target residency parameter values of the CPU idle states provided by the ``CPUIdle`` driver in the ascending order. That is, the first bin spans from 0 up to, but not including, the target residency of the second idle state (idle state 1), the second bin spans from the target residency of idle state 1 up to, but not including, the target residency of idle state 2, the third bin spans from the target residency of idle state 2 up to, but not including, the target residency of idle state 3 and so on. The last bin spans from the target residency of the deepest idle state supplied by the driver to infinity.h](hThe computations carried out by this governor are based on using bins whose boundaries are aligned with the target residency parameter values of the CPU idle states provided by the }(hjX hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjX ubhX driver in the ascending order. That is, the first bin spans from 0 up to, but not including, the target residency of the second idle state (idle state 1), the second bin spans from the target residency of idle state 1 up to, but not including, the target residency of idle state 2, the third bin spans from the target residency of idle state 2 up to, but not including, the target residency of idle state 3 and so on. The last bin spans from the target residency of the deepest idle state supplied by the driver to infinity.}(hjX hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK!hj hhubj)}(hTwo metrics called "hits" and "intercepts" are associated with each bin. They are updated every time before selecting an idle state for the given CPU in accordance with what happened last time.h]hTwo metrics called “hits” and “intercepts” are associated with each bin. They are updated every time before selecting an idle state for the given CPU in accordance with what happened last time.}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK,hj hhubj)}(hX"The "hits" metric reflects the relative frequency of situations in which the sleep length and the idle duration measured after CPU wakeup fall into the same bin (that is, the CPU appears to wake up "on time" relative to the sleep length). In turn, the "intercepts" metric reflects the relative frequency of non-timer wakeup events for which the measured idle duration falls into a bin that corresponds to an idle state shallower than the one whose bin is fallen into by the sleep length (these events are also referred to as "intercepts" below).h]hX2The “hits” metric reflects the relative frequency of situations in which the sleep length and the idle duration measured after CPU wakeup fall into the same bin (that is, the CPU appears to wake up “on time” relative to the sleep length). In turn, the “intercepts” metric reflects the relative frequency of non-timer wakeup events for which the measured idle duration falls into a bin that corresponds to an idle state shallower than the one whose bin is fallen into by the sleep length (these events are also referred to as “intercepts” below).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK0hj hhubj)}(hThe governor also counts "intercepts" with the measured idle duration below the tick period length and uses this information when deciding whether or not to stop the scheduler tick.h]hThe governor also counts “intercepts” with the measured idle duration below the tick period length and uses this information when deciding whether or not to stop the scheduler tick.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK9hj hhubj)}(hIn order to select an idle state for a CPU, the governor takes the following steps (modulo the possible latency constraint that must be taken into account too):h]hIn order to select an idle state for a CPU, the governor takes the following steps (modulo the possible latency constraint that must be taken into account too):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK=hj hhubhenumerated_list)}(hhh](h list_item)}(hXFind the deepest enabled CPU idle state (the candidate idle state) and compute 2 sums as follows: - The sum of the "hits" metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a timer). - The sum of the "intercepts" metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a non-timer wakeup source). h](j)}(haFind the deepest enabled CPU idle state (the candidate idle state) and compute 2 sums as follows:h]haFind the deepest enabled CPU idle state (the candidate idle state) and compute 2 sums as follows:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKAhj ubh bullet_list)}(hhh](j )}(hThe sum of the "hits" metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a timer). h]j)}(hThe sum of the "hits" metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a timer).h]hThe sum of the “hits” metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a timer).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKDhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hThe sum of the "intercepts" metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a non-timer wakeup source). h]j)}(hThe sum of the "intercepts" metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a non-timer wakeup source).h]hThe sum of the “intercepts” metric for all of the idle states shallower than the candidate one (it represents the cases in which the CPU was likely woken up by a non-timer wakeup source).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKHhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]bullet-uh1j hj hKDhj ubeh}(h]h ]h"]h$]h&]uh1j hj ubj )}(hXmIf the second sum computed in step 1 is greater than a half of the sum of both metrics for the candidate state bin and all subsequent bins(if any), a shallower idle state is likely to be more suitable, so look for it. - Traverse the enabled idle states shallower than the candidate one in the descending order. - For each of them compute the sum of the "intercepts" metrics over all of the idle states between it and the candidate one (including the former and excluding the latter). - If this sum is greater than a half of the second sum computed in step 1, use the given idle state as the new candidate one. h](j)}(hIf the second sum computed in step 1 is greater than a half of the sum of both metrics for the candidate state bin and all subsequent bins(if any), a shallower idle state is likely to be more suitable, so look for it.h]hIf the second sum computed in step 1 is greater than a half of the sum of both metrics for the candidate state bin and all subsequent bins(if any), a shallower idle state is likely to be more suitable, so look for it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKLhjubj )}(hhh](j )}(h[Traverse the enabled idle states shallower than the candidate one in the descending order. h]j)}(hZTraverse the enabled idle states shallower than the candidate one in the descending order.h]hZTraverse the enabled idle states shallower than the candidate one in the descending order.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKPhj*ubah}(h]h ]h"]h$]h&]uh1j hj'ubj )}(hFor each of them compute the sum of the "intercepts" metrics over all of the idle states between it and the candidate one (including the former and excluding the latter). h]j)}(hFor each of them compute the sum of the "intercepts" metrics over all of the idle states between it and the candidate one (including the former and excluding the latter).h]hFor each of them compute the sum of the “intercepts” metrics over all of the idle states between it and the candidate one (including the former and excluding the latter).}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKShjCubah}(h]h ]h"]h$]h&]uh1j hj'ubj )}(h|If this sum is greater than a half of the second sum computed in step 1, use the given idle state as the new candidate one. h]j)}(h{If this sum is greater than a half of the second sum computed in step 1, use the given idle state as the new candidate one.h]h{If this sum is greater than a half of the second sum computed in step 1, use the given idle state as the new candidate one.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKWhj\ubah}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ]h"]h$]h&]j j uh1j hj<hKPhjubeh}(h]h ]h"]h$]h&]uh1j hj ubj )}(hIf the current candidate state is state 0 or its target residency is short enough, return it and prevent the scheduler tick from being stopped. h]j)}(hIf the current candidate state is state 0 or its target residency is short enough, return it and prevent the scheduler tick from being stopped.h]hIf the current candidate state is state 0 or its target residency is short enough, return it and prevent the scheduler tick from being stopped.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chKZhjubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hObtain the sleep length value and check if it is below the target residency of the current candidate state, in which case a new shallower candidate state needs to be found, so look for it. h]j)}(hObtain the sleep length value and check if it is below the target residency of the current candidate state, in which case a new shallower candidate state needs to be found, so look for it.h]hObtain the sleep length value and check if it is below the target residency of the current candidate state, in which case a new shallower candidate state needs to be found, so look for it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/admin-guide/pm/cpuidle:431: ./drivers/cpuidle/governors/teo.chK]hjubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j hj hhhNhNubj)}(h.. _idle-states-representation:h]h}(h]h ]h"]h$]h&]jidle-states-representationuh1jhMhj hhhhjKubeh}(h](&the-timer-events-oriented-teo-governorjeh ]h"]((the timer events oriented (teo) governorteo-goveh$]h&]uh1jhjhhhhhMRj }jj sj }jj sjKubj)}(hhh](j)}(hRepresentation of Idle Statesh]hRepresentation of Idle States}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhM_ubj)}(hXFor the CPU idle time management purposes all of the physical idle states supported by the processor have to be represented as a one-dimensional array of |struct cpuidle_state| objects each allowing an individual (logical) CPU to ask the processor hardware to enter an idle state of certain properties. If there is a hierarchy of units in the processor, one |struct cpuidle_state| object can cover a combination of idle states supported by the units at different levels of the hierarchy. In that case, the `target residency and exit latency parameters of it `_, must reflect the properties of the idle state at the deepest level (i.e. the idle state of the unit containing all of the other units).h](hFor the CPU idle time management purposes all of the physical idle states supported by the processor have to be represented as a one-dimensional array of }(hjhhhNhNubh)}(hjMh]jP)}(hjMh]hstruct cpuidle_state}(hjhhhNhNubah}(h]h ](j[j\j]eh"]h$]h&]uh1jOhNhNhjubah}(h]h ]h"]h$]h&]refdocjh refdomainj\reftypejk refexplicitrefwarn reftargetjouh1hhhhKhjhhubh objects each allowing an individual (logical) CPU to ask the processor hardware to enter an idle state of certain properties. If there is a hierarchy of units in the processor, one }(hjhhhNhNubh)}(hjMh]jP)}(hjMh]hstruct cpuidle_state}(hjhhhNhNubah}(h]h ](j[j\j]eh"]h$]h&]uh1jOhNhNhj ubah}(h]h ]h"]h$]h&]refdocjh refdomainj\reftypejk refexplicitrefwarn reftargetjouh1hhhhKhjhhubh object can cover a combination of idle states supported by the units at different levels of the hierarchy. In that case, the }(hjhhhNhNubj)}(hB`target residency and exit latency parameters of it `_h]h2target residency and exit latency parameters of it}(hj-hhhNhNubah}(h]h ]h"]h$]h&]name2target residency and exit latency parameters of itjjuh1jhjjKubj)}(h h]h}(h]h ]h"]2target residency and exit latency parameters of itah$]h&]jjuh1jj idle-loophjjKubh, must reflect the properties of the idle state at the deepest level (i.e. the idle state of the unit containing all of the other units).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMahjhhubj)}(hXNFor example, take a processor with two cores in a larger unit referred to as a "module" and suppose that asking the hardware to enter a specific idle state (say "X") at the "core" level by one core will trigger the module to try to enter a specific idle state of its own (say "MX") if the other core is in idle state "X" already. In other words, asking for idle state "X" at the "core" level gives the hardware a license to go as deep as to idle state "MX" at the "module" level, but there is no guarantee that this is going to happen (the core asking for idle state "X" may just end up in that state by itself instead). Then, the target residency of the |struct cpuidle_state| object representing idle state "X" must reflect the minimum time to spend in idle state "MX" of the module (including the time needed to enter it), because that is the minimum time the CPU needs to be idle to save any energy in case the hardware enters that state. Analogously, the exit latency parameter of that object must cover the exit time of idle state "MX" of the module (and usually its entry time too), because that is the maximum delay between a wakeup signal and the time the CPU will start to execute the first new instruction (assuming that both cores in the module will always be ready to execute instructions as soon as the module becomes operational as a whole).h](hXFor example, take a processor with two cores in a larger unit referred to as a “module” and suppose that asking the hardware to enter a specific idle state (say “X”) at the “core” level by one core will trigger the module to try to enter a specific idle state of its own (say “MX”) if the other core is in idle state “X” already. In other words, asking for idle state “X” at the “core” level gives the hardware a license to go as deep as to idle state “MX” at the “module” level, but there is no guarantee that this is going to happen (the core asking for idle state “X” may just end up in that state by itself instead). Then, the target residency of the }(hjShhhNhNubh)}(hjMh]jP)}(hjMh]hstruct cpuidle_state}(hj^hhhNhNubah}(h]h ](j[j\j]eh"]h$]h&]uh1jOhNhNhj[ubah}(h]h ]h"]h$]h&]refdocjh refdomainj\reftypejk refexplicitrefwarn reftargetjouh1hhhhKhjShhubhX object representing idle state “X” must reflect the minimum time to spend in idle state “MX” of the module (including the time needed to enter it), because that is the minimum time the CPU needs to be idle to save any energy in case the hardware enters that state. Analogously, the exit latency parameter of that object must cover the exit time of idle state “MX” of the module (and usually its entry time too), because that is the maximum delay between a wakeup signal and the time the CPU will start to execute the first new instruction (assuming that both cores in the module will always be ready to execute instructions as soon as the module becomes operational as a whole).}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMlhjhhubj)}(hXThere are processors without direct coordination between different levels of the hierarchy of units inside them, however. In those cases asking for an idle state at the "core" level does not automatically affect the "module" level, for example, in any way and the ``CPUIdle`` driver is responsible for the entire handling of the hierarchy. Then, the definition of the idle state objects is entirely up to the driver, but still the physical properties of the idle state that the processor hardware finally goes into must always follow the parameters used by the governor for idle state selection (for instance, the actual exit latency of that idle state must not exceed the exit latency parameter of the idle state object selected by the governor).h](hXThere are processors without direct coordination between different levels of the hierarchy of units inside them, however. In those cases asking for an idle state at the “core” level does not automatically affect the “module” level, for example, in any way and the }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhX driver is responsible for the entire handling of the hierarchy. Then, the definition of the idle state objects is entirely up to the driver, but still the physical properties of the idle state that the processor hardware finally goes into must always follow the parameters used by the governor for idle state selection (for instance, the actual exit latency of that idle state must not exceed the exit latency parameter of the idle state object selected by the governor).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hX In addition to the target residency and exit latency idle state parameters discussed above, the objects representing idle states each contain a few other parameters describing the idle state and a pointer to the function to run in order to ask the hardware to enter that state. Also, for each |struct cpuidle_state| object, there is a corresponding :c:type:`struct cpuidle_state_usage ` one containing usage statistics of the given idle state. That information is exposed by the kernel via ``sysfs``.h](hX&In addition to the target residency and exit latency idle state parameters discussed above, the objects representing idle states each contain a few other parameters describing the idle state and a pointer to the function to run in order to ask the hardware to enter that state. Also, for each }(hjhhhNhNubh)}(hjMh]jP)}(hjMh]hstruct cpuidle_state}(hjhhhNhNubah}(h]h ](j[j\j]eh"]h$]h&]uh1jOhNhNhjubah}(h]h ]h"]h$]h&]refdocjh refdomainj\reftypejk refexplicitrefwarn reftargetjouh1hhhhKhjhhubh" object, there is a corresponding }(hjhhhNhNubh)}(h::c:type:`struct cpuidle_state_usage `h]jP)}(hjh]hstruct cpuidle_state_usage}(hjhhhNhNubah}(h]h ](j[j\c-typeeh"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]refdocjh refdomainj\reftypetype refexplicitrefwarnjncpuidle_state_usageuh1hhhhMhjubhi one containing usage statistics of the given idle state. That information is exposed by the kernel via }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXFor each CPU in the system, there is a :file:`/sys/devices/system/cpu/cpu/cpuidle/` directory in ``sysfs``, where the number ```` is assigned to the given CPU at the initialization time. That directory contains a set of subdirectories called :file:`state0`, :file:`state1` and so on, up to the number of idle state objects defined for the given CPU minus one. Each of these directories corresponds to one idle state object and the larger the number in its name, the deeper the (effective) idle state represented by it. Each of them contains a number of files (attributes) representing the properties of the idle state object corresponding to it, as follows:h](h'For each CPU in the system, there is a }(hjhhhNhNubjP)}(h/:file:`/sys/devices/system/cpu/cpu/cpuidle/`h]h'/sys/devices/system/cpu/cpu/cpuidle/}(hj hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh directory in }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh, where the number }(hjhhhNhNubjP)}(h````h]h}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhr is assigned to the given CPU at the initialization time. That directory contains a set of subdirectories called }(hjhhhNhNubjP)}(h:file:`state0`h]hstate0}(hjEhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh, }(hjhhhNhNubjP)}(h:file:`state1`h]hstate1}(hjZhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubhX and so on, up to the number of idle state objects defined for the given CPU minus one. Each of these directories corresponds to one idle state object and the larger the number in its name, the deeper the (effective) idle state represented by it. Each of them contains a number of files (attributes) representing the properties of the idle state object corresponding to it, as follows:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubhdefinition_list)}(hhh](hdefinition_list_item)}(h``above`` Total number of times this idle state had been asked for, but the observed idle duration was certainly too short to match its target residency. h](hterm)}(h ``above``h]jP)}(hjh]habove}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhj|ubh definition)}(hhh]j)}(hTotal number of times this idle state had been asked for, but the observed idle duration was certainly too short to match its target residency.h]hTotal number of times this idle state had been asked for, but the observed idle duration was certainly too short to match its target residency.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwubj{)}(h``below`` Total number of times this idle state had been asked for, but certainly a deeper idle state would have been a better match for the observed idle duration. h](j)}(h ``below``h]jP)}(hjh]hbelow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(hTotal number of times this idle state had been asked for, but certainly a deeper idle state would have been a better match for the observed idle duration.h]hTotal number of times this idle state had been asked for, but certainly a deeper idle state would have been a better match for the observed idle duration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(h(``desc`` Description of the idle state. h](j)}(h``desc``h]jP)}(hjh]hdesc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(hDescription of the idle state.h]hDescription of the idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(h8``disable`` Whether or not this idle state is disabled. h](j)}(h ``disable``h]jP)}(hj.h]hdisable}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj,ubah}(h]h ]h"]h$]h&]uh1jhhhMhj(ubj)}(hhh]j)}(h+Whether or not this idle state is disabled.h]h+Whether or not this idle state is disabled.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjCubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(hN``default_status`` The default status of this state, "enabled" or "disabled". h](j)}(h``default_status``h]jP)}(hjfh]hdefault_status}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjdubah}(h]h ]h"]h$]h&]uh1jhhhMhj`ubj)}(hhh]j)}(h:The default status of this state, "enabled" or "disabled".h]hBThe default status of this state, “enabled” or “disabled”.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj{ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(h<``latency`` Exit latency of the idle state in microseconds. h](j)}(h ``latency``h]jP)}(hjh]hlatency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(h/Exit latency of the idle state in microseconds.h]h/Exit latency of the idle state in microseconds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(h!``name`` Name of the idle state. h](j)}(h``name``h]jP)}(hjh]hname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(hName of the idle state.h]hName of the idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(h```power`` Power drawn by hardware in this idle state in milliwatts (if specified, 0 otherwise). h](j)}(h ``power``h]jP)}(hjh]hpower}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj ubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(hUPower drawn by hardware in this idle state in milliwatts (if specified, 0 otherwise).h]hUPower drawn by hardware in this idle state in milliwatts (if specified, 0 otherwise).}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(hB``residency`` Target residency of the idle state in microseconds. h](j)}(h ``residency``h]jP)}(hjFh]h residency}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjDubah}(h]h ]h"]h$]h&]uh1jhhhMhj@ubj)}(hhh]j)}(h3Target residency of the idle state in microseconds.h]h3Target residency of the idle state in microseconds.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(hk``time`` Total time spent in this idle state by the given CPU (as measured by the kernel) in microseconds. h](j)}(h``time``h]jP)}(hj~h]htime}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj|ubah}(h]h ]h"]h$]h&]uh1jhhhMhjxubj)}(hhh]j)}(haTotal time spent in this idle state by the given CPU (as measured by the kernel) in microseconds.h]haTotal time spent in this idle state by the given CPU (as measured by the kernel) in microseconds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(hg``usage`` Total number of times the hardware has been asked by the given CPU to enter this idle state. h](j)}(h ``usage``h]jP)}(hjh]husage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(h\Total number of times the hardware has been asked by the given CPU to enter this idle state.h]h\Total number of times the hardware has been asked by the given CPU to enter this idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubj{)}(he``rejected`` Total number of times a request to enter this idle state on the given CPU was rejected. h](j)}(h ``rejected``h]jP)}(hjh]hrejected}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]j)}(hWTotal number of times a request to enter this idle state on the given CPU was rejected.h]hWTotal number of times a request to enter this idle state on the given CPU was rejected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhhhMhjwhhubeh}(h]h ]h"]h$]h&]uh1juhjhhhhhNubj)}(hXThe :file:`desc` and :file:`name` files both contain strings. The difference between them is that the name is expected to be more concise, while the description may be longer and it may contain white space or special characters. The other files listed above contain integer numbers.h](hThe }(hj&hhhNhNubjP)}(h :file:`desc`h]hdesc}(hj.hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj&ubh and }(hj&hhhNhNubjP)}(h :file:`name`h]hname}(hjChhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj&ubh files both contain strings. The difference between them is that the name is expected to be more concise, while the description may be longer and it may contain white space or special characters. The other files listed above contain integer numbers.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXThe :file:`disable` attribute is the only writeable one. If it contains 1, the given idle state is disabled for this particular CPU, which means that the governor will never select it for this particular CPU and the ``CPUIdle`` driver will never ask the hardware to enter it for that CPU as a result. However, disabling an idle state for one CPU does not prevent it from being asked for by the other CPUs, so it must be disabled for all of them in order to never be asked for by any of them. [Note that, due to the way the ``ladder`` governor is implemented, disabling an idle state prevents that governor from selecting any idle states deeper than the disabled one too.]h](hThe }(hj^hhhNhNubjP)}(h:file:`disable`h]hdisable}(hjfhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj^ubh attribute is the only writeable one. If it contains 1, the given idle state is disabled for this particular CPU, which means that the governor will never select it for this particular CPU and the }(hj^hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj^ubhX) driver will never ask the hardware to enter it for that CPU as a result. However, disabling an idle state for one CPU does not prevent it from being asked for by the other CPUs, so it must be disabled for all of them in order to never be asked for by any of them. [Note that, due to the way the }(hj^hhhNhNubjP)}(h ``ladder``h]hladder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj^ubh governor is implemented, disabling an idle state prevents that governor from selecting any idle states deeper than the disabled one too.]}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXIf the :file:`disable` attribute contains 0, the given idle state is enabled for this particular CPU, but it still may be disabled for some or all of the other CPUs in the system at the same time. Writing 1 to it causes the idle state to be disabled for this particular CPU and writing 0 to it allows the governor to take it into consideration for the given CPU and the driver to ask for it, unless that state was disabled globally in the driver (in which case it cannot be used at all).h](hIf the }(hjhhhNhNubjP)}(h:file:`disable`h]hdisable}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubhX attribute contains 0, the given idle state is enabled for this particular CPU, but it still may be disabled for some or all of the other CPUs in the system at the same time. Writing 1 to it causes the idle state to be disabled for this particular CPU and writing 0 to it allows the governor to take it into consideration for the given CPU and the driver to ask for it, unless that state was disabled globally in the driver (in which case it cannot be used at all).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXThe :file:`power` attribute is not defined very well, especially for idle state objects representing combinations of idle states at different levels of the hierarchy of units in the processor, and it generally is hard to obtain idle state power numbers for complex hardware, so :file:`power` often contains 0 (not available) and if it contains a nonzero number, that number may not be very accurate and it should not be relied on for anything meaningful.h](hThe }(hjhhhNhNubjP)}(h :file:`power`h]hpower}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubhX attribute is not defined very well, especially for idle state objects representing combinations of idle states at different levels of the hierarchy of units in the processor, and it generally is hard to obtain idle state power numbers for complex hardware, so }(hjhhhNhNubjP)}(h :file:`power`h]hpower}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh often contains 0 (not available) and if it contains a nonzero number, that number may not be very accurate and it should not be relied on for anything meaningful.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXThe number in the :file:`time` file generally may be greater than the total time really spent by the given CPU in the given idle state, because it is measured by the kernel and it may not cover the cases in which the hardware refused to enter this idle state and entered a shallower one instead of it (or even it did not enter any idle state at all). The kernel can only measure the time span between asking the hardware to enter an idle state and the subsequent wakeup of the CPU and it cannot say what really happened in the meantime at the hardware level. Moreover, if the idle state object in question represents a combination of idle states at different levels of the hierarchy of units in the processor, the kernel can never say how deep the hardware went down the hierarchy in any particular case. For these reasons, the only reliable way to find out how much time has been spent by the hardware in different idle states supported by it is to use idle state residency counters in the hardware, if available.h](hThe number in the }(hjhhhNhNubjP)}(h :file:`time`h]htime}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubhX file generally may be greater than the total time really spent by the given CPU in the given idle state, because it is measured by the kernel and it may not cover the cases in which the hardware refused to enter this idle state and entered a shallower one instead of it (or even it did not enter any idle state at all). The kernel can only measure the time span between asking the hardware to enter an idle state and the subsequent wakeup of the CPU and it cannot say what really happened in the meantime at the hardware level. Moreover, if the idle state object in question represents a combination of idle states at different levels of the hierarchy of units in the processor, the kernel can never say how deep the hardware went down the hierarchy in any particular case. For these reasons, the only reliable way to find out how much time has been spent by the hardware in different idle states supported by it is to use idle state residency counters in the hardware, if available.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXjGenerally, an interrupt received when trying to enter an idle state causes the idle state entry request to be rejected, in which case the ``CPUIdle`` driver may return an error code to indicate that this was the case. The :file:`usage` and :file:`rejected` files report the number of times the given idle state was entered successfully or rejected, respectively.h](hGenerally, an interrupt received when trying to enter an idle state causes the idle state entry request to be rejected, in which case the }(hj#hhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj#ubhI driver may return an error code to indicate that this was the case. The }(hj#hhhNhNubjP)}(h :file:`usage`h]husage}(hj=hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj#ubh and }(hj#hhhNhNubjP)}(h:file:`rejected`h]hrejected}(hjRhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj#ubhj files report the number of times the given idle state was entered successfully or rejected, respectively.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(h.. _cpu-pm-qos:h]h}(h]h ]h"]h$]h&]jjn uh1jhMQhjhhhhjKubeh}(h](representation-of-idle-statesjeh ]h"](representation of idle statesidle-states-representationeh$]h&]uh1jhjhhhhhM_j }j}jsj }jjsjKubj)}(hhh](j)}(h,Power Management Quality of Service for CPUsh]h,Power Management Quality of Service for CPUs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhMubj)}(hThe power management quality of service (PM QoS) framework in the Linux kernel allows kernel code and user space processes to set constraints on various energy-efficiency features of the kernel to prevent performance from dropping below a required level.h]hThe power management quality of service (PM QoS) framework in the Linux kernel allows kernel code and user space processes to set constraints on various energy-efficiency features of the kernel to prevent performance from dropping below a required level.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXCPU idle time management can be affected by PM QoS in two ways, through the global CPU latency limit and through the resume latency constraints for individual CPUs. Kernel code (e.g. device drivers) can set both of them with the help of special internal interfaces provided by the PM QoS framework. User space can modify the former by opening the :file:`cpu_dma_latency` special device file under :file:`/dev/` and writing a binary value (interpreted as a signed 32-bit integer) to it. In turn, the resume latency constraint for a CPU can be modified from user space by writing a string (representing a signed 32-bit integer) to the :file:`power/pm_qos_resume_latency_us` file under :file:`/sys/devices/system/cpu/cpu/` in ``sysfs``, where the CPU number ```` is allocated at the system initialization time. Negative values will be rejected in both cases and, also in both cases, the written integer number will be interpreted as a requested PM QoS constraint in microseconds.h](hX]CPU idle time management can be affected by PM QoS in two ways, through the global CPU latency limit and through the resume latency constraints for individual CPUs. Kernel code (e.g. device drivers) can set both of them with the help of special internal interfaces provided by the PM QoS framework. User space can modify the former by opening the }(hjhhhNhNubjP)}(h:file:`cpu_dma_latency`h]hcpu_dma_latency}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh special device file under }(hjhhhNhNubjP)}(h :file:`/dev/`h]h/dev/}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh and writing a binary value (interpreted as a signed 32-bit integer) to it. In turn, the resume latency constraint for a CPU can be modified from user space by writing a string (representing a signed 32-bit integer) to the }(hjhhhNhNubjP)}(h&:file:`power/pm_qos_resume_latency_us`h]hpower/pm_qos_resume_latency_us}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh file under }(hjhhhNhNubjP)}(h':file:`/sys/devices/system/cpu/cpu/`h]h/sys/devices/system/cpu/cpu/}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh in }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh, where the CPU number }(hjhhhNhNubjP)}(h````h]h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh is allocated at the system initialization time. Negative values will be rejected in both cases and, also in both cases, the written integer number will be interpreted as a requested PM QoS constraint in microseconds.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXThe requested value is not automatically applied as a new constraint, however, as it may be less restrictive (greater in this particular case) than another constraint previously requested by someone else. For this reason, the PM QoS framework maintains a list of requests that have been made so far for the global CPU latency limit and for each individual CPU, aggregates them and applies the effective (minimum in this particular case) value as the new constraint.h]hXThe requested value is not automatically applied as a new constraint, however, as it may be less restrictive (greater in this particular case) than another constraint previously requested by someone else. For this reason, the PM QoS framework maintains a list of requests that have been made so far for the global CPU latency limit and for each individual CPU, aggregates them and applies the effective (minimum in this particular case) value as the new constraint.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hXIn fact, opening the :file:`cpu_dma_latency` special device file causes a new PM QoS request to be created and added to a global priority list of CPU latency limit requests and the file descriptor coming from the "open" operation represents that request. If that file descriptor is then used for writing, the number written to it will be associated with the PM QoS request represented by it as a new requested limit value. Next, the priority list mechanism will be used to determine the new effective value of the entire list of requests and that effective value will be set as a new CPU latency limit. Thus requesting a new limit value will only change the real limit if the effective "list" value is affected by it, which is the case if it is the minimum of the requested values in the list.h](hIn fact, opening the }(hj5hhhNhNubjP)}(h:file:`cpu_dma_latency`h]hcpu_dma_latency}(hj=hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj5ubhX special device file causes a new PM QoS request to be created and added to a global priority list of CPU latency limit requests and the file descriptor coming from the “open” operation represents that request. If that file descriptor is then used for writing, the number written to it will be associated with the PM QoS request represented by it as a new requested limit value. Next, the priority list mechanism will be used to determine the new effective value of the entire list of requests and that effective value will be set as a new CPU latency limit. Thus requesting a new limit value will only change the real limit if the effective “list” value is affected by it, which is the case if it is the minimum of the requested values in the list.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hThe process holding a file descriptor obtained by opening the :file:`cpu_dma_latency` special device file controls the PM QoS request associated with that file descriptor, but it controls this particular PM QoS request only.h](h>The process holding a file descriptor obtained by opening the }(hjXhhhNhNubjP)}(h:file:`cpu_dma_latency`h]hcpu_dma_latency}(hj`hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjXubh special device file controls the PM QoS request associated with that file descriptor, but it controls this particular PM QoS request only.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM'hjhhubj)}(hXClosing the :file:`cpu_dma_latency` special device file or, more precisely, the file descriptor obtained while opening it, causes the PM QoS request associated with that file descriptor to be removed from the global priority list of CPU latency limit requests and destroyed. If that happens, the priority list mechanism will be used again, to determine the new effective value for the whole list and that value will become the new limit.h](h Closing the }(hj{hhhNhNubjP)}(h:file:`cpu_dma_latency`h]hcpu_dma_latency}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhj{ubhX special device file or, more precisely, the file descriptor obtained while opening it, causes the PM QoS request associated with that file descriptor to be removed from the global priority list of CPU latency limit requests and destroyed. If that happens, the priority list mechanism will be used again, to determine the new effective value for the whole list and that value will become the new limit.}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM,hjhhubj)}(hXIn turn, for each CPU there is one resume latency PM QoS request associated with the :file:`power/pm_qos_resume_latency_us` file under :file:`/sys/devices/system/cpu/cpu/` in ``sysfs`` and writing to it causes this single PM QoS request to be updated regardless of which user space process does that. In other words, this PM QoS request is shared by the entire user space, so access to the file associated with it needs to be arbitrated to avoid confusion. [Arguably, the only legitimate use of this mechanism in practice is to pin a process to the CPU in question and let it use the ``sysfs`` interface to control the resume latency constraint for it.] It is still only a request, however. It is an entry in a priority list used to determine the effective value to be set as the resume latency constraint for the CPU in question every time the list of requests is updated this way or another (there may be other requests coming from kernel code in that list).h](hUIn turn, for each CPU there is one resume latency PM QoS request associated with the }(hjhhhNhNubjP)}(h&:file:`power/pm_qos_resume_latency_us`h]hpower/pm_qos_resume_latency_us}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh file under }(hjhhhNhNubjP)}(h':file:`/sys/devices/system/cpu/cpu/`h]h/sys/devices/system/cpu/cpu/}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jOhjubh in }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhX and writing to it causes this single PM QoS request to be updated regardless of which user space process does that. In other words, this PM QoS request is shared by the entire user space, so access to the file associated with it needs to be arbitrated to avoid confusion. [Arguably, the only legitimate use of this mechanism in practice is to pin a process to the CPU in question and let it use the }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhXq interface to control the resume latency constraint for it.] It is still only a request, however. It is an entry in a priority list used to determine the effective value to be set as the resume latency constraint for the CPU in question every time the list of requests is updated this way or another (there may be other requests coming from kernel code in that list).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM3hjhhubj)}(hX\CPU idle time governors are expected to regard the minimum of the global (effective) CPU latency limit and the effective resume latency constraint for the given CPU as the upper limit for the exit latency of the idle states that they are allowed to select for that CPU. They should never select any idle states with exit latency beyond that limit.h]hX\CPU idle time governors are expected to regard the minimum of the global (effective) CPU latency limit and the effective resume latency constraint for the given CPU as the upper limit for the exit latency of the idle states that they are allowed to select for that CPU. They should never select any idle states with exit latency beyond that limit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMAhjhhubeh}(h](,power-management-quality-of-service-for-cpusjn eh ]h"](,power management quality of service for cpus cpu-pm-qoseh$]h&]uh1jhjhhhhhMj }jjmsj }jn jmsjKubj)}(hhh](j)}(h+Idle States Control Via Kernel Command Lineh]h+Idle States Control Via Kernel Command Line}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhMIubj)}(hIn addition to the ``sysfs`` interface allowing individual idle states to be `disabled for individual CPUs `_, there are kernel command line parameters affecting CPU idle time management.h](hIn addition to the }(hj$hhhNhNubjP)}(h ``sysfs``h]hsysfs}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhj$ubh1 interface allowing individual idle states to be }(hj$hhhNhNubj)}(h=`disabled for individual CPUs `_h]hdisabled for individual CPUs}(hj>hhhNhNubah}(h]h ]h"]h$]h&]namedisabled for individual CPUsjjuh1jhj$jKubj)}(h h]h}(h]h ]h"]disabled for individual cpusah$]h&]jjuh1jjidle-states-representationhj$jKubhN, there are kernel command line parameters affecting CPU idle time management.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMKhjhhubj)}(hXThe ``cpuidle.off=1`` kernel command line option can be used to disable the CPU idle time management entirely. It does not prevent the idle loop from running on idle CPUs, but it prevents the CPU idle time governors and drivers from being invoked. If it is added to the kernel command line, the idle loop will ask the hardware to enter idle states on idle CPUs via the CPU architecture support code that is expected to provide a default mechanism for this purpose. That default mechanism usually is the least common denominator for all of the processors implementing the architecture (i.e. CPU instruction set) in question, however, so it is rather crude and not very energy-efficient. For this reason, it is not recommended for production use.h](hThe }(hjdhhhNhNubjP)}(h``cpuidle.off=1``h]h cpuidle.off=1}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjdubhX kernel command line option can be used to disable the CPU idle time management entirely. It does not prevent the idle loop from running on idle CPUs, but it prevents the CPU idle time governors and drivers from being invoked. If it is added to the kernel command line, the idle loop will ask the hardware to enter idle states on idle CPUs via the CPU architecture support code that is expected to provide a default mechanism for this purpose. That default mechanism usually is the least common denominator for all of the processors implementing the architecture (i.e. CPU instruction set) in question, however, so it is rather crude and not very energy-efficient. For this reason, it is not recommended for production use.}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMOhjhhubj)}(hXThe ``cpuidle.governor=`` kernel command line switch allows the ``CPUIdle`` governor to use to be specified. It has to be appended with a string matching the name of an available governor (e.g. ``cpuidle.governor=menu``) and that governor will be used instead of the default one. It is possible to force the ``menu`` governor to be used on the systems that use the ``ladder`` governor by default this way, for example.h](hThe }(hjhhhNhNubjP)}(h``cpuidle.governor=``h]hcpuidle.governor=}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh' kernel command line switch allows the }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubaHPh}(h]h ]h"]h$]h&]uh1jOhjubhx governor to use to be specified. It has to be appended with a string matching the name of an available governor (e.g. }(hjhhhNhNubjP)}(h``cpuidle.governor=menu``h]hcpuidle.governor=menu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhZ) and that governor will be used instead of the default one. It is possible to force the }(hjhhhNhNubjP)}(h``menu``h]hmenu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh1 governor to be used on the systems that use the }(hjhhhNhNubjP)}(h ``ladder``h]hladder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh+ governor by default this way, for example.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMZhjhhubj)}(hThe other kernel command line parameters controlling CPU idle time management described below are only relevant for the *x86* architecture and references to ``intel_idle`` affect Intel processors only.h](hxThe other kernel command line parameters controlling CPU idle time management described below are only relevant for the }(hjhhhNhNubj^)}(h*x86*h]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubh architecture and references to }(hjhhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh affect Intel processors only.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMahjhhubj)}(hX\The *x86* architecture support code recognizes three kernel command line options related to CPU idle time management: ``idle=poll``, ``idle=halt``, and ``idle=nomwait``. The first two of them disable the ``acpi_idle`` and ``intel_idle`` drivers altogether, which effectively causes the entire ``CPUIdle`` subsystem to be disabled and makes the idle loop invoke the architecture support code to deal with idle CPUs. How it does that depends on which of the two parameters is added to the kernel command line. In the ``idle=halt`` case, the architecture support code will use the ``HLT`` instruction of the CPUs (which, as a rule, suspends the execution of the program and causes the hardware to attempt to enter the shallowest available idle state) for this purpose, and if ``idle=poll`` is used, idle CPUs will execute a more or less "lightweight" sequence of instructions in a tight loop. [Note that using ``idle=poll`` is somewhat drastic in many cases, as preventing idle CPUs from saving almost any energy at all may not be the only effect of it. For example, on Intel hardware it effectively prevents CPUs from using P-states (see |cpufreq|) that require any number of CPUs in a package to be idle, so it very well may hurt single-thread computations performance as well as energy-efficiency. Thus using it for performance reasons may not be a good idea at all.]h](hThe }(hjhhhNhNubj^)}(h*x86*h]hx86}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j]hjubhm architecture support code recognizes three kernel command line options related to CPU idle time management: }(hjhhhNhNubjP)}(h ``idle=poll``h]h idle=poll}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh, }(hjhhhNhNubjP)}(h ``idle=halt``h]h idle=halt}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh, and }(hjhhhNhNubjP)}(h``idle=nomwait``h]h idle=nomwait}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh%. The first two of them disable the }(hjhhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh and }(hjhhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh9 drivers altogether, which effectively causes the entire }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh subsystem to be disabled and makes the idle loop invoke the architecture support code to deal with idle CPUs. How it does that depends on which of the two parameters is added to the kernel command line. In the }(hjhhhNhNubjP)}(h ``idle=halt``h]h idle=halt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh2 case, the architecture support code will use the }(hjhhhNhNubjP)}(h``HLT``h]hHLT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh instruction of the CPUs (which, as a rule, suspends the execution of the program and causes the hardware to attempt to enter the shallowest available idle state) for this purpose, and if }(hjhhhNhNubjP)}(h ``idle=poll``h]h idle=poll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh~ is used, idle CPUs will execute a more or less “lightweight” sequence of instructions in a tight loop. [Note that using }(hjhhhNhNubjP)}(h ``idle=poll``h]h idle=poll}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh is somewhat drastic in many cases, as preventing idle CPUs from saving almost any energy at all may not be the only effect of it. For example, on Intel hardware it effectively prevents CPUs from using P-states (see }(hjhhhNhNubh)}(hj}h]j)}(hj}h]hCPU Performance Scaling}(hjhhhNhNubah}(h]h ](j[jjeh"]h$]h&]uh1jhNhNhjubah}(h]h ]h"]h$]h&]refdocjh refdomainjreftypej refexplicitrefwarn reftargetjuh1hhhhKhjhhubh) that require any number of CPUs in a package to be idle, so it very well may hurt single-thread computations performance as well as energy-efficiency. Thus using it for performance reasons may not be a good idea at all.]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMehjhhubj)}(hXThe ``idle=nomwait`` option prevents the use of ``MWAIT`` instruction of the CPU to enter idle states. When this option is used, the ``acpi_idle`` driver will use the ``HLT`` instruction instead of ``MWAIT``. On systems running Intel processors, this option disables the ``intel_idle`` driver and forces the use of the ``acpi_idle`` driver instead. Note that in either case, ``acpi_idle`` driver will function only if all the information needed by it is in the system's ACPI tables.h](hThe }(hjhhhNhNubjP)}(h``idle=nomwait``h]h idle=nomwait}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh option prevents the use of }(hjhhhNhNubjP)}(h ``MWAIT``h]hMWAIT}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhL instruction of the CPU to enter idle states. When this option is used, the }(hjhhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh driver will use the }(hjhhhNhNubjP)}(h``HLT``h]hHLT}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh instruction instead of }(hjhhhNhNubjP)}(h ``MWAIT``h]hMWAIT}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh@. On systems running Intel processors, this option disables the }(hjhhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh" driver and forces the use of the }(hjhhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh+ driver instead. Note that in either case, }(hjhhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh` driver will function only if all the information needed by it is in the system’s ACPI tables.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMyhjhhubj)}(hXIn addition to the architecture-level kernel command line options affecting CPU idle time management, there are parameters affecting individual ``CPUIdle`` drivers that can be passed to them via the kernel command line. Specifically, the ``intel_idle.max_cstate=`` and ``processor.max_cstate=`` parameters, where ```` is an idle state index also used in the name of the given state's directory in ``sysfs`` (see `Representation of Idle States `_), causes the ``intel_idle`` and ``acpi_idle`` drivers, respectively, to discard all of the idle states deeper than idle state ````. In that case, they will never ask for any of those idle states or expose them to the governor. [The behavior of the two drivers is different for ```` equal to ``0``. Adding ``intel_idle.max_cstate=0`` to the kernel command line disables the ``intel_idle`` driver and allows ``acpi_idle`` to be used, whereas ``processor.max_cstate=0`` is equivalent to ``processor.max_cstate=1``. Also, the ``acpi_idle`` driver is part of the ``processor`` kernel module that can be loaded separately and ``max_cstate=`` can be passed to it as a module parameter when it is loaded.]h](hIn addition to the architecture-level kernel command line options affecting CPU idle time management, there are parameters affecting individual }(hjhhhNhNubjP)}(h ``CPUIdle``h]hCPUIdle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhT drivers that can be passed to them via the kernel command line. Specifically, the }(hjhhhNhNubjP)}(h``intel_idle.max_cstate=``h]hintel_idle.max_cstate=}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh and }(hjhhhNhNubjP)}(h``processor.max_cstate=``h]hprocessor.max_cstate=}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh parameters, where }(hjhhhNhNubjP)}(h````h]h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhR is an idle state index also used in the name of the given state’s directory in }(hjhhhNhNubjP)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh (see }(hjhhhNhNubj)}(h>`Representation of Idle States `_h]hRepresentation of Idle States}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameRepresentation of Idle Statesjjuh1jhjjKubj)}(h h]h}(h]h ]h"]representation of idle statesah$]h&]jjuh1jjidle-states-representationhjjKubh), causes the }(hjhhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh and }hjsbjP)}(h ``acpi_idle``h]h acpi_idle}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubhQ drivers, respectively, to discard all of the idle states deeper than idle state }(hjhhhNhNubjP)}(h````h]h}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh. In that case, they will never ask for any of those idle states or expose them to the governor. [The behavior of the two drivers is different for }(hjhhhNhNubjP)}(h````h]h}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh equal to }(hjhhhNhNubjP)}(h``0``h]h0}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh . Adding }(hjhhhNhNubjP)}(h``intel_idle.max_cstate=0``h]hintel_idle.max_cstate=0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh) to the kernel command line disables the }(hjhhhNhNubjP)}(h``intel_idle``h]h intel_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh driver and allows }(hjhhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh to be used, whereas }(hjhhhNhNubjP)}(h``processor.max_cstate=0``h]hprocessor.max_cstate=0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh is equivalent to }(hjhhhNhNubjP)}(h``processor.max_cstate=1``h]hprocessor.max_cstate=1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh . Also, the }(hjhhhNhNubjP)}(h ``acpi_idle``h]h acpi_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh driver is part of the }(hjhhhNhNubjP)}(h ``processor``h]h processor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh1 kernel module that can be loaded separately and }(hjhhhNhNubjP)}(h``max_cstate=``h]hmax_cstate=}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jOhjubh> can be passed to it as a module parameter when it is loaded.]}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubeh}(h]+idle-states-control-via-kernel-command-lineah ]h"]+idle states control via kernel command lineah$]h&]uh1jhjhhhhhMIubeh}(h]cpu-idle-time-managementah ]h"]cpu idle time managementah$]h&]uh1jhhhhhhhK ubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(jN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjUerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets](jj9 jo j j j=jNj"esubstitution_defs}(hhhhhhj jjjj*jj9j-jHj<jWjKjfjZjujijjxjjjjjjjjjjjjjjjjj jjjj)jj8j,jGj;jVjJjejYjtjhjjwjjjjjjjjjjjjjjjjj jjj j(jj7j+jFj:jUjIjdjXjsjgjjvjjjjjjjjjjjjjjjjj jjj j'jj6j*jEj9jTjHjcjWjrjfjjujjjjjjjjjjjjjjjjjjjj j&jj5j)jDj8struct cpuidle_statejGjjwusubstitution_names}(amphߌaposhasthbrvbarj bsoljcentj*colonj9commajHcommatjWcopyjfcurrenjudarrjdegjdividejdollarjequalsjexcljfrac12jfrac14jfrac18jfrac34j frac38jfrac58j)frac78j8gtjGhalfjVhorbarjehyphenjtiexcljiquestjlaquojlarrjlcubjldquojlowbarjlparjlsqbjlsquoj ltjmicroj(middotj7nbspjFnotjUnumjdohmjsordfjordmjparajpercntjperiodjplusjplusmnjpoundjquestjquotj raquojrarrj'rcubj6rdquojEregjTrparjcrsqbjrrsquojsectjsemijshyjsoljsungjsup1jsup2jsup3jtimesjtradejuarrj&verbarj5yenjDstruct cpuidle_statejcpufreqjurefnames}(teo-gov](jjeidle-cpus-and-tick](j9 j( j j e cpu-pm-qos](jo j^ emenu-gov](j j e idle-loop](j=j-eidle-states-representation](jNj>j"jeurefids}(j](jj=ej8 ](j} j9 j ej} ](js j ej](j jej](jjNj"ejn ](jmjo eunameids}(j/j,jjjjjjj jj j j j8 j j j j} j j jjjjj}jj|jyjjn j j j'j$u nametypes}(j/jjjj j j j j j jjj}j|jj j'uh}(j,jjjDjjjjjjj jj8 j j j j} j j j jj jj jjjyjjn jj jj$ju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages](hsystem_message)}(hhh]j)}(hhh]h)Hyperlink target "teo" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1jubj)}(hhh]j)}(hhh]h>Hyperlink target "stopped by the idle loop" is not referenced.}hj:sbah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineKuh1jubj)}(hhh]j)}(hhh]h,Hyperlink target "pm qos" is not referenced.}hjTsbah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineM=uh1jubj)}(hhh]j)}(hhh]h=Hyperlink target "stop the scheduler tick" is not referenced.}hjnsbah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineMEuh1jubj)}(hhh]j)}(hhh]h)Hyperlink target "one" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineMTuh1jubj)}(hhh]j)}(hhh]hXHyperlink target "target residency and exit latency parameters of it" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineMauh1jubj)}(hhh]j)}(hhh]hBHyperlink target "disabled for individual cpus" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineMKuh1jubj)}(hhh]j)}(hhh]hCHyperlink target "representation of idle states" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]levelKtypej4sourcehlineMuh1jube transformerN include_log](Documentation/admin-guide/pm/cpuidle.rst(NNNNta decorationNhhub.