€•ê$      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ./translations/zh_CN/admin-guide/perf/xgene-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ./translations/zh_TW/admin-guide/perf/xgene-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ./translations/it_IT/admin-guide/perf/xgene-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ./translations/ja_JP/admin-guide/perf/xgene-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ./translations/ko_KR/admin-guide/perf/xgene-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ./translations/sp_SP/admin-guide/perf/xgene-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ0APM X-Gene SoC Performance Monitoring Unit (PMU)”h]”hŒ0APM X-Gene SoC Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒH/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/xgene-pmu.rst”h KubhŒ	paragraph”“”)”}”(hX;  X-Gene SoC PMU consists of various independent system device PMUs such as
L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
controller(s). These PMU devices are loosely architected to follow the
same model as the PMU for ARM cores. The PMUs share the same top level
interrupt and status CSR region.”h]”hX;  X-Gene SoC PMU consists of various independent system device PMUs such as
L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
controller(s). These PMU devices are loosely architected to follow the
same model as the PMU for ARM cores. The PMUs share the same top level
interrupt and status CSR region.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒPMU (perf) driver”h]”hŒPMU (perf) driver”…””}”(hhÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhÇhžhhŸh¶h Kubh¸)”}”(hŒÚThe xgene-pmu driver registers several perf PMU drivers. Each of the perf
driver provides description of its available events and configuration options
in sysfs, see /sys/bus/event_source/devices/<l3cX/iobX/mcbX/mcX>/.”h]”hŒÚThe xgene-pmu driver registers several perf PMU drivers. Each of the perf
driver provides description of its available events and configuration options
in sysfs, see /sys/bus/event_source/devices/<l3cX/iobX/mcbX/mcX>/.”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubh¸)”}”(hXA  The "format" directory describes format of the config (event ID),
config1 (agent ID) fields of the perf_event_attr structure. The "events"
directory provides configuration templates for all supported event types that
can be used with perf tool. For example, "l3c0/bank-fifo-full/" is an
equivalent of "l3c0/config=0x0b/".”h]”hXQ  The â€œformatâ€ directory describes format of the config (event ID),
config1 (agent ID) fields of the perf_event_attr structure. The â€œeventsâ€
directory provides configuration templates for all supported event types that
can be used with perf tool. For example, â€œl3c0/bank-fifo-full/â€ is an
equivalent of â€œl3c0/config=0x0b/â€.”…””}”(hhæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubh¸)”}”(hX’  Most of the SoC PMU has a specific list of agent ID used for monitoring
performance of a specific datapath. For example, agents of a L3 cache can be
a specific CPU or an I/O bridge. Each PMU has a set of 2 registers capable of
masking the agents from which the request come from. If the bit with
the bit number corresponding to the agent is set, the event is counted only if
it is caused by a request from that agent. Each agent ID bit is inversely mapped
to a corresponding bit in "config1" field. By default, the event will be
counted for all agent requests (config1 = 0x0). For all the supported agents of
each PMU, please refer to APM X-Gene User Manual.”h]”hX–  Most of the SoC PMU has a specific list of agent ID used for monitoring
performance of a specific datapath. For example, agents of a L3 cache can be
a specific CPU or an I/O bridge. Each PMU has a set of 2 registers capable of
masking the agents from which the request come from. If the bit with
the bit number corresponding to the agent is set, the event is counted only if
it is caused by a request from that agent. Each agent ID bit is inversely mapped
to a corresponding bit in â€œconfig1â€ field. By default, the event will be
counted for all agent requests (config1 = 0x0). For all the supported agents of
each PMU, please refer to APM X-Gene User Manual.”…””}”(hhôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubh¸)”}”(hŒœEach perf driver also provides a "cpumask" sysfs attribute, which contains a
single CPU ID of the processor which will be used to handle all the PMU events.”h]”hŒ Each perf driver also provides a â€œcpumaskâ€ sysfs attribute, which contains a
single CPU ID of the processor which will be used to handle all the PMU events.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K"hhÇhžhubh¸)”}”(hŒExample for perf tool use::”h]”hŒExample for perf tool use:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K%hhÇhžhubhŒliteral_block”“”)”}”(hXR  / # perf list | grep -e l3c -e iob -e mcb -e mc
  l3c0/ackq-full/                                    [Kernel PMU event]
<...>
  mcb1/mcb-csw-stall/                                [Kernel PMU event]

/ # perf stat -a -e l3c0/read-miss/,mcb1/csw-write-request/ sleep 1

/ # perf stat -a -e l3c0/read-miss,config1=0xfffffffffffffffe/ sleep 1”h]”hXR  / # perf list | grep -e l3c -e iob -e mcb -e mc
  l3c0/ackq-full/                                    [Kernel PMU event]
<...>
  mcb1/mcb-csw-stall/                                [Kernel PMU event]

/ # perf stat -a -e l3c0/read-miss/,mcb1/csw-write-request/ sleep 1

/ # perf stat -a -e l3c0/read-miss,config1=0xfffffffffffffffe/ sleep 1”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1j  hŸh¶h K'hhÇhžhubh¸)”}”(hŒ…The driver does not support sampling, therefore "perf record" will
not work. Per-task (without "-a") perf sessions are not supported.”h]”hŒThe driver does not support sampling, therefore â€œperf recordâ€ will
not work. Per-task (without â€œ-aâ€) perf sessions are not supported.”…””}”(hj0  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K0hhÇhžhubeh}”(h]”Œpmu-perf-driver”ah ]”h"]”Œpmu (perf) driver”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubeh}”(h]”Œ.apm-x-gene-soc-performance-monitoring-unit-pmu”ah ]”h"]”Œ0apm x-gene soc performance monitoring unit (pmu)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.