€•ŸŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ0/translations/zh_CN/admin-guide/perf/qcom_l2_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ0/translations/zh_TW/admin-guide/perf/qcom_l2_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ0/translations/it_IT/admin-guide/perf/qcom_l2_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ0/translations/ja_JP/admin-guide/perf/qcom_l2_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ0/translations/ko_KR/admin-guide/perf/qcom_l2_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ0/translations/sp_SP/admin-guide/perf/qcom_l2_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒEQualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)”h]”hŒEQualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒJ/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/qcom_l2_pmu.rst”h KubhŒ paragraph”“”)”}”(hŒÕThis driver supports the L2 cache clusters found in Qualcomm Technologies Centriq SoCs. There are multiple physical L2 cache clusters, each with their own PMU. Each cluster has one or more CPUs associated with it.”h]”hŒÕThis driver supports the L2 cache clusters found in Qualcomm Technologies Centriq SoCs. There are multiple physical L2 cache clusters, each with their own PMU. Each cluster has one or more CPUs associated with it.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒYThere is one logical L2 PMU exposed, which aggregates the results from the physical PMUs.”h]”hŒYThere is one logical L2 PMU exposed, which aggregates the results from the physical PMUs.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hh£hžhubh¸)”}”(hŒŠThe driver provides a description of its available events and configuration options in sysfs, see /sys/bus/event_source/devices/l2cache_0.”h]”hŒŠThe driver provides a description of its available events and configuration options in sysfs, see /sys/bus/event_source/devices/l2cache_0.”…””}”(hhÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hh£hžhubh¸)”}”(hŒ:The "format" directory describes the format of the events.”h]”hŒ>The “format†directory describes the format of the events.”…””}”(hhãhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hXEvents can be envisioned as a 2-dimensional array. Each column represents a group of events. There are 8 groups. Only one entry from each group can be in use at a time. If multiple events from the same group are specified, the conflicting events cannot be counted at the same time.”h]”hXEvents can be envisioned as a 2-dimensional array. Each column represents a group of events. There are 8 groups. Only one entry from each group can be in use at a time. If multiple events from the same group are specified, the conflicting events cannot be counted at the same time.”…””}”(hhñhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒEvents are specified as 0xCCG, where CC is 2 hex digits specifying the code (array row) and G specifies the group (column) 0-7.”h]”hŒEvents are specified as 0xCCG, where CC is 2 hex digits specifying the code (array row) and G specifies the group (column) 0-7.”…””}”(hhÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒiIn addition there is a cycle counter event specified by the value 0xFE which is outside the above scheme.”h]”hŒiIn addition there is a cycle counter event specified by the value 0xFE which is outside the above scheme.”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒ¨The driver provides a "cpumask" sysfs attribute which contains a mask consisting of one CPU per cluster which will be used to handle all the PMU events on that cluster.”h]”hŒ¬The driver provides a “cpumask†sysfs attribute which contains a mask consisting of one CPU per cluster which will be used to handle all the PMU events on that cluster.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒExamples for use with perf::”h]”hŒExamples for use with perf:”…””}”(hj)hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hh£hžhubhŒ literal_block”“”)”}”(hŒyperf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1”h]”hŒyperf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1”…””}”hj9sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1j7hŸh¶h K"hh£hžhubh¸)”}”(hŒvThe driver does not support sampling, therefore "perf record" will not work. Per-task perf sessions are not supported.”h]”hŒzThe driver does not support sampling, therefore “perf record†will not work. Per-task perf sessions are not supported.”…””}”(hjIhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K&hh£hžhubeh}”(h]”ŒCqualcomm-technologies-level-2-cache-performance-monitoring-unit-pmu”ah ]”h"]”ŒEqualcomm technologies level-2 cache performance monitoring unit (pmu)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j‚Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”j\jYsŒ nametypes”}”j\‰sh}”jYh£sŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.