€•nÚ      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ//translations/zh_CN/admin-guide/perf/nvidia-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/zh_TW/admin-guide/perf/nvidia-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/it_IT/admin-guide/perf/nvidia-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/ja_JP/admin-guide/perf/nvidia-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/ko_KR/admin-guide/perf/nvidia-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/sp_SP/admin-guide/perf/nvidia-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ9NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)”h]”hŒ9NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒI/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/nvidia-pmu.rst”h KubhŒ	paragraph”“”)”}”(hŒ…The NVIDIA Tegra SoC includes various system PMUs to measure key performance
metrics like memory bandwidth, latency, and utilization:”h]”hŒ…The NVIDIA Tegra SoC includes various system PMUs to measure key performance
metrics like memory bandwidth, latency, and utilization:”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒScalable Coherency Fabric (SCF)”h]”h¸)”}”(hhÐh]”hŒScalable Coherency Fabric (SCF)”…””}”(hhÒhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÎubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hŒNVLink-C2C0”h]”h¸)”}”(hhçh]”hŒNVLink-C2C0”…””}”(hhéhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K	hhåubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hŒNVLink-C2C1”h]”h¸)”}”(hhþh]”hŒNVLink-C2C1”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K
hhüubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hŒCNVLink”h]”h¸)”}”(hj  h]”hŒCNVLink”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hŒPCIE
”h]”h¸)”}”(hŒPCIE”h]”hŒPCIE”…””}”(hj.  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj*  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1hÇhŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒ
PMU Driver”h]”hŒ
PMU Driver”…””}”(hjM  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjJ  hžhhŸh¶h Kubh¸)”}”(hXR  The PMUs in this document are based on ARM CoreSight PMU Architecture as
described in document: ARM IHI 0091. Since this is a standard architecture, the
PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
the available events and configuration of each PMU in sysfs. Please see the
sections below to get the sysfs path of each PMU. Like other uncore PMU drivers,
the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
the PMU event. There is also "associated_cpus" sysfs attribute, which contains a
list of CPUs associated with the PMU instance.”h]”hX^  The PMUs in this document are based on ARM CoreSight PMU Architecture as
described in document: ARM IHI 0091. Since this is a standard architecture, the
PMUs are managed by a common driver â€œarm-cs-arch-pmuâ€. This driver describes
the available events and configuration of each PMU in sysfs. Please see the
sections below to get the sysfs path of each PMU. Like other uncore PMU drivers,
the driver provides â€œcpumaskâ€ sysfs attribute to show the CPU id used to handle
the PMU event. There is also â€œassociated_cpusâ€ sysfs attribute, which contains a
list of CPUs associated with the PMU instance.”…””}”(hj[  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjJ  hžhubhŒtarget”“”)”}”(hŒ.. _SCF_PMU_Section:”h]”h}”(h]”h ]”h"]”h$]”h&]”Œrefid”Œscf-pmu-section”uh1ji  h KhjJ  hžhhŸh¶ubeh}”(h]”Œ
pmu-driver”ah ]”h"]”Œ
pmu driver”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒSCF PMU”h]”hŒSCF PMU”…””}”(hj‚  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h Kubh¸)”}”(hŒìThe SCF PMU monitors system level cache events, CPU traffic, and
strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU
traffic coverage.”h]”(hŒThe SCF PMU monitors system level cache events, CPU traffic, and
strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
”…””}”(hj  hžhhŸNh Nubh)”}”(hŒ1:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`”h]”hŒinline”“”)”}”(hjš  h]”hŒ*NVIDIA_Uncore_PMU_Traffic_Coverage_Section”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”(Œxref”Œstd”Œstd-ref”eh"]”h$]”h&]”uh1jœ  hj˜  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”Œadmin-guide/perf/nvidia-pmu”Œ	refdomain”j©  Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆŒ	reftarget”Œ*nvidia_uncore_pmu_traffic_coverage_section”uh1hhŸh¶h Khj  ubhŒ. for more info about the PMU
traffic coverage.”…””}”(hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  hžhubh¸)”}”(hŒThe events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>.”h]”hŒThe events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>.”…””}”(hjÇ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K$hj  hžhubh¸)”}”(hŒExample usage:”h]”hŒExample usage:”…””}”(hjÕ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K'hj  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒOCount event id 0x0 in socket 0::

 perf stat -a -e nvidia_scf_pmu_0/event=0x0/
”h]”(h¸)”}”(hŒ Count event id 0x0 in socket 0::”h]”hŒCount event id 0x0 in socket 0:”…””}”(hjê  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K)hjæ  ubhŒliteral_block”“”)”}”(hŒ+perf stat -a -e nvidia_scf_pmu_0/event=0x0/”h]”hŒ+perf stat -a -e nvidia_scf_pmu_0/event=0x0/”…””}”hjú  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jø  hŸh¶h K+hjæ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjã  hžhhŸh¶h NubhÍ)”}”(hŒOCount event id 0x0 in socket 1::

 perf stat -a -e nvidia_scf_pmu_1/event=0x0/
”h]”(h¸)”}”(hŒ Count event id 0x0 in socket 1::”h]”hŒCount event id 0x0 in socket 1:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K-hj  ubjù  )”}”(hŒ+perf stat -a -e nvidia_scf_pmu_1/event=0x0/”h]”hŒ+perf stat -a -e nvidia_scf_pmu_1/event=0x0/”…””}”hj"  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K/hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjã  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h K)hj  hžhubeh}”(h]”(Œscf-pmu”jv  eh ]”h"]”(Œscf pmu”Œscf_pmu_section”eh$]”h&]”uh1h¡hh£hžhhŸh¶h KŒexpect_referenced_by_name”}”jB  jk  sŒexpect_referenced_by_id”}”jv  jk  subh¢)”}”(hhh]”(h§)”}”(hŒNVLink-C2C0 PMU”h]”hŒNVLink-C2C0 PMU”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjI  hžhhŸh¶h K2ubh¸)”}”(hŒÇThe NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
varies dependent on the chip configuration:”h]”hŒÇThe NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
varies dependent on the chip configuration:”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K4hjI  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒ™NVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC.

In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.
”h]”(h¸)”}”(hŒFNVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC.”h]”hŒFNVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC.”…””}”(hjo  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K8hjk  ubh¸)”}”(hŒPIn this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.”h]”hŒPIn this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.”…””}”(hj}  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K:hjk  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjh  hžhhŸh¶h NubhÍ)”}”(hŒ©NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.

In this config, the PMU captures read and relaxed ordered (RO) writes from
PCIE device of the remote SoC.
”h]”(h¸)”}”(hŒ=NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.”h]”hŒ=NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.”…””}”(hj•  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K<hj‘  ubh¸)”}”(hŒiIn this config, the PMU captures read and relaxed ordered (RO) writes from
PCIE device of the remote SoC.”h]”hŒiIn this config, the PMU captures read and relaxed ordered (RO) writes from
PCIE device of the remote SoC.”…””}”(hj£  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K>hj‘  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjh  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h K8hjI  hžhubh¸)”}”(hŒjPlease see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about
the PMU traffic coverage.”h]”(hŒPlease see ”…””}”(hj½  hžhhŸNh Nubh)”}”(hŒ1:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`”h]”j  )”}”(hjÇ  h]”hŒ*NVIDIA_Uncore_PMU_Traffic_Coverage_Section”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”(j¨  Œstd”Œstd-ref”eh"]”h$]”h&]”uh1jœ  hjÅ  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jµ  Œ	refdomain”jÓ  Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆj»  Œ*nvidia_uncore_pmu_traffic_coverage_section”uh1hhŸh¶h KAhj½  ubhŒ. for more info about
the PMU traffic coverage.”…””}”(hj½  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KAhjI  hžhubh¸)”}”(hŒ•The events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.”h]”hŒ•The events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.”…””}”(hjï  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KDhjI  hžhubh¸)”}”(hŒExample usage:”h]”hŒExample usage:”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KGhjI  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒtCount event id 0x0 from the GPU/CPU connected with socket 0::

 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/
”h]”(h¸)”}”(hŒ=Count event id 0x0 from the GPU/CPU connected with socket 0::”h]”hŒ<Count event id 0x0 from the GPU/CPU connected with socket 0:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KIhj  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KKhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h NubhÍ)”}”(hŒtCount event id 0x0 from the GPU/CPU connected with socket 1::

 perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/
”h]”(h¸)”}”(hŒ=Count event id 0x0 from the GPU/CPU connected with socket 1::”h]”hŒ<Count event id 0x0 from the GPU/CPU connected with socket 1:”…””}”(hj8  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KMhj4  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/”…””}”hjF  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KOhj4  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h NubhÍ)”}”(hŒtCount event id 0x0 from the GPU/CPU connected with socket 2::

 perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/
”h]”(h¸)”}”(hŒ=Count event id 0x0 from the GPU/CPU connected with socket 2::”h]”hŒ<Count event id 0x0 from the GPU/CPU connected with socket 2:”…””}”(hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KQhjZ  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/”…””}”hjl  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KShjZ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h NubhÍ)”}”(hŒtCount event id 0x0 from the GPU/CPU connected with socket 3::

 perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/
”h]”(h¸)”}”(hŒ=Count event id 0x0 from the GPU/CPU connected with socket 3::”h]”hŒ<Count event id 0x0 from the GPU/CPU connected with socket 3:”…””}”(hj„  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KUhj€  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/”…””}”hj’  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KWhj€  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h KIhjI  hžhubh¸)”}”(hXn  The NVLink-C2C has two ports that can be connected to one GPU (occupying both
ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
parameter to select the port(s) to monitor. Each bit represents the port number,
e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
PMU will monitor both ports by default if not specified.”h]”hXz  The NVLink-C2C has two ports that can be connected to one GPU (occupying both
ports) or to two GPUs (one GPU per port). The user can use â€œportâ€ bitmap
parameter to select the port(s) to monitor. Each bit represents the port number,
e.g. â€œport=0x1â€ corresponds to port 0 and â€œport=0x3â€ is for port 0 and 1. The
PMU will monitor both ports by default if not specified.”…””}”(hj¬  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KYhjI  hžhubh¸)”}”(hŒExample for port filtering:”h]”hŒExample for port filtering:”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K_hjI  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒƒCount event id 0x0 from the GPU connected with socket 0 on port 0::

 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/
”h]”(h¸)”}”(hŒCCount event id 0x0 from the GPU connected with socket 0 on port 0::”h]”hŒBCount event id 0x0 from the GPU connected with socket 0 on port 0:”…””}”(hjÏ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KahjË  ubjù  )”}”(hŒ<perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/”h]”hŒ<perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/”…””}”hjÝ  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KchjË  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÈ  hžhhŸh¶h NubhÍ)”}”(hŒCount event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::

 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/
”h]”(h¸)”}”(hŒOCount event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::”h]”hŒNCount event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1:”…””}”(hjõ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kehjñ  ubjù  )”}”(hŒ<perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/”h]”hŒ<perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h Kghjñ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÈ  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h KahjI  hžhubeh}”(h]”Œnvlink-c2c0-pmu”ah ]”h"]”Œnvlink-c2c0 pmu”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K2ubh¢)”}”(hhh]”(h§)”}”(hŒNVLink-C2C1 PMU”h]”hŒNVLink-C2C1 PMU”…””}”(hj(  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj%  hžhhŸh¶h Kjubh¸)”}”(hXL  The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU
traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about
the PMU traffic coverage.”h]”(hŒíThe NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU
traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
Please see ”…””}”(hj6  hžhhŸNh Nubh)”}”(hŒ1:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`”h]”j  )”}”(hj@  h]”hŒ*NVIDIA_Uncore_PMU_Traffic_Coverage_Section”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”(j¨  Œstd”Œstd-ref”eh"]”h$]”h&]”uh1jœ  hj>  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jµ  Œ	refdomain”jL  Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆj»  Œ*nvidia_uncore_pmu_traffic_coverage_section”uh1hhŸh¶h Klhj6  ubhŒ. for more info about
the PMU traffic coverage.”…””}”(hj6  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Klhj%  hžhubh¸)”}”(hŒ•The events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.”h]”hŒ•The events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Krhj%  hžhubh¸)”}”(hŒExample usage:”h]”hŒExample usage:”…””}”(hjv  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kuhj%  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒpCount event id 0x0 from the GPU connected with socket 0::

 perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/
”h]”(h¸)”}”(hŒ9Count event id 0x0 from the GPU connected with socket 0::”h]”hŒ8Count event id 0x0 from the GPU connected with socket 0:”…””}”(hj‹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kwhj‡  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/”…””}”hj™  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h Kyhj‡  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj„  hžhhŸh¶h NubhÍ)”}”(hŒpCount event id 0x0 from the GPU connected with socket 1::

 perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/
”h]”(h¸)”}”(hŒ9Count event id 0x0 from the GPU connected with socket 1::”h]”hŒ8Count event id 0x0 from the GPU connected with socket 1:”…””}”(hj±  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K{hj­  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/”…””}”hj¿  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K}hj­  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj„  hžhhŸh¶h NubhÍ)”}”(hŒpCount event id 0x0 from the GPU connected with socket 2::

 perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/
”h]”(h¸)”}”(hŒ9Count event id 0x0 from the GPU connected with socket 2::”h]”hŒ8Count event id 0x0 from the GPU connected with socket 2:”…””}”(hj×  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjÓ  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/”…””}”hjå  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KhjÓ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj„  hžhhŸh¶h NubhÍ)”}”(hŒpCount event id 0x0 from the GPU connected with socket 3::

 perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/
”h]”(h¸)”}”(hŒ9Count event id 0x0 from the GPU connected with socket 3::”h]”hŒ8Count event id 0x0 from the GPU connected with socket 3:”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kƒhjù  ubjù  )”}”(hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/”h]”hŒ3perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K…hjù  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj„  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h Kwhj%  hžhubh¸)”}”(hXn  The NVLink-C2C has two ports that can be connected to one GPU (occupying both
ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
parameter to select the port(s) to monitor. Each bit represents the port number,
e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
PMU will monitor both ports by default if not specified.”h]”hXz  The NVLink-C2C has two ports that can be connected to one GPU (occupying both
ports) or to two GPUs (one GPU per port). The user can use â€œportâ€ bitmap
parameter to select the port(s) to monitor. Each bit represents the port number,
e.g. â€œport=0x1â€ corresponds to port 0 and â€œport=0x3â€ is for port 0 and 1. The
PMU will monitor both ports by default if not specified.”…””}”(hj%  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K‡hj%  hžhubh¸)”}”(hŒExample for port filtering:”h]”hŒExample for port filtering:”…””}”(hj3  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj%  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒƒCount event id 0x0 from the GPU connected with socket 0 on port 0::

 perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/
”h]”(h¸)”}”(hŒCCount event id 0x0 from the GPU connected with socket 0 on port 0::”h]”hŒBCount event id 0x0 from the GPU connected with socket 0 on port 0:”…””}”(hjH  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjD  ubjù  )”}”(hŒ<perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/”h]”hŒ<perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/”…””}”hjV  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K‘hjD  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjA  hžhhŸh¶h NubhÍ)”}”(hŒCount event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::

 perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/
”h]”(h¸)”}”(hŒOCount event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::”h]”hŒNCount event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1:”…””}”(hjn  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K“hjj  ubjù  )”}”(hŒ<perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/”h]”hŒ<perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/”…””}”hj|  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K•hjj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjA  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h Khj%  hžhubeh}”(h]”Œnvlink-c2c1-pmu”ah ]”h"]”Œnvlink-c2c1 pmu”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kjubh¢)”}”(hhh]”(h§)”}”(hŒCNVLink PMU”h]”hŒCNVLink PMU”…””}”(hj¡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjž  hžhhŸh¶h K˜ubh¸)”}”(hX  The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
(RO) write traffic. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
for more info about the PMU traffic coverage.”h]”(hŒ¹The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
(RO) write traffic. Please see ”…””}”(hj¯  hžhhŸNh Nubh)”}”(hŒ1:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`”h]”j  )”}”(hj¹  h]”hŒ*NVIDIA_Uncore_PMU_Traffic_Coverage_Section”…””}”(hj»  hžhhŸNh Nubah}”(h]”h ]”(j¨  Œstd”Œstd-ref”eh"]”h$]”h&]”uh1jœ  hj·  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jµ  Œ	refdomain”jÅ  Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆj»  Œ*nvidia_uncore_pmu_traffic_coverage_section”uh1hhŸh¶h Kšhj¯  ubhŒ.
for more info about the PMU traffic coverage.”…””}”(hj¯  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kšhjž  hžhubh¸)”}”(hŒ‘The events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>.”h]”hŒ‘The events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>.”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KŸhjž  hžhubh¸)”}”(hXÑ  Each SoC socket can be connected to one or more sockets via CNVLink. The user can
use "rem_socket" bitmap parameter to select the remote socket(s) to monitor.
Each bit represents the socket number, e.g. "rem_socket=0xE" corresponds to
socket 1 to 3. The PMU will monitor all remote sockets by default if not
specified.
/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
shows the valid bits that can be set in the "rem_socket" parameter.”h]”hXÝ  Each SoC socket can be connected to one or more sockets via CNVLink. The user can
use â€œrem_socketâ€ bitmap parameter to select the remote socket(s) to monitor.
Each bit represents the socket number, e.g. â€œrem_socket=0xEâ€ corresponds to
socket 1 to 3. The PMU will monitor all remote sockets by default if not
specified.
/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
shows the valid bits that can be set in the â€œrem_socketâ€ parameter.”…””}”(hjï  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¢hjž  hžhubh¸)”}”(hŒÅThe PMU can not distinguish the remote traffic initiator, therefore it does not
provide filter to select the traffic source to monitor. It reports combined
traffic from remote GPU and PCIE devices.”h]”hŒÅThe PMU can not distinguish the remote traffic initiator, therefore it does not
provide filter to select the traffic source to monitor. It reports combined
traffic from remote GPU and PCIE devices.”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kªhjž  hžhubh¸)”}”(hŒExample usage:”h]”hŒExample usage:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K®hjž  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒ‘Count event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0::

 perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/
”h]”(h¸)”}”(hŒOCount event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0::”h]”hŒNCount event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0:”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K°hj  ubjù  )”}”(hŒ>perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/”h]”hŒ>perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/”…””}”hj.  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K²hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h NubhÍ)”}”(hŒ‘Count event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1::

 perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/
”h]”(h¸)”}”(hŒOCount event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1::”h]”hŒNCount event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1:”…””}”(hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K´hjB  ubjù  )”}”(hŒ>perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/”h]”hŒ>perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/”…””}”hjT  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K¶hjB  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h NubhÍ)”}”(hŒ‘Count event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2::

 perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/
”h]”(h¸)”}”(hŒOCount event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2::”h]”hŒNCount event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2:”…””}”(hjl  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¸hjh  ubjù  )”}”(hŒ>perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/”h]”hŒ>perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/”…””}”hjz  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h Kºhjh  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h NubhÍ)”}”(hŒ’Count event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3::

 perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/

”h]”(h¸)”}”(hŒOCount event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3::”h]”hŒNCount event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3:”…””}”(hj’  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¼hjŽ  ubjù  )”}”(hŒ>perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/”h]”hŒ>perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h K¾hjŽ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h K°hjž  hžhubeh}”(h]”Œcnvlink-pmu”ah ]”h"]”Œcnvlink pmu”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K˜ubh¢)”}”(hhh]”(h§)”}”(hŒPCIE PMU”h]”hŒPCIE PMU”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÂ  hžhhŸh¶h KÂubh¸)”}”(hŒÄThe PCIE PMU monitors all read/write traffic from PCIE root ports to
local/remote memory. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
for more info about the PMU traffic coverage.”h]”(hŒeThe PCIE PMU monitors all read/write traffic from PCIE root ports to
local/remote memory. Please see ”…””}”(hjÓ  hžhhŸNh Nubh)”}”(hŒ1:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`”h]”j  )”}”(hjÝ  h]”hŒ*NVIDIA_Uncore_PMU_Traffic_Coverage_Section”…””}”(hjß  hžhhŸNh Nubah}”(h]”h ]”(j¨  Œstd”Œstd-ref”eh"]”h$]”h&]”uh1jœ  hjÛ  ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jµ  Œ	refdomain”jé  Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆj»  Œ*nvidia_uncore_pmu_traffic_coverage_section”uh1hhŸh¶h KÄhjÓ  ubhŒ.
for more info about the PMU traffic coverage.”…””}”(hjÓ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÄhjÂ  hžhubh¸)”}”(hŒŽThe events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>.”h]”hŒŽThe events and configuration options of this PMU device are described in sysfs,
see /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÈhjÂ  hžhubh¸)”}”(hX…  Each SoC socket can support multiple root ports. The user can use
"root_port" bitmap parameter to select the port(s) to monitor, i.e.
"root_port=0xF" corresponds to root port 0 to 3. The PMU will monitor all root
ports by default if not specified.
/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
shows the valid bits that can be set in the "root_port" parameter.”h]”hX‘  Each SoC socket can support multiple root ports. The user can use
â€œroot_portâ€ bitmap parameter to select the port(s) to monitor, i.e.
â€œroot_port=0xFâ€ corresponds to root port 0 to 3. The PMU will monitor all root
ports by default if not specified.
/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
shows the valid bits that can be set in the â€œroot_portâ€ parameter.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KËhjÂ  hžhubh¸)”}”(hŒExample usage:”h]”hŒExample usage:”…””}”(hj!  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÒhjÂ  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒuCount event id 0x0 from root port 0 and 1 of socket 0::

 perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/
”h]”(h¸)”}”(hŒ7Count event id 0x0 from root port 0 and 1 of socket 0::”h]”hŒ6Count event id 0x0 from root port 0 and 1 of socket 0:”…””}”(hj6  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÔhj2  ubjù  )”}”(hŒ:perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/”h]”hŒ:perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/”…””}”hjD  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KÖhj2  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj/  hžhhŸh¶h NubhÍ)”}”(hŒuCount event id 0x0 from root port 0 and 1 of socket 1::

 perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/
”h]”(h¸)”}”(hŒ7Count event id 0x0 from root port 0 and 1 of socket 1::”h]”hŒ6Count event id 0x0 from root port 0 and 1 of socket 1:”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KØhjX  ubjù  )”}”(hŒ:perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/”h]”hŒ:perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/”…””}”hjj  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h KÚhjX  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj/  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h KÔhjÂ  hžhubjj  )”}”(hŒ/.. _NVIDIA_Uncore_PMU_Traffic_Coverage_Section:”h]”h}”(h]”h ]”h"]”h$]”h&]”ju  Œ*nvidia-uncore-pmu-traffic-coverage-section”uh1ji  h KÜhjÂ  hžhhŸh¶ubeh}”(h]”Œpcie-pmu”ah ]”h"]”Œpcie pmu”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KÂubh¢)”}”(hhh]”(h§)”}”(hŒTraffic Coverage”h]”hŒTraffic Coverage”…””}”(hjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj—  hžhhŸh¶h Kßubh¸)”}”(hŒFThe PMU traffic coverage may vary dependent on the chip configuration:”h]”hŒFThe PMU traffic coverage may vary dependent on the chip configuration:”…””}”(hj¨  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Káhj—  hžhubhÈ)”}”(hhh]”(hÍ)”}”(hX¶  **NVIDIA Grace Hopper Superchip**: Hopper GPU is connected with Grace SoC.

Example configuration with two Grace SoCs::

 *********************************          *********************************
 * SOCKET-A                      *          * SOCKET-B                      *
 *                               *          *                               *
 *                     ::::::::  *          *  ::::::::                     *
 *                     : PCIE :  *          *  : PCIE :                     *
 *                     ::::::::  *          *  ::::::::                     *
 *                         |     *          *      |                        *
 *                         |     *          *      |                        *
 *  :::::::            ::::::::: *          *  :::::::::            ::::::: *
 *  :     :            :       : *          *  :       :            :     : *
 *  : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
 *  :     :    C2C     :  SoC  : *          *  :  SoC  :    C2C     :     : *
 *  :::::::            ::::::::: *          *  :::::::::            ::::::: *
 *     |                   |     *          *      |                   |    *
 *     |                   |     *          *      |                   |    *
 *  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
 *  & GMEM &           & CMEM &  *          *   & CMEM &           & GMEM & *
 *  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
 *                               *          *                               *
 *********************************          *********************************

 GMEM = GPU Memory (e.g. HBM)
 CMEM = CPU Memory (e.g. LPDDR5X)

|
| Following table contains traffic coverage of Grace SoC PMU in socket-A:

::

 +--------------+-------+-----------+-----------+-----+----------+----------+
 |              |                        Source                             |
 +              +-------+-----------+-----------+-----+----------+----------+
 | Destination  |       |GPU ATS    |GPU Not-ATS|     | Socket-B | Socket-B |
 |              |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
 |              |       |EGM        |           |     |          |          |
 +==============+=======+===========+===========+=====+==========+==========+
 | Local        | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
 | SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |          | PMU      |
 +--------------+-------+-----------+-----------+-----+----------+----------+
 | Local GMEM   | PCIE  |    N/A    |NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
 |              | PMU   |           |PMU        | PMU |          | PMU      |
 +--------------+-------+-----------+-----------+-----+----------+----------+
 | Remote       | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
 | SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
 | over CNVLink |       |           |           |     |          |          |
 +--------------+-------+-----------+-----------+-----+----------+----------+
 | Remote GMEM  | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
 | over CNVLink | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
 +--------------+-------+-----------+-----------+-----+----------+----------+

 PCIE1 traffic represents strongly ordered (SO) writes.
 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
”h]”(h¸)”}”(hŒJ**NVIDIA Grace Hopper Superchip**: Hopper GPU is connected with Grace SoC.”h]”(hŒstrong”“”)”}”(hŒ!**NVIDIA Grace Hopper Superchip**”h]”hŒNVIDIA Grace Hopper Superchip”…””}”(hjÃ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  hj½  ubhŒ): Hopper GPU is connected with Grace SoC.”…””}”(hj½  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kãhj¹  ubh¸)”}”(hŒ+Example configuration with two Grace SoCs::”h]”hŒ*Example configuration with two Grace SoCs:”…””}”(hjÛ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kåhj¹  ubjù  )”}”(hXB  *********************************          *********************************
* SOCKET-A                      *          * SOCKET-B                      *
*                               *          *                               *
*                     ::::::::  *          *  ::::::::                     *
*                     : PCIE :  *          *  : PCIE :                     *
*                     ::::::::  *          *  ::::::::                     *
*                         |     *          *      |                        *
*                         |     *          *      |                        *
*  :::::::            ::::::::: *          *  :::::::::            ::::::: *
*  :     :            :       : *          *  :       :            :     : *
*  : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
*  :     :    C2C     :  SoC  : *          *  :  SoC  :    C2C     :     : *
*  :::::::            ::::::::: *          *  :::::::::            ::::::: *
*     |                   |     *          *      |                   |    *
*     |                   |     *          *      |                   |    *
*  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
*  & GMEM &           & CMEM &  *          *   & CMEM &           & GMEM & *
*  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
*                               *          *                               *
*********************************          *********************************

GMEM = GPU Memory (e.g. HBM)
CMEM = CPU Memory (e.g. LPDDR5X)”h]”hXB  *********************************          *********************************
* SOCKET-A                      *          * SOCKET-B                      *
*                               *          *                               *
*                     ::::::::  *          *  ::::::::                     *
*                     : PCIE :  *          *  : PCIE :                     *
*                     ::::::::  *          *  ::::::::                     *
*                         |     *          *      |                        *
*                         |     *          *      |                        *
*  :::::::            ::::::::: *          *  :::::::::            ::::::: *
*  :     :            :       : *          *  :       :            :     : *
*  : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
*  :     :    C2C     :  SoC  : *          *  :  SoC  :    C2C     :     : *
*  :::::::            ::::::::: *          *  :::::::::            ::::::: *
*     |                   |     *          *      |                   |    *
*     |                   |     *          *      |                   |    *
*  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
*  & GMEM &           & CMEM &  *          *   & CMEM &           & GMEM & *
*  &&&&&&&&           &&&&&&&&  *          *   &&&&&&&&           &&&&&&&& *
*                               *          *                               *
*********************************          *********************************

GMEM = GPU Memory (e.g. HBM)
CMEM = CPU Memory (e.g. LPDDR5X)”…””}”hjé  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h Kçhj¹  ubhŒ
line_block”“”)”}”(hhh]”(hh “”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1h hjù  Œindent”K hŸh¶h K ubjü  )”}”(hŒGFollowing table contains traffic coverage of Grace SoC PMU in socket-A:”h]”hŒGFollowing table contains traffic coverage of Grace SoC PMU in socket-A:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h j  K hjù  hŸh¶h K ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j÷  hj¹  ubjù  )”}”(hX{  +--------------+-------+-----------+-----------+-----+----------+----------+
|              |                        Source                             |
+              +-------+-----------+-----------+-----+----------+----------+
| Destination  |       |GPU ATS    |GPU Not-ATS|     | Socket-B | Socket-B |
|              |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
|              |       |EGM        |           |     |          |          |
+==============+=======+===========+===========+=====+==========+==========+
| Local        | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
| SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |          | PMU      |
+--------------+-------+-----------+-----------+-----+----------+----------+
| Local GMEM   | PCIE  |    N/A    |NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
|              | PMU   |           |PMU        | PMU |          | PMU      |
+--------------+-------+-----------+-----------+-----+----------+----------+
| Remote       | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
| SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
| over CNVLink |       |           |           |     |          |          |
+--------------+-------+-----------+-----------+-----+----------+----------+
| Remote GMEM  | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
| over CNVLink | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
+--------------+-------+-----------+-----------+-----+----------+----------+

PCIE1 traffic represents strongly ordered (SO) writes.
PCIE2 traffic represents reads and relaxed ordered (RO) writes.”h]”hX{  +--------------+-------+-----------+-----------+-----+----------+----------+
|              |                        Source                             |
+              +-------+-----------+-----------+-----+----------+----------+
| Destination  |       |GPU ATS    |GPU Not-ATS|     | Socket-B | Socket-B |
|              |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
|              |       |EGM        |           |     |          |          |
+==============+=======+===========+===========+=====+==========+==========+
| Local        | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
| SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |          | PMU      |
+--------------+-------+-----------+-----------+-----+----------+----------+
| Local GMEM   | PCIE  |    N/A    |NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
|              | PMU   |           |PMU        | PMU |          | PMU      |
+--------------+-------+-----------+-----------+-----+----------+----------+
| Remote       | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
| SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
| over CNVLink |       |           |           |     |          |          |
+--------------+-------+-----------+-----------+-----+----------+----------+
| Remote GMEM  | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF |          |          |
| over CNVLink | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
+--------------+-------+-----------+-----------+-----+----------+----------+

PCIE1 traffic represents strongly ordered (SO) writes.
PCIE2 traffic represents reads and relaxed ordered (RO) writes.”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h Mhj¹  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj¶  hžhhŸh¶h NubhÍ)”}”(hXX	  **NVIDIA Grace CPU Superchip**: two Grace CPU SoCs are connected.

Example configuration with two Grace SoCs::

 *******************             *******************
 * SOCKET-A        *             * SOCKET-B        *
 *                 *             *                 *
 *    ::::::::     *             *    ::::::::     *
 *    : PCIE :     *             *    : PCIE :     *
 *    ::::::::     *             *    ::::::::     *
 *        |        *             *        |        *
 *        |        *             *        |        *
 *    :::::::::    *             *    :::::::::    *
 *    :       :    *             *    :       :    *
 *    : Grace :<--------NVLink------->: Grace :    *
 *    :  SoC  :    *     C2C     *    :  SoC  :    *
 *    :::::::::    *             *    :::::::::    *
 *        |        *             *        |        *
 *        |        *             *        |        *
 *     &&&&&&&&    *             *     &&&&&&&&    *
 *     & CMEM &    *             *     & CMEM &    *
 *     &&&&&&&&    *             *     &&&&&&&&    *
 *                 *             *                 *
 *******************             *******************

 GMEM = GPU Memory (e.g. HBM)
 CMEM = CPU Memory (e.g. LPDDR5X)

|
| Following table contains traffic coverage of Grace SoC PMU in socket-A:

::

 +-----------------+-----------+---------+----------+-------------+
 |                 |                      Source                  |
 +                 +-----------+---------+----------+-------------+
 | Destination     |           |         | Socket-B | Socket-B    |
 |                 |  PCI R/W  |   CPU   | CPU/PCIE1| PCIE2       |
 |                 |           |         |          |             |
 +=================+===========+=========+==========+=============+
 | Local           |  PCIE PMU | SCF PMU | SCF PMU  | NVLink-C2C0 |
 | SYSRAM/CMEM     |           |         |          | PMU         |
 +-----------------+-----------+---------+----------+-------------+
 | Remote          |           |         |          |             |
 | SYSRAM/CMEM     |  PCIE PMU | SCF PMU |   N/A    |     N/A     |
 | over NVLink-C2C |           |         |          |             |
 +-----------------+-----------+---------+----------+-------------+

 PCIE1 traffic represents strongly ordered (SO) writes.
 PCIE2 traffic represents reads and relaxed ordered (RO) writes.”h]”(h¸)”}”(hŒA**NVIDIA Grace CPU Superchip**: two Grace CPU SoCs are connected.”h]”(jÂ  )”}”(hŒ**NVIDIA Grace CPU Superchip**”h]”hŒNVIDIA Grace CPU Superchip”…””}”(hj7  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÁ  hj3  ubhŒ#: two Grace CPU SoCs are connected.”…””}”(hj3  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj/  ubh¸)”}”(hŒ+Example configuration with two Grace SoCs::”h]”hŒ*Example configuration with two Grace SoCs:”…””}”(hjO  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj/  ubjù  )”}”(hXN  *******************             *******************
* SOCKET-A        *             * SOCKET-B        *
*                 *             *                 *
*    ::::::::     *             *    ::::::::     *
*    : PCIE :     *             *    : PCIE :     *
*    ::::::::     *             *    ::::::::     *
*        |        *             *        |        *
*        |        *             *        |        *
*    :::::::::    *             *    :::::::::    *
*    :       :    *             *    :       :    *
*    : Grace :<--------NVLink------->: Grace :    *
*    :  SoC  :    *     C2C     *    :  SoC  :    *
*    :::::::::    *             *    :::::::::    *
*        |        *             *        |        *
*        |        *             *        |        *
*     &&&&&&&&    *             *     &&&&&&&&    *
*     & CMEM &    *             *     & CMEM &    *
*     &&&&&&&&    *             *     &&&&&&&&    *
*                 *             *                 *
*******************             *******************

GMEM = GPU Memory (e.g. HBM)
CMEM = CPU Memory (e.g. LPDDR5X)”h]”hXN  *******************             *******************
* SOCKET-A        *             * SOCKET-B        *
*                 *             *                 *
*    ::::::::     *             *    ::::::::     *
*    : PCIE :     *             *    : PCIE :     *
*    ::::::::     *             *    ::::::::     *
*        |        *             *        |        *
*        |        *             *        |        *
*    :::::::::    *             *    :::::::::    *
*    :       :    *             *    :       :    *
*    : Grace :<--------NVLink------->: Grace :    *
*    :  SoC  :    *     C2C     *    :  SoC  :    *
*    :::::::::    *             *    :::::::::    *
*        |        *             *        |        *
*        |        *             *        |        *
*     &&&&&&&&    *             *     &&&&&&&&    *
*     & CMEM &    *             *     & CMEM &    *
*     &&&&&&&&    *             *     &&&&&&&&    *
*                 *             *                 *
*******************             *******************

GMEM = GPU Memory (e.g. HBM)
CMEM = CPU Memory (e.g. LPDDR5X)”…””}”hj]  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h M hj/  ubjø  )”}”(hhh]”(jü  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1h hjk  j  K hŸh¶h K ubjü  )”}”(hŒGFollowing table contains traffic coverage of Grace SoC PMU in socket-A:”h]”hŒGFollowing table contains traffic coverage of Grace SoC PMU in socket-A:”…””}”(hjw  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h j  K hjk  hŸh¶h K ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j÷  hj/  ubjù  )”}”(hX!  +-----------------+-----------+---------+----------+-------------+
|                 |                      Source                  |
+                 +-----------+---------+----------+-------------+
| Destination     |           |         | Socket-B | Socket-B    |
|                 |  PCI R/W  |   CPU   | CPU/PCIE1| PCIE2       |
|                 |           |         |          |             |
+=================+===========+=========+==========+=============+
| Local           |  PCIE PMU | SCF PMU | SCF PMU  | NVLink-C2C0 |
| SYSRAM/CMEM     |           |         |          | PMU         |
+-----------------+-----------+---------+----------+-------------+
| Remote          |           |         |          |             |
| SYSRAM/CMEM     |  PCIE PMU | SCF PMU |   N/A    |     N/A     |
| over NVLink-C2C |           |         |          |             |
+-----------------+-----------+---------+----------+-------------+

PCIE1 traffic represents strongly ordered (SO) writes.
PCIE2 traffic represents reads and relaxed ordered (RO) writes.”h]”hX!  +-----------------+-----------+---------+----------+-------------+
|                 |                      Source                  |
+                 +-----------+---------+----------+-------------+
| Destination     |           |         | Socket-B | Socket-B    |
|                 |  PCI R/W  |   CPU   | CPU/PCIE1| PCIE2       |
|                 |           |         |          |             |
+=================+===========+=========+==========+=============+
| Local           |  PCIE PMU | SCF PMU | SCF PMU  | NVLink-C2C0 |
| SYSRAM/CMEM     |           |         |          | PMU         |
+-----------------+-----------+---------+----------+-------------+
| Remote          |           |         |          |             |
| SYSRAM/CMEM     |  PCIE PMU | SCF PMU |   N/A    |     N/A     |
| over NVLink-C2C |           |         |          |             |
+-----------------+-----------+---------+----------+-------------+

PCIE1 traffic represents strongly ordered (SO) writes.
PCIE2 traffic represents reads and relaxed ordered (RO) writes.”…””}”hj‹  sbah}”(h]”h ]”h"]”h$]”h&]”j  j	  uh1jø  hŸh¶h M=hj/  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj¶  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jH  jI  uh1hÇhŸh¶h Kãhj—  hžhubeh}”(h]”(Œtraffic-coverage”jŽ  eh ]”h"]”(Œtraffic coverage”Œ*nvidia_uncore_pmu_traffic_coverage_section”eh$]”h&]”uh1h¡hh£hžhhŸh¶h KßjE  }”j«  j„  sjG  }”jŽ  j„  subeh}”(h]”Œ7nvidia-tegra-soc-uncore-performance-monitoring-unit-pmu”ah ]”h"]”Œ9nvidia tegra soc uncore performance monitoring unit (pmu)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jÛ  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”(jv  ]”jk  ajŽ  ]”j„  auŒnameids”}”(jµ  j²  j|  jy  jB  jv  jA  j>  j"  j  j›  j˜  j¿  j¼  j”  j‘  j«  jŽ  jª  j§  uŒ	nametypes”}”(jµ  ‰j|  ‰jB  ˆjA  ‰j"  ‰j›  ‰j¿  ‰j”  ‰j«  ˆjª  ‰uh}”(j²  h£jy  jJ  jv  j  j>  j  j  jI  j˜  j%  j¼  jž  j‘  jÂ  jŽ  j—  j§  j—  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”(hŒsystem_message”“”)”}”(hhh]”h¸)”}”(hhh]”hŒ5Hyperlink target "scf-pmu-section" is not referenced.”…””}”hjF	  sbah}”(h]”h ]”h"]”h$]”h&]”uh1h·hjC	  ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”ŒINFO”Œsource”h¶Œline”Kuh1jA	  ubjB	  )”}”(hhh]”h¸)”}”(hhh]”hŒPHyperlink target "nvidia-uncore-pmu-traffic-coverage-section" is not referenced.”…””}”hja	  sbah}”(h]”h ]”h"]”h$]”h&]”uh1h·hj^	  ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”j[	  Œsource”h¶Œline”KÜuh1jA	  ubeŒtransformer”NŒinclude_log”]”Œ
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