€•\3      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ9/translations/zh_CN/admin-guide/perf/mrvl-odyssey-ddr-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ9/translations/zh_TW/admin-guide/perf/mrvl-odyssey-ddr-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ9/translations/it_IT/admin-guide/perf/mrvl-odyssey-ddr-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ9/translations/ja_JP/admin-guide/perf/mrvl-odyssey-ddr-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ9/translations/ko_KR/admin-guide/perf/mrvl-odyssey-ddr-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ9/translations/sp_SP/admin-guide/perf/mrvl-odyssey-ddr-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ@Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)”h]”hŒ@Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒS/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst”h KubhŒ	paragraph”“”)”}”(hXl  Odyssey DRAM Subsystem supports eight counters for monitoring performance
and software can program those counters to monitor any of the defined
performance events. Supported performance events include those counted
at the interface between the DDR controller and the PHY, interface between
the DDR Controller and the CHI interconnect, or within the DDR Controller.”h]”hXl  Odyssey DRAM Subsystem supports eight counters for monitoring performance
and software can program those counters to monitor any of the defined
performance events. Supported performance events include those counted
at the interface between the DDR controller and the PHY, interface between
the DDR Controller and the CHI interconnect, or within the DDR Controller.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒtAdditionally DSS also supports two fixed performance event counters, one
for ddr reads and the other for ddr writes.”h]”hŒtAdditionally DSS also supports two fixed performance event counters, one
for ddr reads and the other for ddr writes.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒ<The counter will be operating in either manual or auto mode.”h]”hŒ<The counter will be operating in either manual or auto mode.”…””}”(hhÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒLThe PMU driver exposes the available events and format options under sysfs::”h]”hŒKThe PMU driver exposes the available events and format options under sysfs:”…””}”(hhãhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒliteral_block”“”)”}”(hŒk/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/
/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/”h]”hŒk/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/
/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/”…””}”hhósbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hñhŸh¶h Khh£hžhubh¸)”}”(hŒ
Examples::”h]”hŒ	Examples:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhò)”}”(hXX  $ perf list | grep ddr
mrvl_ddr_pmu_<>/ddr_act_bypass_access/   [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_bsm_alloc/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_bsm_starvation/      [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_active_access/   [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_mwr/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_read/            [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_wr_access/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_write/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_capar_error/         [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_crit_ref/            [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_ddr_reads/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_ddr_writes/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_cycles/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/   [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/  [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/  [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_mpsm/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_powerdown/     [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_selfref/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rd_access/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rmw_access/      [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_wr_access/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_load_mode/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/  [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_raw_hazard/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_bypass_access/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_crc_error/        [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/     [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rdwr_transitions/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_refresh/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_retry_fifo_full/     [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_spec_ref/            [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_tcr_mrr/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_war_hazard/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_waw_hazard/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_wr_crc_error/        [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_write_combine/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqcl/                [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqlatch/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqstart/             [Kernel PMU event]

$ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,ddr_cam
  rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr <workload>”h]”hXX  $ perf list | grep ddr
mrvl_ddr_pmu_<>/ddr_act_bypass_access/   [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_bsm_alloc/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_bsm_starvation/      [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_active_access/   [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_mwr/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_read/            [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_wr_access/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_write/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_capar_error/         [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_crit_ref/            [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_ddr_reads/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_ddr_writes/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_cycles/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/   [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/  [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/  [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_mpsm/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_powerdown/     [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_selfref/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rd_access/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rmw_access/      [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_wr_access/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_load_mode/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge/           [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/  [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_raw_hazard/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_bypass_access/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_crc_error/        [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/     [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rdwr_transitions/    [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_refresh/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_retry_fifo_full/     [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_spec_ref/            [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_tcr_mrr/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_war_hazard/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_waw_hazard/          [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_wr_crc_error/        [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_write_combine/       [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqcl/                [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqlatch/             [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqstart/             [Kernel PMU event]

$ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,ddr_cam
  rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr <workload>”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j  j  uh1hñhŸh¶h Khh£hžhubeh}”(h]”Œ>marvell-odyssey-ddr-pmu-performance-monitoring-unit-pmu-uncore”ah ]”h"]”Œ@marvell odyssey ddr pmu performance monitoring unit (pmu uncore)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jJ  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”j$  j!  sŒ	nametypes”}”j$  ‰sh}”j!  h£sŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.