€•‘MŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ,/translations/zh_CN/admin-guide/perf/imx-ddr”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/zh_TW/admin-guide/perf/imx-ddr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/it_IT/admin-guide/perf/imx-ddr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/ja_JP/admin-guide/perf/imx-ddr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/ko_KR/admin-guide/perf/imx-ddr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/sp_SP/admin-guide/perf/imx-ddr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ5Freescale i.MX8 DDR Performance Monitoring Unit (PMU)”h]”hŒ5Freescale i.MX8 DDR Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒF/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/imx-ddr.rst”h KubhŒ paragraph”“”)”}”(hX=There are no performance counters inside the DRAM controller, so performance signals are brought out to the edge of the controller where a set of 4 x 32 bit counters is implemented. This is controlled by the CSV modes programmed in counter control register which causes a large number of PERF signals to be generated.”h]”hX=There are no performance counters inside the DRAM controller, so performance signals are brought out to the edge of the controller where a set of 4 x 32 bit counters is implemented. This is controlled by the CSV modes programmed in counter control register which causes a large number of PERF signals to be generated.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hXYSelection of the value for each counter is done via the config registers. There is one register for each counter. Counter 0 is special in that it always counts “time†and when expired causes a lock on itself and the other counters and an interrupt is raised. If any other counter overflows, it continues counting, and no interrupt is raised.”h]”hXYSelection of the value for each counter is done via the config registers. There is one register for each counter. Counter 0 is special in that it always counts “time†and when expired causes a lock on itself and the other counters and an interrupt is raised. If any other counter overflows, it continues counting, and no interrupt is raised.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hh£hžhubh¸)”}”(hXÙThe "format" directory describes format of the config (event ID) and config1/2 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/ devices/imx8_ddr0/format/. The "events" directory describes the events types hardware supported that can be used with perf tool, see /sys/bus/event_source/ devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.”h]”hXåThe “format†directory describes format of the config (event ID) and config1/2 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/ devices/imx8_ddr0/format/. The “events†directory describes the events types hardware supported that can be used with perf tool, see /sys/bus/event_source/ devices/imx8_ddr0/events/. The “caps†directory describes filter features implemented in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.”…””}”(hhÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒ block_quote”“”)”}”(hŒy.. code-block:: bash perf stat -a -e imx8_ddr0/cycles/ cmd perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd ”h]”hŒ literal_block”“”)”}”(hŒZperf stat -a -e imx8_ddr0/cycles/ cmd perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd”h]”hŒZperf stat -a -e imx8_ddr0/cycles/ cmd perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd”…””}”hhësbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”Œforce”‰Œlanguage”Œbash”Œhighlight_args”}”uh1héhŸh¶h Khhåubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhŸh¶h Khh£hžhubh¸)”}”(hX±AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) to count reading or writing matches filter setting. Filter setting is various from different DRAM controller implementations, which is distinguished by quirks in the driver. You also can dump info from userspace, "caps" directory show the type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for un-supported, and value 1 for supported.”h]”hXµAXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) to count reading or writing matches filter setting. Filter setting is various from different DRAM controller implementations, which is distinguished by quirks in the driver. You also can dump info from userspace, “caps†directory show the type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for un-supported, and value 1 for supported.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hXWith DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). Filter is defined with two configuration parts: --AXI_ID defines AxID matching value. --AXI_MASKING defines which bits of AxID are meaningful for the matching. - 0: corresponding bit is masked. - 1: corresponding bit is not masked, i.e. used to do the matching. AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. When non-masked bits are matching corresponding AXI_ID bits then counter is incremented. Perf counter is incremented if:: AxID && AXI_MASKING == AXI_ID && AXI_MASKING This filter doesn't support filter different AXI ID for axid-read and axid-write event at the same time as this filter is shared between counters. .. code-block:: bash perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd .. note:: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and it will be reverted in driver automatically. so that the user can just specify axi_id to monitor a specific id, rather than having to specify axi_mask. .. code-block:: bash perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 ”h]”(h¸)”}”(hŒñWith DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). Filter is defined with two configuration parts: --AXI_ID defines AxID matching value. --AXI_MASKING defines which bits of AxID are meaningful for the matching.”h]”hŒñWith DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). Filter is defined with two configuration parts: --AXI_ID defines AxID matching value. --AXI_MASKING defines which bits of AxID are meaningful for the matching.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K#hjubhä)”}”(hŒf- 0: corresponding bit is masked. - 1: corresponding bit is not masked, i.e. used to do the matching. ”h]”j)”}”(hhh]”(j)”}”(hŒ0: corresponding bit is masked.”h]”h¸)”}”(hj6h]”hŒ0: corresponding bit is masked.”…””}”(hj8hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K(hj4ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj1ubj)”}”(hŒB1: corresponding bit is not masked, i.e. used to do the matching. ”h]”h¸)”}”(hŒA1: corresponding bit is not masked, i.e. used to do the matching.”h]”hŒA1: corresponding bit is not masked, i.e. used to do the matching.”…””}”(hjOhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K)hjKubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj1ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jhŸh¶h K(hj-ubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhŸh¶h K(hjubh¸)”}”(hŒÅAXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. When non-masked bits are matching corresponding AXI_ID bits then counter is incremented. Perf counter is incremented if::”h]”hŒÄAXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. When non-masked bits are matching corresponding AXI_ID bits then counter is incremented. Perf counter is incremented if:”…””}”(hjqhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K+hjubhê)”}”(hŒ,AxID && AXI_MASKING == AXI_ID && AXI_MASKING”h]”hŒ,AxID && AXI_MASKING == AXI_ID && AXI_MASKING”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hùhúuh1héhŸh¶h K/hjubh¸)”}”(hŒ’This filter doesn't support filter different AXI ID for axid-read and axid-write event at the same time as this filter is shared between counters.”h]”hŒ”This filter doesn’t support filter different AXI ID for axid-read and axid-write event at the same time as this filter is shared between counters.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K1hjubhê)”}”(hŒŽperf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd”h]”hŒŽperf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd”…””}”hj›sbah}”(h]”h ]”h"]”h$]”h&]”hùhúhû‰hüŒbash”hþ}”uh1héhŸh¶h K4hjubhŒnote”“”)”}”(hŒÞaxi_mask is inverted in userspace(i.e. set bits are bits to mask), and it will be reverted in driver automatically. so that the user can just specify axi_id to monitor a specific id, rather than having to specify axi_mask.”h]”h¸)”}”(hŒÞaxi_mask is inverted in userspace(i.e. set bits are bits to mask), and it will be reverted in driver automatically. so that the user can just specify axi_id to monitor a specific id, rather than having to specify axi_mask.”h]”hŒÞaxi_mask is inverted in userspace(i.e. set bits are bits to mask), and it will be reverted in driver automatically. so that the user can just specify axi_id to monitor a specific id, rather than having to specify axi_mask.”…””}”(hj±hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K;hj­ubah}”(h]”h ]”h"]”h$]”h&]”uh1j«hjubhê)”}”(hŒRperf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12”h]”hŒRperf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12”…””}”hjÅsbah}”(h]”h ]”h"]”h$]”h&]”hùhúhû‰hüŒbash”hþ}”uh1héhŸh¶h K?hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸNh Nubj)”}”(hX8With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits counting the number of bytes (as opposed to the number of bursts) from DDR read and write transactions concurrently with another set of data counters. ”h]”h¸)”}”(hX7With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits counting the number of bytes (as opposed to the number of bursts) from DDR read and write transactions concurrently with another set of data counters.”h]”hX7With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits counting the number of bytes (as opposed to the number of bursts) from DDR read and write transactions concurrently with another set of data counters.”…””}”(hjßhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KChjÛubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸh¶h Nubj)”}”(hX1With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). There is a limitation in previous AXI filter, it cannot filter different IDs at the same time as the filter is shared between counters. This quirk is the extension of AXI ID filter. One improvement is that counter 1-3 has their own filter, means that it supports concurrently filter various IDs. Another improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support selecting address channel or data channel. Filter is defined with 2 configuration registers per counter 1-3. --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT. - 0: address channel - 1: data channel PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved which should be 0. .. code-block:: bash perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd .. note:: axi_channel is inverted in userspace, and it will be reverted in driver automatically. So that users do not need specify axi_channel if want to monitor data channel from DDR transactions, since data channel is more meaningful.”h]”(h¸)”}”(hX With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). There is a limitation in previous AXI filter, it cannot filter different IDs at the same time as the filter is shared between counters. This quirk is the extension of AXI ID filter. One improvement is that counter 1-3 has their own filter, means that it supports concurrently filter various IDs. Another improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support selecting address channel or data channel.”h]”hX With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). There is a limitation in previous AXI filter, it cannot filter different IDs at the same time as the filter is shared between counters. This quirk is the extension of AXI ID filter. One improvement is that counter 1-3 has their own filter, means that it supports concurrently filter various IDs. Another improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support selecting address channel or data channel.”…””}”(hj÷hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KHhjóubh¸)”}”(hŒÈFilter is defined with 2 configuration registers per counter 1-3. --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.”h]”hŒÈFilter is defined with 2 configuration registers per counter 1-3. --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KPhjóubhä)”}”(hŒ'- 0: address channel - 1: data channel ”h]”j)”}”(hhh]”(j)”}”(hŒ0: address channel”h]”h¸)”}”(hjh]”hŒ0: address channel”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KThjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj)”}”(hŒ1: data channel ”h]”h¸)”}”(hŒ1: data channel”h]”hŒ1: data channel”…””}”(hj5hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KUhj1ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubeh}”(h]”h ]”h"]”h$]”h&]”jijjuh1jhŸh¶h KThjubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhŸh¶h KThjóubh¸)”}”(hŒ^PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved which should be 0.”h]”hŒ^PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved which should be 0.”…””}”(hjUhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KWhjóubhê)”}”(hŒ®perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd”h]”hŒ®perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd”…””}”hjcsbah}”(h]”h ]”h"]”h$]”h&]”hùhúhû‰hüŒbash”hþ}”uh1héhŸh¶h KZhjóubj¬)”}”(hŒâaxi_channel is inverted in userspace, and it will be reverted in driver automatically. So that users do not need specify axi_channel if want to monitor data channel from DDR transactions, since data channel is more meaningful.”h]”h¸)”}”(hŒâaxi_channel is inverted in userspace, and it will be reverted in driver automatically. So that users do not need specify axi_channel if want to monitor data channel from DDR transactions, since data channel is more meaningful.”h]”hŒâaxi_channel is inverted in userspace, and it will be reverted in driver automatically. So that users do not need specify axi_channel if want to monitor data channel from DDR transactions, since data channel is more meaningful.”…””}”(hjwhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kahjsubah}”(h]”h ]”h"]”h$]”h&]”uh1j«hjóubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”jiŒ*”uh1jhŸh¶h K#hh£hžhubeh}”(h]”Œ3freescale-i-mx8-ddr-performance-monitoring-unit-pmu”ah ]”h"]”Œ5freescale i.mx8 ddr performance monitoring unit (pmu)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jÃŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”jjšsŒ nametypes”}”j‰sh}”jšh£sŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.