ksphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget-/translations/zh_CN/admin-guide/perf/hisi-pmumodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/zh_TW/admin-guide/perf/hisi-pmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/it_IT/admin-guide/perf/hisi-pmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ja_JP/admin-guide/perf/hisi-pmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ko_KR/admin-guide/perf/hisi-pmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/pt_BR/admin-guide/perf/hisi-pmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/sp_SP/admin-guide/perf/hisi-pmumodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h6HiSilicon SoC uncore Performance Monitoring Unit (PMU)h]h6HiSilicon SoC uncore Performance Monitoring Unit (PMU)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhG/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/hisi-pmu.rsthKubh paragraph)}(hThe HiSilicon SoC chip includes various independent system device PMUs such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are independent and have hardware logic to gather statistics and performance information.h]hThe HiSilicon SoC chip includes various independent system device PMUs such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are independent and have hardware logic to gather statistics and performance information.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXThe HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster (CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.h]hXThe HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster (CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hHiSilicon SoC uncore PMU driverh]hHiSilicon SoC uncore PMU driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hEach device PMU has separate registers for event counting, control and interrupt, and the PMU driver shall register perf PMU drivers like L3C, HHA and DDRC etc. The available events and configuration options shall be described in the sysfs, see::h]hEach device PMU has separate registers for event counting, control and interrupt, and the PMU driver shall register perf PMU drivers like L3C, HHA and DDRC etc. The available events and configuration options shall be described in the sysfs, see:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh literal_block)}(hB/sys/bus/event_source/devices/hisi_sccl{X}_h]hB/sys/bus/event_source/devices/hisi_sccl{X}_}hj sbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jhhhKhhhhubh)}(hCThe "perf list" command shall list the available events from sysfs.h]hGThe “perf list” command shall list the available events from sysfs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hEach L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU name will appear in event listing as hisi_sccl_module. where "sccl-id" is the identifier of the SCCL and "index-id" is the index of module.h]hEach L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU name will appear in event listing as hisi_sccl_module. where “sccl-id” is the identifier of the SCCL and “index-id” is the index of module.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXe.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in SCCL ID #3.h]hXe.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in SCCL ID #3.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXe.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in SCCL ID #1.h]hXe.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in SCCL ID #1.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hhhhubh)}(hX}The driver also provides a "cpumask" sysfs attribute, which shows the CPU core ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is also provided to show the CPUs associated with this PMU. The "cpumask" indicates the CPUs to open the events, usually as a hint for userspaces tools like perf. It only contains one associated CPU from the "associated_cpus".h]hXThe driver also provides a “cpumask” sysfs attribute, which shows the CPU core ID used to count the uncore PMU event. An “associated_cpus” sysfs attribute is also provided to show the CPUs associated with this PMU. The “cpumask” indicates the CPUs to open the events, usually as a hint for userspaces tools like perf. It only contains one associated CPU from the “associated_cpus”.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hhhhubh)}(hExample usage of perf::h]hExample usage of perf:}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hhhhubj )}(hX$# perf list hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] ------------------------------------------ hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] ------------------------------------------ hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] ------------------------------------------ hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] ------------------------------------------ $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5h]hX$# perf list hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] ------------------------------------------ hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] ------------------------------------------ hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] ------------------------------------------ hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] ------------------------------------------ $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5}hjnsbah}(h]h ]h"]h$]h&]jjuh1jhhhK.hhhhubh)}(hFor HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same as PMU v1, but some new functions are added to the hardware.h]hFor HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same as PMU v1, but some new functions are added to the hardware.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hhhhubh)}(hd1. L3C PMU supports filtering by core/thread within the cluster which can be specified as a bitmap::h]hc1. L3C PMU supports filtering by core/thread within the cluster which can be specified as a bitmap:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hhhhubj )}(hC$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5h]hC$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKAhhhhubh)}(hMThis will only count the operations from core/thread 0 and 1 in this cluster.h]hMThis will only count the operations from core/thread 0 and 1 in this cluster.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChhhhubh)}(hUser should not use tt_core_deprecated to specify the core/thread filtering. This option is provided for backward compatiblility and only support 8bit which may not cover all the core/thread sharing L3C.h]hUser should not use tt_core_deprecated to specify the core/thread filtering. This option is provided for backward compatiblility and only support 8bit which may not cover all the core/thread sharing L3C.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhhhhubh)}(hXo2. Tracetag allow the user to chose to count only read, write or atomic operations via the tt_req parameeter in perf. The default value counts all operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101 represents write operations, 3'b110 represents atomic store operations and 3'b111 represents atomic non-store operations, other values are reserved::h]hXv2. Tracetag allow the user to chose to count only read, write or atomic operations via the tt_req parameeter in perf. The default value counts all operations. tt_req is 3bits, 3’b100 represents read operations, 3’b101 represents write operations, 3’b110 represents atomic store operations and 3’b111 represents atomic non-store operations, other values are reserved:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhhhhubj )}(hB$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5h]hB$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKOhhhhubh)}(h9This will only count the read operations in this cluster.h]h9This will only count the read operations in this cluster.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhhhhubh)}(hq3. Datasrc allows the user to check where the data comes from. It is 5 bits. Some important codes are as follows:h]hq3. Datasrc allows the user to check where the data comes from. It is 5 bits. Some important codes are as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShhhhubh bullet_list)}(hhh](h list_item)}(h%5'b00001: comes from L3C in this die;h]h)}(hjh]h'5’b00001: comes from L3C in this die;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h*5'b01000: comes from L3C in the cross-die;h]h)}(hjh]h,5’b01000: comes from L3C in the cross-die;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h45'b01001: comes from L3C which is in another socket;h]h)}(hj1h]h65’b01001: comes from L3C which is in another socket;}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj/ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h#5'b01110: comes from the local DDR;h]h)}(hjHh]h%5’b01110: comes from the local DDR;}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjFubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h'5'b01111: comes from the cross-die DDR;h]h)}(hj_h]h)5’b01111: comes from the cross-die DDR;}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhj]ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h'5'b10000: comes from cross-socket DDR; h]h)}(h&5'b10000: comes from cross-socket DDR;h]h(5’b10000: comes from cross-socket DDR;}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjtubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKVhhhhubh)}(hetc, it is mainly helpful to find that the data source is nearest from the CPU cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be configured in perf command::h]hetc, it is mainly helpful to find that the data source is nearest from the CPU cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be configured in perf command:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hhhhubj )}(hu$# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/, hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5h]hu$# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/, hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKahhhhubh)}(hX`4. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die contains several Compute Clusters (CCLs). The I/O dies are called Super I/O clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit CCL/ICL-ID. For I/O die, the ICL-ID is followed by:h]hX`4. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die contains several Compute Clusters (CCLs). The I/O dies are called Super I/O clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit CCL/ICL-ID. For I/O die, the ICL-ID is followed by:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhhhhubj)}(hhh](j)}(h5'b00000: I/O_MGMT_ICL;h]h)}(hjh]h5’b00000: I/O_MGMT_ICL;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5'b00001: Network_ICL;h]h)}(hjh]h5’b00001: Network_ICL;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5'b00011: HAC_ICL;h]h)}(hjh]h5’b00011: HAC_ICL;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5'b10000: PCIe_ICL; h]h)}(h5'b10000: PCIe_ICL;h]h5’b10000: PCIe_ICL;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKjhhhhubh)}(h5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request uring channel. It is 2 bits. Some important codes are as follows:h]h5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request uring channel. It is 2 bits. Some important codes are as follows:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohhhhubj)}(hhh](j)}(hC2'b11: count the events which sent to the uring_ext (MATA) channel;h]h)}(hj7h]hE2’b11: count the events which sent to the uring_ext (MATA) channel;}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhj5ubah}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubj)}(h2'b01: is the same as 2'b11;h]h)}(hjNh]h 2’b01: is the same as 2’b11;}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjLubah}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubj)}(hC2'b10: count the events which sent to the uring (non-MATA) channel;h]h)}(hjeh]hE2’b10: count the events which sent to the uring (non-MATA) channel;}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjcubah}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubj)}(hX2'b00: default value, count the events which sent to both uring and uring_ext channels; h]h)}(hW2'b00: default value, count the events which sent to both uring and uring_ext channels;h]hY2’b00: default value, count the events which sent to both uring and uring_ext channels;}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjzubah}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKrhhhhubh)}(h6. ch: NoC PMU supports filtering the event counts of certain transaction channel with this option. The current supported channels are as follows:h]h6. ch: NoC PMU supports filtering the event counts of certain transaction channel with this option. The current supported channels are as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhhhhubj)}(hhh](j)}(h3'b010: Request channelh]h)}(hjh]h3’b010: Request channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h3'b100: Snoop channelh]h)}(hjh]h3’b100: Snoop channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h3'b110: Response channelh]h)}(hjh]h3’b110: Response channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h3'b111: Data channel h]h)}(h3'b111: Data channelh]h3’b111: Data channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhK{hhhhubh)}(h7. tt_en: NoC PMU supports counting only transactions that have tracetag set if this option is set. See the 2nd list for more information about tracetag.h]h7. tt_en: NoC PMU supports counting only transactions that have tracetag set if this option is set. See the 2nd list for more information about tracetag.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXLFor HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are further divided into parts for finer granularity of tracing, each part has its own dedicated PMU, and all such PMUs together cover the monitoring job of events on particular uncore device. Such PMUs are described in sysfs with name format slightly changed::h]hXKFor HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are further divided into parts for finer granularity of tracing, each part has its own dedicated PMU, and all such PMUs together cover the monitoring job of events on particular uncore device. Such PMUs are described in sysfs with name format slightly changed:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubj )}(hN/sys/bus/event_source/devices/hisi_sccl{X}_h]hN/sys/bus/event_source/devices/hisi_sccl{X}_}hj(sbah}(h]h ]h"]h$]h&]jjuh1jhhhKhhhhubh)}(hGZ is the sub-id, indicating different PMUs for part of hardware device.h]hGZ is the sub-id, indicating different PMUs for part of hardware device.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXUsage of most PMUs with different sub-ids are identical. Specially, L3C PMU provides ``ext`` option to allow exploration of even finer granual statistics of L3C PMU. L3C PMU driver uses that as hint of termination when delivering perf command to hardware:h](hUUsage of most PMUs with different sub-ids are identical. Specially, L3C PMU provides }(hjDhhhNhNubhliteral)}(h``ext``h]hext}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjDubh option to allow exploration of even finer granual statistics of L3C PMU. L3C PMU driver uses that as hint of termination when delivering perf command to hardware:}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubj)}(hhh](j)}(h/ext=0: Default, could be used with event names.h]h)}(hjkh]h/ext=0: Default, could be used with event names.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjiubah}(h]h ]h"]h$]h&]uh1jhjfhhhhhNubj)}(hOext=1 and ext=2: Must be used with event codes, event names are not supported. h]h)}(hNext=1 and ext=2: Must be used with event codes, event names are not supported.h]hNext=1 and ext=2: Must be used with event codes, event names are not supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjfhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhhhhubh)}(h%An example of perf command could be::h]h$An example of perf command could be:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubj )}(h6$# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5h]h6$# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhhhhubh)}(hor::h]hor:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubj )}(h=$# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5h]h=$# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhhhhubh)}(hUAs above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1 pipe0.h](h As above, }(hjhhhNhNubjM)}(h``hisi_sccl0_l3c1_0``h]hhisi_sccl0_l3c1_0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjubh6 locates PMU of Super CPU CLuster 0, L3 cache 1 pipe0.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hFirst command locates the first part of L3C since ``ext=0`` is implied by default. Second command issues the counting on another part of L3C with the event ``0x1``.h](h2First command locates the first part of L3C since }(hjhhhNhNubjM)}(h ``ext=0``h]hext=0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjubha is implied by default. Second command issues the counting on another part of L3C with the event }(hjhhhNhNubjM)}(h``0x1``h]h0x1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX$Users could configure IDs to count data come from specific CCL/ICL, by setting srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not check the bit when matching against the srcid_cmd/tgtid_cmd.h]hX$Users could configure IDs to count data come from specific CCL/ICL, by setting srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not check the bit when matching against the srcid_cmd/tgtid_cmd.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hIf all of these options are disabled, it can works by the default value that doesn't distinguish the filter condition and ID information and will return the total counter values in the PMU counters.h]hIf all of these options are disabled, it can works by the default value that doesn’t distinguish the filter condition and ID information and will return the total counter values in the PMU counters.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThe current driver does not support sampling. So "perf record" is unsupported. Also attach to a task is unsupported as the events are all uncore.h]hThe current driver does not support sampling. So “perf record” is unsupported. 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