€•àO      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ-/translations/zh_CN/admin-guide/perf/hisi-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ-/translations/zh_TW/admin-guide/perf/hisi-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ-/translations/it_IT/admin-guide/perf/hisi-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ-/translations/ja_JP/admin-guide/perf/hisi-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ-/translations/ko_KR/admin-guide/perf/hisi-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ-/translations/sp_SP/admin-guide/perf/hisi-pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ6HiSilicon SoC uncore Performance Monitoring Unit (PMU)”h]”hŒ6HiSilicon SoC uncore Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒG/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/hisi-pmu.rst”h KubhŒ	paragraph”“”)”}”(hŒäThe HiSilicon SoC chip includes various independent system device PMUs
such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
independent and have hardware logic to gather statistics and performance
information.”h]”hŒäThe HiSilicon SoC chip includes various independent system device PMUs
such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
independent and have hardware logic to gather statistics and performance
information.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hX  The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.”h]”hX  The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K
hh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒHiSilicon SoC uncore PMU driver”h]”hŒHiSilicon SoC uncore PMU driver”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhÕhžhhŸh¶h Kubh¸)”}”(hŒõEach device PMU has separate registers for event counting, control and
interrupt, and the PMU driver shall register perf PMU drivers like L3C,
HHA and DDRC etc. The available events and configuration options shall
be described in the sysfs, see:”h]”hŒõEach device PMU has separate registers for event counting, control and
interrupt, and the PMU driver shall register perf PMU drivers like L3C,
HHA and DDRC etc. The available events and configuration options shall
be described in the sysfs, see:”…””}”(hhæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubh¸)”}”(hŒ‡/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
The "perf list" command shall list the available events from sysfs.”h]”hŒ‹/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
The â€œperf listâ€ command shall list the available events from sysfs.”…””}”(hhôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubh¸)”}”(hŒèEach L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
module.”h]”hŒðEach L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
where â€œsccl-idâ€ is the identifier of the SCCL and â€œindex-idâ€ is the index of
module.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubh¸)”}”(hŒXe.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
SCCL ID #3.”h]”hŒXe.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
SCCL ID #3.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubh¸)”}”(hŒXe.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
SCCL ID #1.”h]”hŒXe.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
SCCL ID #1.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K"hhÕhžhubh¸)”}”(hX}  The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is
also provided to show the CPUs associated with this PMU. The "cpumask" indicates
the CPUs to open the events, usually as a hint for userspaces tools like perf.
It only contains one associated CPU from the "associated_cpus".”h]”hX  The driver also provides a â€œcpumaskâ€ sysfs attribute, which shows the CPU core
ID used to count the uncore PMU event. An â€œassociated_cpusâ€ sysfs attribute is
also provided to show the CPUs associated with this PMU. The â€œcpumaskâ€ indicates
the CPUs to open the events, usually as a hint for userspaces tools like perf.
It only contains one associated CPU from the â€œassociated_cpusâ€.”…””}”(hj,  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K%hhÕhžhubh¸)”}”(hŒExample usage of perf::”h]”hŒExample usage of perf:”…””}”(hj:  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K+hhÕhžhubhŒliteral_block”“”)”}”(hXî  $# perf list
hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
------------------------------------------
hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
------------------------------------------
hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
------------------------------------------
hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
------------------------------------------

$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5”h]”hXî  $# perf list
hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
------------------------------------------
hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
------------------------------------------
hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
------------------------------------------
hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
------------------------------------------

$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5”…””}”hjJ  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jH  hŸh¶h K-hhÕhžhubh¸)”}”(hŒ‹For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
as PMU v1, but some new functions are added to the hardware.”h]”hŒ‹For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
as PMU v1, but some new functions are added to the hardware.”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K:hhÕhžhubh¸)”}”(hŒd1. L3C PMU supports filtering by core/thread within the cluster which can be
specified as a bitmap::”h]”hŒc1. L3C PMU supports filtering by core/thread within the cluster which can be
specified as a bitmap:”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K=hhÕhžhubjI  )”}”(hŒC$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5”h]”hŒC$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5”…””}”hjv  sbah}”(h]”h ]”h"]”h$]”h&]”jX  jY  uh1jH  hŸh¶h K@hhÕhžhubh¸)”}”(hŒMThis will only count the operations from core/thread 0 and 1 in this cluster.”h]”hŒMThis will only count the operations from core/thread 0 and 1 in this cluster.”…””}”(hj„  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KBhhÕhžhubh¸)”}”(hXo  2. Tracetag allow the user to chose to count only read, write or atomic
operations via the tt_req parameeter in perf. The default value counts all
operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101
represents write operations, 3'b110 represents atomic store operations and
3'b111 represents atomic non-store operations, other values are reserved::”h]”hXv  2. Tracetag allow the user to chose to count only read, write or atomic
operations via the tt_req parameeter in perf. The default value counts all
operations. tt_req is 3bits, 3â€™b100 represents read operations, 3â€™b101
represents write operations, 3â€™b110 represents atomic store operations and
3â€™b111 represents atomic non-store operations, other values are reserved:”…””}”(hj’  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KDhhÕhžhubjI  )”}”(hŒB$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5”h]”hŒB$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”jX  jY  uh1jH  hŸh¶h KJhhÕhžhubh¸)”}”(hŒ9This will only count the read operations in this cluster.”h]”hŒ9This will only count the read operations in this cluster.”…””}”(hj®  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KLhhÕhžhubh¸)”}”(hŒq3. Datasrc allows the user to check where the data comes from. It is 5 bits.
Some important codes are as follows:”h]”hŒq3. Datasrc allows the user to check where the data comes from. It is 5 bits.
Some important codes are as follows:”…””}”(hj¼  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KNhhÕhžhubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ%5'b00001: comes from L3C in this die;”h]”h¸)”}”(hjÓ  h]”hŒ'5â€™b00001: comes from L3C in this die;”…””}”(hjÕ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KQhjÑ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjÌ  hžhhŸh¶h NubjÐ  )”}”(hŒ*5'b01000: comes from L3C in the cross-die;”h]”h¸)”}”(hjê  h]”hŒ,5â€™b01000: comes from L3C in the cross-die;”…””}”(hjì  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KRhjè  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjÌ  hžhhŸh¶h NubjÐ  )”}”(hŒ45'b01001: comes from L3C which is in another socket;”h]”h¸)”}”(hj  h]”hŒ65â€™b01001: comes from L3C which is in another socket;”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KShjÿ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjÌ  hžhhŸh¶h NubjÐ  )”}”(hŒ#5'b01110: comes from the local DDR;”h]”h¸)”}”(hj  h]”hŒ%5â€™b01110: comes from the local DDR;”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KThj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjÌ  hžhhŸh¶h NubjÐ  )”}”(hŒ'5'b01111: comes from the cross-die DDR;”h]”h¸)”}”(hj/  h]”hŒ)5â€™b01111: comes from the cross-die DDR;”…””}”(hj1  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KUhj-  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjÌ  hžhhŸh¶h NubjÐ  )”}”(hŒ'5'b10000: comes from cross-socket DDR;
”h]”h¸)”}”(hŒ&5'b10000: comes from cross-socket DDR;”h]”hŒ(5â€™b10000: comes from cross-socket DDR;”…””}”(hjH  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KVhjD  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjÌ  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jÊ  hŸh¶h KQhhÕhžhubh¸)”}”(hŒ¶etc, it is mainly helpful to find that the data source is nearest from the CPU
cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be
configured in perf command::”h]”hŒµetc, it is mainly helpful to find that the data source is nearest from the CPU
cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be
configured in perf command:”…””}”(hjd  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KXhhÕhžhubjI  )”}”(hŒu$# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5”h]”hŒu$# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5”…””}”hjr  sbah}”(h]”h ]”h"]”h$]”h&]”jX  jY  uh1jH  hŸh¶h K\hhÕhžhubh¸)”}”(hX`  4. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die
contains several Compute Clusters (CCLs). The I/O dies are called Super I/O
clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the
SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
CCL/ICL-ID. For I/O die, the ICL-ID is followed by:”h]”hX`  4. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die
contains several Compute Clusters (CCLs). The I/O dies are called Super I/O
clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the
SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
CCL/ICL-ID. For I/O die, the ICL-ID is followed by:”…””}”(hj€  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K_hhÕhžhubjË  )”}”(hhh]”(jÐ  )”}”(hŒ5'b00000: I/O_MGMT_ICL;”h]”h¸)”}”(hj“  h]”hŒ5â€™b00000: I/O_MGMT_ICL;”…””}”(hj•  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kehj‘  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjŽ  hžhhŸh¶h NubjÐ  )”}”(hŒ5'b00001: Network_ICL;”h]”h¸)”}”(hjª  h]”hŒ5â€™b00001: Network_ICL;”…””}”(hj¬  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kfhj¨  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjŽ  hžhhŸh¶h NubjÐ  )”}”(hŒ5'b00011: HAC_ICL;”h]”h¸)”}”(hjÁ  h]”hŒ5â€™b00011: HAC_ICL;”…””}”(hjÃ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kghj¿  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjŽ  hžhhŸh¶h NubjÐ  )”}”(hŒ5'b10000: PCIe_ICL;
”h]”h¸)”}”(hŒ5'b10000: PCIe_ICL;”h]”hŒ5â€™b10000: PCIe_ICL;”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhjÖ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hjŽ  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jb  jc  uh1jÊ  hŸh¶h KehhÕhžhubh¸)”}”(hŒŒ5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
uring channel. It is 2 bits. Some important codes are as follows:”h]”hŒŒ5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
uring channel. It is 2 bits. Some important codes are as follows:”…””}”(hjô  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KjhhÕhžhubjË  )”}”(hhh]”(jÐ  )”}”(hŒC2'b11: count the events which sent to the uring_ext (MATA) channel;”h]”h¸)”}”(hj  h]”hŒE2â€™b11: count the events which sent to the uring_ext (MATA) channel;”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kmhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hj  hžhhŸh¶h NubjÐ  )”}”(hŒ2'b01: is the same as 2'b11;”h]”h¸)”}”(hj  h]”hŒ 2â€™b01: is the same as 2â€™b11;”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Knhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hj  hžhhŸh¶h NubjÐ  )”}”(hŒC2'b10: count the events which sent to the uring (non-MATA) channel;”h]”h¸)”}”(hj5  h]”hŒE2â€™b10: count the events which sent to the uring (non-MATA) channel;”…””}”(hj7  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kohj3  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hj  hžhhŸh¶h NubjÐ  )”}”(hŒ[2'b00: default value, count the events which sent to the both uring and
uring_ext channel;
”h]”h¸)”}”(hŒZ2'b00: default value, count the events which sent to the both uring and
uring_ext channel;”h]”hŒ\2â€™b00: default value, count the events which sent to the both uring and
uring_ext channel;”…””}”(hjN  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KphjJ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÏ  hj  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jb  jc  uh1jÊ  hŸh¶h KmhhÕhžhubh¸)”}”(hX$  Users could configure IDs to count data come from specific CCL/ICL, by setting
srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
check the bit when matching against the srcid_cmd/tgtid_cmd.”h]”hX$  Users could configure IDs to count data come from specific CCL/ICL, by setting
srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
check the bit when matching against the srcid_cmd/tgtid_cmd.”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KshhÕhžhubh¸)”}”(hŒÆIf all of these options are disabled, it can works by the default value that
doesn't distinguish the filter condition and ID information and will return
the total counter values in the PMU counters.”h]”hŒÈIf all of these options are disabled, it can works by the default value that
doesnâ€™t distinguish the filter condition and ID information and will return
the total counter values in the PMU counters.”…””}”(hjv  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KxhhÕhžhubh¸)”}”(hŒ‘The current driver does not support sampling. So "perf record" is unsupported.
Also attach to a task is unsupported as the events are all uncore.”h]”hŒ•The current driver does not support sampling. So â€œperf recordâ€ is unsupported.
Also attach to a task is unsupported as the events are all uncore.”…””}”(hj„  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K|hhÕhžhubh¸)”}”(hŒ‰Note: Please contact the maintainer for a complete list of events supported for
the PMU devices in the SoC and its information if needed.”h]”hŒ‰Note: Please contact the maintainer for a complete list of events supported for
the PMU devices in the SoC and its information if needed.”…””}”(hj’  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubeh}”(h]”Œhisilicon-soc-uncore-pmu-driver”ah ]”h"]”Œhisilicon soc uncore pmu driver”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubeh}”(h]”Œ4hisilicon-soc-uncore-performance-monitoring-unit-pmu”ah ]”h"]”Œ6hisilicon soc uncore performance monitoring unit (pmu)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jÓ  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j­  jª  j¥  j¢  uŒ	nametypes”}”(j­  ‰j¥  ‰uh}”(jª  h£j¢  hÕuŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.