€•$=Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ1/translations/zh_CN/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/zh_TW/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/it_IT/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ja_JP/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ko_KR/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/sp_SP/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒFSynopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)”h]”hŒFSynopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒK/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/dwc_pcie_pmu.rst”h Kubh¢)”}”(hhh]”(h§)”}”(hŒDesignWare Cores (DWC) PCIe PMU”h]”hŒDesignWare Cores (DWC) PCIe PMU”…””}”(hhºhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh·hžhhŸh¶h KubhŒ paragraph”“”)”}”(hŒ·The PMU is a PCIe configuration space register block provided by each PCIe Root Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error injection, and Statistics).”h]”hŒ·The PMU is a PCIe configuration space register block provided by each PCIe Root Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error injection, and Statistics).”…””}”(hhÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khh·hžhubhÉ)”}”(hŒøAs the name indicates, the RAS DES capability supports system level debugging, AER error injection, and collection of statistics. To facilitate collection of statistics, Synopsys DesignWare Cores PCIe controller provides the following two features:”h]”hŒøAs the name indicates, the RAS DES capability supports system level debugging, AER error injection, and collection of statistics. To facilitate collection of statistics, Synopsys DesignWare Cores PCIe controller provides the following two features:”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K hh·hžhubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒsone 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and”h]”hÉ)”}”(hŒsone 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and”h]”hŒsone 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and”…””}”(hhñhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khhíubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhhèhžhhŸh¶h Nubhì)”}”(hŒXone 32-bit counter for Event Counting (error and non-error events for a specified lane) ”h]”hÉ)”}”(hŒWone 32-bit counter for Event Counting (error and non-error events for a specified lane)”h]”hŒWone 32-bit counter for Event Counting (error and non-error events for a specified lane)”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhhèhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1hæhŸh¶h Khh·hžhubhÉ)”}”(hŒ1Note: There is no interrupt for counter overflow.”h]”hŒ1Note: There is no interrupt for counter overflow.”…””}”(hj%hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khh·hžhubh¢)”}”(hhh]”(h§)”}”(hŒTime Based Analysis”h]”hŒTime Based Analysis”…””}”(hj6hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj3hžhhŸh¶h KubhÉ)”}”(hŒ¶Using this feature you can obtain information regarding RX/TX data throughput and time spent in each low-power LTSSM state by the controller. The PMU measures data in two categories:”h]”hŒ¶Using this feature you can obtain information regarding RX/TX data throughput and time spent in each low-power LTSSM state by the controller. The PMU measures data in two categories:”…””}”(hjDhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khj3hžhubhç)”}”(hhh]”(hì)”}”(hŒAGroup#0: Percentage of time the controller stays in LTSSM states.”h]”hÉ)”}”(hjWh]”hŒAGroup#0: Percentage of time the controller stays in LTSSM states.”…””}”(hjYhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KhjUubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhjRhžhhŸh¶h Nubhì)”}”(hŒ7Group#1: Amount of data processed (Units of 16 bytes). ”h]”hÉ)”}”(hŒ6Group#1: Amount of data processed (Units of 16 bytes).”h]”hŒ6Group#1: Amount of data processed (Units of 16 bytes).”…””}”(hjphžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K hjlubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhjRhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j#j$uh1hæhŸh¶h Khj3hžhubeh}”(h]”Œtime-based-analysis”ah ]”h"]”Œtime based analysis”ah$]”h&]”uh1h¡hh·hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒLane Event counters”h]”hŒLane Event counters”…””}”(hj•hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj’hžhhŸh¶h K#ubhÉ)”}”(hŒŠUsing this feature you can obtain Error and Non-Error information in specific lane by the controller. The PMU event is selected by all of:”h]”hŒŠUsing this feature you can obtain Error and Non-Error information in specific lane by the controller. The PMU event is selected by all of:”…””}”(hj£hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K%hj’hžhubhç)”}”(hhh]”(hì)”}”(hŒGroup i”h]”hÉ)”}”(hj¶h]”hŒGroup i”…””}”(hj¸hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K(hj´ubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhj±hžhhŸh¶h Nubhì)”}”(hŒEvent j within the Group i”h]”hÉ)”}”(hjÍh]”hŒEvent j within the Group i”…””}”(hjÏhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K)hjËubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhj±hžhhŸh¶h Nubhì)”}”(hŒLane k ”h]”hÉ)”}”(hŒLane k”h]”hŒLane k”…””}”(hjæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K*hjâubah}”(h]”h ]”h"]”h$]”h&]”uh1hëhj±hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j#j$uh1hæhŸh¶h K(hj’hžhubhÉ)”}”(hŒ:Some of the events only exist for specific configurations.”h]”hŒ:Some of the events only exist for specific configurations.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K,hj’hžhubeh}”(h]”Œlane-event-counters”ah ]”h"]”Œlane event counters”ah$]”h&]”uh1h¡hh·hžhhŸh¶h K#ubeh}”(h]”Œdesignware-cores-dwc-pcie-pmu”ah ]”h"]”Œdesignware cores (dwc) pcie pmu”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒ&DesignWare Cores (DWC) PCIe PMU Driver”h]”hŒ&DesignWare Cores (DWC) PCIe PMU Driver”…””}”(hj!hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjhžhhŸh¶h K/ubhÉ)”}”(hŒkThis driver adds PMU devices for each PCIe Root Port named based on the SBDF of the Root Port. For example,”h]”hŒkThis driver adds PMU devices for each PCIe Root Port named based on the SBDF of the Root Port. For example,”…””}”(hj/hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K1hjhžhubhŒ block_quote”“”)”}”(hŒ30001:30:03.0 PCI bridge: Device 1ded:8000 (rev 01) ”h]”hÉ)”}”(hŒ20001:30:03.0 PCI bridge: Device 1ded:8000 (rev 01)”h]”hŒ20001:30:03.0 PCI bridge: Device 1ded:8000 (rev 01)”…””}”(hjChžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K4hj?ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=hŸh¶h K4hjhžhubhÉ)”}”(hŒ=the PMU device name for this Root Port is dwc_rootport_13018.”h]”hŒ=the PMU device name for this Root Port is dwc_rootport_13018.”…””}”(hjWhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K6hjhžhubhÉ)”}”(hŒ¾The DWC PCIe PMU driver registers a perf PMU driver, which provides description of available events and configuration options in sysfs, see /sys/bus/event_source/devices/dwc_rootport_{sbdf}.”h]”hŒ¾The DWC PCIe PMU driver registers a perf PMU driver, which provides description of available events and configuration options in sysfs, see /sys/bus/event_source/devices/dwc_rootport_{sbdf}.”…””}”(hjehžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K8hjhžhubhÉ)”}”(hXThe "format" directory describes format of the config fields of the perf_event_attr structure. The "events" directory provides configuration templates for all documented events. For example, "rx_pcie_tlp_data_payload" is an equivalent of "eventid=0x21,type=0x0".”h]”hXThe “format†directory describes format of the config fields of the perf_event_attr structure. The “events†directory provides configuration templates for all documented events. For example, “rx_pcie_tlp_data_payload†is an equivalent of “eventid=0x21,type=0x0â€.”…””}”(hjshžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/ [Kernel PMU event] <...> dwc_rootport_13018/rx_memory_read,lane=?/ [Kernel PMU event]”h]”hŒ¾$# perf list | grep dwc_rootport <...> dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/ [Kernel PMU event] <...> dwc_rootport_13018/rx_memory_read,lane=?/ [Kernel PMU event]”…””}”hj‘sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1jhŸh¶h KChjhžhubh¢)”}”(hhh]”(h§)”}”(hŒTime Based Analysis Event Usage”h]”hŒTime Based Analysis Event Usage”…””}”(hj¤hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¡hžhhŸh¶h KJubhÉ)”}”(hŒEExample usage of counting PCIe RX TLP data payload (Units of bytes)::”h]”hŒDExample usage of counting PCIe RX TLP data payload (Units of bytes):”…””}”(hj²hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KLhj¡hžhubj)”}”(hŒ?$# perf stat -a -e dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/”h]”hŒ?$# perf stat -a -e dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/”…””}”hjÀsbah}”(h]”h ]”h"]”h$]”h&]”jŸj uh1jhŸh¶h KNhj¡hžhubhÉ)”}”(hŒJThe average RX/TX bandwidth can be calculated using the following formula:”h]”hŒJThe average RX/TX bandwidth can be calculated using the following formula:”…””}”(hjÎhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KPhj¡hžhubj>)”}”(hŒ†PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window ”h]”hÉ)”}”(hŒ…PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window”h]”hŒ…PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window”…””}”(hjàhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KRhjÜubah}”(h]”h ]”h"]”h$]”h&]”uh1j=hŸh¶h KRhj¡hžhubeh}”(h]”Œtime-based-analysis-event-usage”ah ]”h"]”Œtime based analysis event usage”ah$]”h&]”uh1h¡hjhžhhŸh¶h KJubh¢)”}”(hhh]”(h§)”}”(hŒLane Event Usage”h]”hŒLane Event Usage”…””}”(hjÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjühžhhŸh¶h KVubhÉ)”}”(hŒŽEach lane has the same event set and to avoid generating a list of hundreds of events, the user need to specify the lane ID explicitly, e.g.::”h]”hŒEach lane has the same event set and to avoid generating a list of hundreds of events, the user need to specify the lane ID explicitly, e.g.:”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KXhjühžhubj)”}”(hŒ<$# perf stat -a -e dwc_rootport_13018/rx_memory_read,lane=4/”h]”hŒ<$# perf stat -a -e dwc_rootport_13018/rx_memory_read,lane=4/”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”jŸj uh1jhŸh¶h K[hjühžhubhÉ)”}”(hŒ…The driver does not support sampling, therefore "perf record" will not work. Per-task (without "-a") perf sessions are not supported.”h]”hŒThe driver does not support sampling, therefore “perf record†will not work. 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