€•7>Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ1/translations/zh_CN/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/zh_TW/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/it_IT/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ja_JP/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ko_KR/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/pt_BR/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/sp_SP/admin-guide/perf/dwc_pcie_pmu”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒFSynopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)”h]”hŒFSynopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒK/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/dwc_pcie_pmu.rst”h´Kubh¶)”}”(hhh]”(h»)”}”(hŒDesignWare Cores (DWC) PCIe PMU”h]”hŒDesignWare Cores (DWC) PCIe PMU”…””}”(hhÎh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhËh²hh³hÊh´KubhŒ paragraph”“”)”}”(hŒ·The PMU is a PCIe configuration space register block provided by each PCIe Root Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error injection, and Statistics).”h]”hŒ·The PMU is a PCIe configuration space register block provided by each PCIe Root Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error injection, and Statistics).”…””}”(hhÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)”}”(hŒøAs the name indicates, the RAS DES capability supports system level debugging, AER error injection, and collection of statistics. To facilitate collection of statistics, Synopsys DesignWare Cores PCIe controller provides the following two features:”h]”hŒøAs the name indicates, the RAS DES capability supports system level debugging, AER error injection, and collection of statistics. To facilitate collection of statistics, Synopsys DesignWare Cores PCIe controller provides the following two features:”…””}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K hhËh²hubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒsone 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and”h]”hÝ)”}”(hŒsone 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and”h]”hŒsone 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhhüh²hh³hÊh´Nubj)”}”(hŒbone 32-bit counter per event for Event Counting (error and non-error events for a specified lane) ”h]”hÝ)”}”(hŒaone 32-bit counter per event for Event Counting (error and non-error events for a specified lane)”h]”hŒaone 32-bit counter per event for Event Counting (error and non-error events for a specified lane)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhhüh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1húh³hÊh´KhhËh²hubhÝ)”}”(hŒ1Note: There is no interrupt for counter overflow.”h]”hŒ1Note: There is no interrupt for counter overflow.”…””}”(hj9h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubh¶)”}”(hhh]”(h»)”}”(hŒTime Based Analysis”h]”hŒTime Based Analysis”…””}”(hjJh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjGh²hh³hÊh´KubhÝ)”}”(hŒ¶Using this feature you can obtain information regarding RX/TX data throughput and time spent in each low-power LTSSM state by the controller. The PMU measures data in two categories:”h]”hŒ¶Using this feature you can obtain information regarding RX/TX data throughput and time spent in each low-power LTSSM state by the controller. The PMU measures data in two categories:”…””}”(hjXh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhjGh²hubhû)”}”(hhh]”(j)”}”(hŒAGroup#0: Percentage of time the controller stays in LTSSM states.”h]”hÝ)”}”(hjkh]”hŒAGroup#0: Percentage of time the controller stays in LTSSM states.”…””}”(hjmh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjiubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhjfh²hh³hÊh´Nubj)”}”(hŒ7Group#1: Amount of data processed (Units of 16 bytes). ”h]”hÝ)”}”(hŒ6Group#1: Amount of data processed (Units of 16 bytes).”h]”hŒ6Group#1: Amount of data processed (Units of 16 bytes).”…””}”(hj„h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K hj€ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhjfh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j7j8uh1húh³hÊh´KhjGh²hubeh}”(h]”Œtime-based-analysis”ah ]”h"]”Œtime based analysis”ah$]”h&]”uh1hµhhËh²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒLane Event counters”h]”hŒLane Event counters”…””}”(hj©h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj¦h²hh³hÊh´K#ubhÝ)”}”(hŒŠUsing this feature you can obtain Error and Non-Error information in specific lane by the controller. The PMU event is selected by all of:”h]”hŒŠUsing this feature you can obtain Error and Non-Error information in specific lane by the controller. The PMU event is selected by all of:”…””}”(hj·h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K%hj¦h²hubhû)”}”(hhh]”(j)”}”(hŒGroup i”h]”hÝ)”}”(hjÊh]”hŒGroup i”…””}”(hjÌh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K(hjÈubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhjÅh²hh³hÊh´Nubj)”}”(hŒEvent j within the Group i”h]”hÝ)”}”(hjáh]”hŒEvent j within the Group i”…””}”(hjãh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K)hjßubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhjÅh²hh³hÊh´Nubj)”}”(hŒLane k ”h]”hÝ)”}”(hŒLane k”h]”hŒLane k”…””}”(hjúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K*hjöubah}”(h]”h ]”h"]”h$]”h&]”uh1hÿhjÅh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j7j8uh1húh³hÊh´K(hj¦h²hubhÝ)”}”(hŒ:Some of the events only exist for specific configurations.”h]”hŒ:Some of the events only exist for specific configurations.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K,hj¦h²hubeh}”(h]”Œlane-event-counters”ah ]”h"]”Œlane event counters”ah$]”h&]”uh1hµhhËh²hh³hÊh´K#ubeh}”(h]”Œdesignware-cores-dwc-pcie-pmu”ah ]”h"]”Œdesignware cores (dwc) pcie pmu”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒ&DesignWare Cores (DWC) PCIe PMU Driver”h]”hŒ&DesignWare Cores (DWC) PCIe PMU Driver”…””}”(hj5h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj2h²hh³hÊh´K/ubhÝ)”}”(hŒkThis driver adds PMU devices for each PCIe Root Port named based on the SBDF of the Root Port. For example,”h]”hŒkThis driver adds PMU devices for each PCIe Root Port named based on the SBDF of the Root Port. For example,”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K1hj2h²hubhŒ block_quote”“”)”}”(hŒ30001:30:03.0 PCI bridge: Device 1ded:8000 (rev 01) ”h]”hÝ)”}”(hŒ20001:30:03.0 PCI bridge: Device 1ded:8000 (rev 01)”h]”hŒ20001:30:03.0 PCI bridge: Device 1ded:8000 (rev 01)”…””}”(hjWh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K4hjSubah}”(h]”h ]”h"]”h$]”h&]”uh1jQh³hÊh´K4hj2h²hubhÝ)”}”(hŒ=the PMU device name for this Root Port is dwc_rootport_13018.”h]”hŒ=the PMU device name for this Root Port is dwc_rootport_13018.”…””}”(hjkh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K6hj2h²hubhÝ)”}”(hŒ¾The DWC PCIe PMU driver registers a perf PMU driver, which provides description of available events and configuration options in sysfs, see /sys/bus/event_source/devices/dwc_rootport_{sbdf}.”h]”hŒ¾The DWC PCIe PMU driver registers a perf PMU driver, which provides description of available events and configuration options in sysfs, see /sys/bus/event_source/devices/dwc_rootport_{sbdf}.”…””}”(hjyh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K8hj2h²hubhÝ)”}”(hXThe "format" directory describes format of the config fields of the perf_event_attr structure. The "events" directory provides configuration templates for all documented events. For example, "rx_pcie_tlp_data_payload" is an equivalent of "eventid=0x21,type=0x0".”h]”hXThe “format†directory describes format of the config fields of the perf_event_attr structure. The “events†directory provides configuration templates for all documented events. For example, “rx_pcie_tlp_data_payload†is an equivalent of “eventid=0x21,type=0x0â€.”…””}”(hj‡h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/ [Kernel PMU event] <...> dwc_rootport_13018/rx_memory_read,lane=?/ [Kernel PMU event]”h]”hŒ¾$# perf list | grep dwc_rootport <...> dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/ [Kernel PMU event] <...> dwc_rootport_13018/rx_memory_read,lane=?/ [Kernel PMU event]”…””}”hj¥sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1j£h³hÊh´KChj2h²hubh¶)”}”(hhh]”(h»)”}”(hŒTime Based Analysis Event Usage”h]”hŒTime Based Analysis Event Usage”…””}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjµh²hh³hÊh´KJubhÝ)”}”(hŒEExample usage of counting PCIe RX TLP data payload (Units of bytes)::”h]”hŒDExample usage of counting PCIe RX TLP data payload (Units of bytes):”…””}”(hjÆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KLhjµh²hubj¤)”}”(hŒ?$# perf stat -a -e dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/”h]”hŒ?$# perf stat -a -e dwc_rootport_13018/Rx_PCIe_TLP_Data_Payload/”…””}”hjÔsbah}”(h]”h ]”h"]”h$]”h&]”j³j´uh1j£h³hÊh´KNhjµh²hubhÝ)”}”(hŒJThe average RX/TX bandwidth can be calculated using the following formula:”h]”hŒJThe average RX/TX bandwidth can be calculated using the following formula:”…””}”(hjâh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KPhjµh²hubjR)”}”(hŒ†PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window ”h]”hÝ)”}”(hŒ…PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window”h]”hŒ…PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window”…””}”(hjôh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KRhjðubah}”(h]”h ]”h"]”h$]”h&]”uh1jQh³hÊh´KRhjµh²hubeh}”(h]”Œtime-based-analysis-event-usage”ah ]”h"]”Œtime based analysis event usage”ah$]”h&]”uh1hµhj2h²hh³hÊh´KJubh¶)”}”(hhh]”(h»)”}”(hŒLane Event Usage”h]”hŒLane Event Usage”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjh²hh³hÊh´KVubhÝ)”}”(hŒŽEach lane has the same event set and to avoid generating a list of hundreds of events, the user need to specify the lane ID explicitly, e.g.::”h]”hŒEach lane has the same event set and to avoid generating a list of hundreds of events, the user need to specify the lane ID explicitly, e.g.:”…””}”(hj!h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KXhjh²hubj¤)”}”(hŒ<$# perf stat -a -e dwc_rootport_13018/rx_memory_read,lane=4/”h]”hŒ<$# perf stat -a -e dwc_rootport_13018/rx_memory_read,lane=4/”…””}”hj/sbah}”(h]”h ]”h"]”h$]”h&]”j³j´uh1j£h³hÊh´K[hjh²hubhÝ)”}”(hŒ…The driver does not support sampling, therefore "perf record" will not work. Per-task (without "-a") perf sessions are not supported.”h]”hŒThe driver does not support sampling, therefore “perf record†will not work. Per-task (without “-aâ€) perf sessions are not supported.”…””}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K]hjh²hubeh}”(h]”Œlane-event-usage”ah ]”h"]”Œlane event usage”ah$]”h&]”uh1hµhj2h²hh³hÊh´KVubeh}”(h]”Œ$designware-cores-dwc-pcie-pmu-driver”ah ]”h"]”Œ&designware cores (dwc) pcie pmu driver”ah$]”h&]”uh1hµhh·h²hh³hÊh´K/ubeh}”(h]”ŒBsynopsys-designware-cores-dwc-pcie-performance-monitoring-unit-pmu”ah ]”h"]”ŒFsynopsys designware cores (dwc) pcie performance monitoring unit (pmu)”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j†Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j`j]j/j,j£j j'j$jXjUj j jPjMuŒ nametypes”}”(j`‰j/‰j£‰j'‰jX‰j ‰jP‰uh}”(j]h·j,hËj jGj$j¦jUj2j jµjMjuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.