€•z<      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ0/translations/zh_CN/admin-guide/perf/alibaba_pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/zh_TW/admin-guide/perf/alibaba_pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/it_IT/admin-guide/perf/alibaba_pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ja_JP/admin-guide/perf/alibaba_pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ko_KR/admin-guide/perf/alibaba_pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/sp_SP/admin-guide/perf/alibaba_pmu”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ=Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)”h]”hŒ?Alibabaâ€™s T-Head SoC Uncore Performance Monitoring Unit (PMU)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒJ/var/lib/git/docbuild/linux/Documentation/admin-guide/perf/alibaba_pmu.rst”h KubhŒ	paragraph”“”)”}”(hŒ³The Yitian 710, custom-built by Alibaba Group's chip development business,
T-Head, implements uncore PMU for performance and functional debugging to
facilitate system maintenance.”h]”hŒµThe Yitian 710, custom-built by Alibaba Groupâ€™s chip development business,
T-Head, implements uncore PMU for performance and functional debugging to
facilitate system maintenance.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒ(DDR Sub-System Driveway (DRW) PMU Driver”h]”hŒ(DDR Sub-System Driveway (DRW) PMU Driver”…””}”(hhÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhÇhžhhŸh¶h K
ubh¸)”}”(hX<  Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
is independent of others to service system memory requests. And one DDR5
channel is split into two independent sub-channels. The DDR Sub-System Driveway
implements separate PMUs for each sub-channel to monitor various performance
metrics.”h]”hX<  Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
is independent of others to service system memory requests. And one DDR5
channel is split into two independent sub-channels. The DDR Sub-System Driveway
implements separate PMUs for each sub-channel to monitor various performance
metrics.”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubh¸)”}”(hX  The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
sub-channels of the same channel in die 0. And the PMU device of die 1 is
prefixed with ali_drw_400XXXXX, e.g. ali_drw_40021000.”h]”hX  The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
sub-channels of the same channel in die 0. And the PMU device of die 1 is
prefixed with ali_drw_400XXXXX, e.g. ali_drw_40021000.”…””}”(hhæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubh¸)”}”(hŒTEach sub-channel has 36 PMU counters in total, which is classified into
four groups:”h]”hŒTEach sub-channel has 36 PMU counters in total, which is classified into
four groups:”…””}”(hhôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ¤Group 0: PMU Cycle Counter. This group has one pair of counters
pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
based on DDRC core clock.
”h]”h¸)”}”(hŒ£Group 0: PMU Cycle Counter. This group has one pair of counters
pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
based on DDRC core clock.”h]”hŒ£Group 0: PMU Cycle Counter. This group has one pair of counters
pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
based on DDRC core clock.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  hžhhŸh¶h Nubj  )”}”(hŒïGroup 1: PMU Bandwidth Counters. This group has 8 counters that are used
to count the total access number of either the eight bank groups in a
selected rank, or four ranks separately in the first 4 counters. The base
transfer unit is 64B.
”h]”h¸)”}”(hŒîGroup 1: PMU Bandwidth Counters. This group has 8 counters that are used
to count the total access number of either the eight bank groups in a
selected rank, or four ranks separately in the first 4 counters. The base
transfer unit is 64B.”h]”hŒîGroup 1: PMU Bandwidth Counters. This group has 8 counters that are used
to count the total access number of either the eight bank groups in a
selected rank, or four ranks separately in the first 4 counters. The base
transfer unit is 64B.”…””}”(hj%  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj!  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  hžhhŸh¶h Nubj  )”}”(hŒŠGroup 2: PMU Retry Counters. This group has 10 counters, that intend to
count the total retry number of each type of uncorrectable error.
”h]”h¸)”}”(hŒ‰Group 2: PMU Retry Counters. This group has 10 counters, that intend to
count the total retry number of each type of uncorrectable error.”h]”hŒ‰Group 2: PMU Retry Counters. This group has 10 counters, that intend to
count the total retry number of each type of uncorrectable error.”…””}”(hj=  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K#hj9  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  hžhhŸh¶h Nubj  )”}”(hŒdGroup 3: PMU Common Counters. This group has 16 counters, that are used
to count the common events.
”h]”h¸)”}”(hŒcGroup 3: PMU Common Counters. This group has 16 counters, that are used
to count the common events.”h]”hŒcGroup 3: PMU Common Counters. This group has 16 counters, that are used
to count the common events.”…””}”(hjU  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K&hjQ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j  hŸh¶h KhhÇhžhubh¸)”}”(hŒKFor now, the Driveway PMU driver only uses counters in group 0 and group 3.”h]”hŒKFor now, the Driveway PMU driver only uses counters in group 0 and group 3.”…””}”(hjq  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K)hhÇhžhubh¸)”}”(hX  The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
for connecting an SoC application bus to DDR memory devices. The DDRCTL
receives transactions Host Interface (HIF) which is custom-defined by Synopsys.
These transactions are queued internally and scheduled for access while
satisfying the SDRAM protocol timing requirements, transaction priorities, and
dependencies between the transactions. The DDRCTL in turn issues commands on
the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
to and from the SDRAM. The driveway PMUs have hardware logic to gather
statistics and performance logging signals on HIF, DFI, etc.”h]”hX  The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
for connecting an SoC application bus to DDR memory devices. The DDRCTL
receives transactions Host Interface (HIF) which is custom-defined by Synopsys.
These transactions are queued internally and scheduled for access while
satisfying the SDRAM protocol timing requirements, transaction priorities, and
dependencies between the transactions. The DDRCTL in turn issues commands on
the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
to and from the SDRAM. The driveway PMUs have hardware logic to gather
statistics and performance logging signals on HIF, DFI, etc.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K+hhÇhžhubh¸)”}”(hŒ¬By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
interface, we could calculate the bandwidth. Example usage of counting memory
data bandwidth::”h]”hŒ«By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
interface, we could calculate the bandwidth. Example usage of counting memory
data bandwidth:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K5hhÇhžhubhŒliteral_block”“”)”}”(hXµ  perf stat \
  -e ali_drw_21000/hif_wr/ \
  -e ali_drw_21000/hif_rd/ \
  -e ali_drw_21000/hif_rmw/ \
  -e ali_drw_21000/cycle/ \
  -e ali_drw_21080/hif_wr/ \
  -e ali_drw_21080/hif_rd/ \
  -e ali_drw_21080/hif_rmw/ \
  -e ali_drw_21080/cycle/ \
  -e ali_drw_23000/hif_wr/ \
  -e ali_drw_23000/hif_rd/ \
  -e ali_drw_23000/hif_rmw/ \
  -e ali_drw_23000/cycle/ \
  -e ali_drw_23080/hif_wr/ \
  -e ali_drw_23080/hif_rd/ \
  -e ali_drw_23080/hif_rmw/ \
  -e ali_drw_23080/cycle/ \
  -e ali_drw_25000/hif_wr/ \
  -e ali_drw_25000/hif_rd/ \
  -e ali_drw_25000/hif_rmw/ \
  -e ali_drw_25000/cycle/ \
  -e ali_drw_25080/hif_wr/ \
  -e ali_drw_25080/hif_rd/ \
  -e ali_drw_25080/hif_rmw/ \
  -e ali_drw_25080/cycle/ \
  -e ali_drw_27000/hif_wr/ \
  -e ali_drw_27000/hif_rd/ \
  -e ali_drw_27000/hif_rmw/ \
  -e ali_drw_27000/cycle/ \
  -e ali_drw_27080/hif_wr/ \
  -e ali_drw_27080/hif_rd/ \
  -e ali_drw_27080/hif_rmw/ \
  -e ali_drw_27080/cycle/ -- sleep 10”h]”hXµ  perf stat \
  -e ali_drw_21000/hif_wr/ \
  -e ali_drw_21000/hif_rd/ \
  -e ali_drw_21000/hif_rmw/ \
  -e ali_drw_21000/cycle/ \
  -e ali_drw_21080/hif_wr/ \
  -e ali_drw_21080/hif_rd/ \
  -e ali_drw_21080/hif_rmw/ \
  -e ali_drw_21080/cycle/ \
  -e ali_drw_23000/hif_wr/ \
  -e ali_drw_23000/hif_rd/ \
  -e ali_drw_23000/hif_rmw/ \
  -e ali_drw_23000/cycle/ \
  -e ali_drw_23080/hif_wr/ \
  -e ali_drw_23080/hif_rd/ \
  -e ali_drw_23080/hif_rmw/ \
  -e ali_drw_23080/cycle/ \
  -e ali_drw_25000/hif_wr/ \
  -e ali_drw_25000/hif_rd/ \
  -e ali_drw_25000/hif_rmw/ \
  -e ali_drw_25000/cycle/ \
  -e ali_drw_25080/hif_wr/ \
  -e ali_drw_25080/hif_rd/ \
  -e ali_drw_25080/hif_rmw/ \
  -e ali_drw_25080/cycle/ \
  -e ali_drw_27000/hif_wr/ \
  -e ali_drw_27000/hif_rd/ \
  -e ali_drw_27000/hif_rmw/ \
  -e ali_drw_27000/cycle/ \
  -e ali_drw_27080/hif_wr/ \
  -e ali_drw_27080/hif_rd/ \
  -e ali_drw_27080/hif_rmw/ \
  -e ali_drw_27080/cycle/ -- sleep 10”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1j›  hŸh¶h K9hhÇhžhubh¸)”}”(hŒEExample usage of counting all memory read/write bandwidth by metric::”h]”hŒDExample usage of counting all memory read/write bandwidth by metric:”…””}”(hj­  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K[hhÇhžhubjœ  )”}”(hŒ`perf stat -M ddr_read_bandwidth.all -- sleep 10
perf stat -M ddr_write_bandwidth.all -- sleep 10”h]”hŒ`perf stat -M ddr_read_bandwidth.all -- sleep 10
perf stat -M ddr_write_bandwidth.all -- sleep 10”…””}”hj»  sbah}”(h]”h ]”h"]”h$]”h&]”j«  j¬  uh1j›  hŸh¶h K]hhÇhžhubh¸)”}”(hŒ8The average DRAM bandwidth can be calculated as follows:”h]”hŒ8The average DRAM bandwidth can be calculated as follows:”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K`hhÇhžhubj  )”}”(hhh]”(j  )”}”(hŒCRead Bandwidth =  perf_hif_rd * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle”h]”h¸)”}”(hjÜ  h]”hŒCRead Bandwidth =  perf_hif_rd * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle”…””}”(hjÞ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KbhjÚ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj×  hžhhŸh¶h Nubj  )”}”(hŒUWrite Bandwidth = (perf_hif_wr + perf_hif_rmw) * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle
”h]”h¸)”}”(hŒTWrite Bandwidth = (perf_hif_wr + perf_hif_rmw) * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle”h]”hŒTWrite Bandwidth = (perf_hif_wr + perf_hif_rmw) * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle”…””}”(hjõ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kchjñ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj×  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jo  jp  uh1j  hŸh¶h KbhhÇhžhubh¸)”}”(hŒHere, DDRC_WIDTH = 64 bytes.”h]”hŒHere, DDRC_WIDTH = 64 bytes.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KehhÇhžhubh¸)”}”(hŒ’The current driver does not support sampling. So "perf record" is
unsupported.  Also attach to a task is unsupported as the events are all
uncore.”h]”hŒ–The current driver does not support sampling. So â€œperf recordâ€ is
unsupported.  Also attach to a task is unsupported as the events are all
uncore.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KghhÇhžhubeh}”(h]”Œ&ddr-sub-system-driveway-drw-pmu-driver”ah ]”h"]”Œ(ddr sub-system driveway (drw) pmu driver”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K
ubeh}”(h]”Œ;alibaba-s-t-head-soc-uncore-performance-monitoring-unit-pmu”ah ]”h"]”Œ=alibaba's t-head soc uncore performance monitoring unit (pmu)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j^  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j8  j5  j0  j-  uŒ	nametypes”}”(j8  ‰j0  ‰uh}”(j5  h£j-  hÇuŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.