sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/admin-guide/media/mgb4modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/admin-guide/media/mgb4.rsthKubhsection)}(hhh](htitle)}(hThe mgb4 driverh]hThe mgb4 driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hsysfs interfaceh]hsysfs interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe mgb4 driver provides a sysfs interface, that is used to configure video stream related parameters (some of them must be set properly before the v4l2 device can be opened) and obtain the video device/stream status.h]hThe mgb4 driver provides a sysfs interface, that is used to configure video stream related parameters (some of them must be set properly before the v4l2 device can be opened) and obtain the video device/stream status.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hThere are two types of parameters - global / PCI card related, found under ``/sys/class/video4linux/videoX/device`` and module specific found under ``/sys/class/video4linux/videoX``.h](hKThere are two types of parameters - global / PCI card related, found under }(hhhhhNhNubhliteral)}(h(``/sys/class/video4linux/videoX/device``h]h$/sys/class/video4linux/videoX/device}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh! and module specific found under }(hhhhhNhNubh)}(h!``/sys/class/video4linux/videoX``h]h/sys/class/video4linux/videoX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hGlobal (PCI card) parametersh]hGlobal (PCI card) parameters}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubhdefinition_list)}(hhh](hdefinition_list_item)}(h**module_type** (R): Module type. | 0 - No module present | 1 - FPDL3 | 2 - GMSL (one serializer, two daisy chained deserializers) | 3 - GMSL (one serializer, two deserializers) | 4 - GMSL (two deserializers with two daisy chain outputs) h](hterm)}(h**module_type** (R):h](hstrong)}(h**module_type**h]h module_type}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj<ubh (R):}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj6ubh definition)}(hhh](h)}(h Module type.h]h Module type.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\ubh line_block)}(hhh](hh)}(h0 - No module presenth]h0 - No module present}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjohhhKubjr)}(h 1 - FPDL3h]h 1 - FPDL3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjohhhKubjr)}(h:2 - GMSL (one serializer, two daisy chained deserializers)h]h:2 - GMSL (one serializer, two daisy chained deserializers)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjohhhKubjr)}(h,3 - GMSL (one serializer, two deserializers)h]h,3 - GMSL (one serializer, two deserializers)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjohhhKubjr)}(h94 - GMSL (two deserializers with two daisy chain outputs)h]h94 - GMSL (two deserializers with two daisy chain outputs)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjohhhKubeh}(h]h ]h"]h$]h&]uh1jmhj\ubeh}(h]h ]h"]h$]h&]uh1jZhj6ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj1ubj5)}(hQ**module_version** (R): Module version number. Zero in case of a missing module. h](j;)}(h**module_version** (R):h](jA)}(h**module_version**h]hmodule_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjubj[)}(hhh]h)}(h8Module version number. Zero in case of a missing module.h]h8Module version number. Zero in case of a missing module.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj1hhubj5)}(h8**fw_type** (R): Firmware type. | 1 - FPDL3 | 2 - GMSL h](j;)}(h**fw_type** (R):h](jA)}(h **fw_type**h]hfw_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK$hj ubj[)}(hhh](h)}(hFirmware type.h]hFirmware type.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hj)ubjn)}(hhh](jr)}(h 1 - FPDL3h]h 1 - FPDL3}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj:hhhKubjr)}(h2 - GMSLh]h2 - GMSL}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj:hhhKubeh}(h]h ]h"]h$]h&]uh1jmhj)ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhK$hj1hhubj5)}(h-**fw_version** (R): Firmware version number. h](j;)}(h**fw_version** (R):h](jA)}(h**fw_version**h]h fw_version}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjoubh (R):}(hjohhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK'hjkubj[)}(hhh]h)}(hFirmware version number.h]hFirmware version number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jZhjkubeh}(h]h ]h"]h$]h&]uh1j4hhhK'hj1hhubj5)}(h**serial_number** (R): Card serial number. The format is:: PRODUCT-REVISION-SERIES-SERIAL where each component is a 8b number. h](j;)}(h**serial_number** (R):h](jA)}(h**serial_number**h]h serial_number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK.hjubj[)}(hhh](h)}(h#Card serial number. The format is::h]h"Card serial number. The format is:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubh literal_block)}(hPRODUCT-REVISION-SERIES-SERIALh]hPRODUCT-REVISION-SERIES-SERIAL}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK,hjubh)}(h$where each component is a 8b number.h]h$where each component is a 8b number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhK.hj1hhubeh}(h]h ]h"]h$]h&]uh1j/hjhhhhhNubeh}(h]global-pci-card-parametersah ]h"]global (pci card) parametersah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h"Common FPDL3/GMSL input parametersh]h"Common FPDL3/GMSL input parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK1ubj0)}(hhh](j5)}(h/**input_id** (R): Input number ID, zero based. h](j;)}(h**input_id** (R):h](jA)}(h **input_id**h]hinput_id}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj)ubh (R):}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK4hj%ubj[)}(hhh]h)}(hInput number ID, zero based.h]hInput number ID, zero based.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjEubah}(h]h ]h"]h$]h&]uh1jZhj%ubeh}(h]h ]h"]h$]h&]uh1j4hhhK4hj"ubj5)}(hb**oldi_lane_width** (RW): Number of deserializer output lanes. | 0 - single | 1 - dual (default) h](j;)}(h**oldi_lane_width** (RW):h](jA)}(h**oldi_lane_width**h]holdi_lane_width}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjfubh (RW):}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK:hjbubj[)}(hhh](h)}(h$Number of deserializer output lanes.h]h$Number of deserializer output lanes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubjn)}(hhh](jr)}(h 0 - singleh]h 0 - single}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h1 - dual (default)h]h1 - dual (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjbubeh}(h]h ]h"]h$]h&]uh1j4hhhK:hj"hhubj5)}(h**color_mapping** (RW): Mapping of the incoming bits in the signal to the colour bits of the pixels. | 0 - OLDI/JEIDA | 1 - SPWG/VESA (default) h](j;)}(h**color_mapping** (RW):h](jA)}(h**color_mapping**h]h color_mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK@hjubj[)}(hhh](h)}(hLMapping of the incoming bits in the signal to the colour bits of the pixels.h]hLMapping of the incoming bits in the signal to the colour bits of the pixels.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubjn)}(hhh](jr)}(h0 - OLDI/JEIDAh]h0 - OLDI/JEIDA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h1 - SPWG/VESA (default)h]h1 - SPWG/VESA (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhK@hj"hhubj5)}(hXG**link_status** (R): Video link status. If the link is locked, chips are properly connected and communicating at the same speed and protocol. The link can be locked without an active video stream. A value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2 VIDIOC_ENUMINPUT status bits. | 0 - unlocked | 1 - locked h](j;)}(h**link_status** (R):h](jA)}(h**link_status**h]h link_status}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj*ubh (R):}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKKhj&ubj[)}(hhh](h)}(hVideo link status. If the link is locked, chips are properly connected and communicating at the same speed and protocol. The link can be locked without an active video stream.h]hVideo link status. If the link is locked, chips are properly connected and communicating at the same speed and protocol. The link can be locked without an active video stream.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjFubh)}(hcA value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2 VIDIOC_ENUMINPUT status bits.h]hcA value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2 VIDIOC_ENUMINPUT status bits.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjFubjn)}(hhh](jr)}(h 0 - unlockedh]h 0 - unlocked}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjehhhKubjr)}(h 1 - lockedh]h 1 - locked}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjehhhKubeh}(h]h ]h"]h$]h&]uh1jmhjFubeh}(h]h ]h"]h$]h&]uh1jZhj&ubeh}(h]h ]h"]h$]h&]uh1j4hhhKKhj"hhubj5)}(hX **stream_status** (R): Video stream status. A stream is detected if the link is locked, the input pixel clock is running and the DE signal is moving. A value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2 VIDIOC_ENUMINPUT status bits. | 0 - not detected | 1 - detected h](j;)}(h**stream_status** (R):h](jA)}(h**stream_status**h]h stream_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKUhjubj[)}(hhh](h)}(h~Video stream status. A stream is detected if the link is locked, the input pixel clock is running and the DE signal is moving.h]h~Video stream status. A stream is detected if the link is locked, the input pixel clock is running and the DE signal is moving.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubh)}(heA value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2 VIDIOC_ENUMINPUT status bits.h]heA value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2 VIDIOC_ENUMINPUT status bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubjn)}(hhh](jr)}(h0 - not detectedh]h0 - not detected}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h 1 - detectedh]h 1 - detected}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKUhj"hhubj5)}(h**video_width** (R): Video stream width. This is the actual width as detected by the HW. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width field of the v4l2_bt_timings struct. h](j;)}(h**video_width** (R):h](jA)}(h**video_width**h]h video_width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK[hjubj[)}(hhh](h)}(hCVideo stream width. This is the actual width as detected by the HW.h]hCVideo stream width. This is the actual width as detected by the HW.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj&ubh)}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width field of the v4l2_bt_timings struct.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhj&ubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhK[hj"hhubj5)}(h**video_height** (R): Video stream height. This is the actual height as detected by the HW. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height field of the v4l2_bt_timings struct. h](j;)}(h**video_height** (R):h](jA)}(h**video_height**h]h video_height}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjUubh (R):}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKahjQubj[)}(hhh](h)}(hEVideo stream height. This is the actual height as detected by the HW.h]hEVideo stream height. This is the actual height as detected by the HW.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjqubh)}(hqThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height field of the v4l2_bt_timings struct.h]hqThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height field of the v4l2_bt_timings struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjqubeh}(h]h ]h"]h$]h&]uh1jZhjQubeh}(h]h ]h"]h$]h&]uh1j4hhhKahj"hhubj5)}(hX**vsync_status** (R): The type of VSYNC pulses as detected by the video format detector. The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct. | 0 - active low | 1 - active high | 2 - not available h](j;)}(h**vsync_status** (R):h](jA)}(h**vsync_status**h]h vsync_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKkhjubj[)}(hhh](h)}(hBThe type of VSYNC pulses as detected by the video format detector.h]hBThe type of VSYNC pulses as detected by the video format detector.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubh)}(hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.h]hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjubjn)}(hhh](jr)}(h0 - active lowh]h0 - active low}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h1 - active highh]h1 - active high}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h2 - not availableh]h2 - not available}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKkhj"hhubj5)}(hX**hsync_status** (R): The type of HSYNC pulses as detected by the video format detector. The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct. | 0 - active low | 1 - active high | 2 - not available h](j;)}(h**hsync_status** (R):h](jA)}(h**hsync_status**h]h hsync_status}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKuhjubj[)}(hhh](h)}(hBThe type of HSYNC pulses as detected by the video format detector.h]hBThe type of HSYNC pulses as detected by the video format detector.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhj:ubh)}(hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.h]hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphj:ubjn)}(hhh](jr)}(h0 - active lowh]h0 - active low}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjYhhhKubjr)}(h1 - active highh]h1 - active high}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjYhhhKubjr)}(h2 - not availableh]h2 - not available}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjYhhhKubeh}(h]h ]h"]h$]h&]uh1jmhj:ubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKuhj"hhubj5)}(hXU**vsync_gap_length** (RW): If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal VSYNC pulse. h](j;)}(h**vsync_gap_length** (RW):h](jA)}(h**vsync_gap_length**h]hvsync_gap_length}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhK|hjubj[)}(hhh]h)}(hX9If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal VSYNC pulse.h]hX=If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many “empty” pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal VSYNC pulse.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhK|hj"hhubj5)}(hX**hsync_gap_length** (RW): If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal HSYNC pulse. The value must be greater than 1 and smaller than vsync_gap_length. h](j;)}(h**hsync_gap_length** (RW):h](jA)}(h**hsync_gap_length**h]hhsync_gap_length}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjubj[)}(hhh]h)}(hX}If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal HSYNC pulse. The value must be greater than 1 and smaller than vsync_gap_length.h]hXIf the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many “empty” pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal HSYNC pulse. The value must be greater than 1 and smaller than vsync_gap_length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(hX**pclk_frequency** (R): Input pixel clock frequency in kHz. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the pixelclock field of the v4l2_bt_timings struct. *Note: The frequency_range parameter must be set properly first to get a valid frequency here.* h](j;)}(h**pclk_frequency** (R):h](jA)}(h**pclk_frequency**h]hpclk_frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjubj[)}(hhh](h)}(h#Input pixel clock frequency in kHz.h]h#Input pixel clock frequency in kHz.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubh)}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the pixelclock field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the pixelclock field of the v4l2_bt_timings struct.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubh)}(h_*Note: The frequency_range parameter must be set properly first to get a valid frequency here.*h]hemphasis)}(hjSh]h]Note: The frequency_range parameter must be set properly first to get a valid frequency here.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjQubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(h**hsync_width** (R): Width of the HSYNC signal in PCLK clock ticks. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hsync field of the v4l2_bt_timings struct. h](j;)}(h**hsync_width** (R):h](jA)}(h**hsync_width**h]h hsync_width}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjzubh (R):}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjvubj[)}(hhh](h)}(h.Width of the HSYNC signal in PCLK clock ticks.h]h.Width of the HSYNC signal in PCLK clock ticks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hsync field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hsync field of the v4l2_bt_timings struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jZhjvubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(h**vsync_width** (R): Width of the VSYNC signal in PCLK clock ticks. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vsync field of the v4l2_bt_timings struct. h](j;)}(h**vsync_width** (R):h](jA)}(h**vsync_width**h]h vsync_width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjubj[)}(hhh](h)}(h.Width of the VSYNC signal in PCLK clock ticks.h]h.Width of the VSYNC signal in PCLK clock ticks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vsync field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vsync field of the v4l2_bt_timings struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(hX**hback_porch** (R): Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hbackporch field of the v4l2_bt_timings struct. h](j;)}(h**hback_porch** (R):h](jA)}(h**hback_porch**h]h hback_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh](h)}(h{Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1).h]h{Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1).}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj,ubh)}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hbackporch field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hbackporch field of the v4l2_bt_timings struct.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj,ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(hX**hfront_porch** (R): Number of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hfrontporch field of the v4l2_bt_timings struct. h](j;)}(h**hfront_porch** (R):h](jA)}(h**hfront_porch**h]h hfront_porch}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj[ubh (R):}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjWubj[)}(hhh](h)}(hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal.h]hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjwubh)}(hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hfrontporch field of the v4l2_bt_timings struct.h]hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hfrontporch field of the v4l2_bt_timings struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjwubeh}(h]h ]h"]h$]h&]uh1jZhjWubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(hX **vback_porch** (R): Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vbackporch field of the v4l2_bt_timings struct. h](j;)}(h**vback_porch** (R):h](jA)}(h**vback_porch**h]h vback_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjubj[)}(hhh](h)}(h}Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1).h]h}Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vbackporch field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vbackporch field of the v4l2_bt_timings struct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(hX**vfront_porch** (R): Number of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vfrontporch field of the v4l2_bt_timings struct. h](j;)}(h**vfront_porch** (R):h](jA)}(h**vfront_porch**h]h vfront_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjubj[)}(hhh](h)}(hvNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal.h]hvNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vfrontporch field of the v4l2_bt_timings struct.h]hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vfrontporch field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubj5)}(hX~**frequency_range** (RW) PLL frequency range of the OLDI input clock generator. The PLL frequency is derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to "dual". | 0 - PLL < 50MHz (default) | 1 - PLL >= 50MHz *Note: This parameter can not be changed while the input v4l2 device is open.* h](j;)}(h**frequency_range** (RW)h](jA)}(h**frequency_range**h]hfrequency_range}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj< ubh (RW)}(hj< hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj8 ubj[)}(hhh](h)}(hPLL frequency range of the OLDI input clock generator. The PLL frequency is derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to "dual".h]hPLL frequency range of the OLDI input clock generator. The PLL frequency is derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if oldi_lane_width is set to “single” and PCLK/2 if oldi_lane_width is set to “dual”.}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjX ubjn)}(hhh](jr)}(h0 - PLL < 50MHz (default)h]h0 - PLL < 50MHz (default)}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhji hhhKubjr)}(h1 - PLL >= 50MHzh]h1 - PLL >= 50MHz}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhji hhhKubeh}(h]h ]h"]h$]h&]uh1jmhjX ubh)}(hN*Note: This parameter can not be changed while the input v4l2 device is open.*h]jV)}(hj h]hLNote: This parameter can not be changed while the input v4l2 device is open.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhjX ubeh}(h]h ]h"]h$]h&]uh1jZhj8 ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj"hhubeh}(h]h ]h"]h$]h&]uh1j/hjhhhhhNubeh}(h]"common-fpdl3-gmsl-input-parametersah ]h"]"common fpdl3/gmsl input parametersah$]h&]uh1hhhhhhhhK1ubh)}(hhh](h)}(h#Common FPDL3/GMSL output parametersh]h#Common FPDL3/GMSL output parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubj0)}(hhh](j5)}(h1**output_id** (R): Output number ID, zero based. h](j;)}(h**output_id** (R):h](jA)}(h **output_id**h]h output_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh]h)}(hOutput number ID, zero based.h]hOutput number ID, zero based.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj ubj5)}(hX**video_source** (RW): Output video source. If set to 0 or 1, the source is the corresponding card input and the v4l2 output devices are disabled. If set to 2 or 3, the source is the corresponding v4l2 video output device. The default is the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2. | 0 - input 0 | 1 - input 1 | 2 - v4l2 output 0 | 3 - v4l2 output 1 *Note: This parameter can not be changed while ANY of the input/output v4l2 devices is open.* h](j;)}(h**video_source** (RW):h](jA)}(h**video_source**h]h video_source}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh](h)}(hXOutput video source. If set to 0 or 1, the source is the corresponding card input and the v4l2 output devices are disabled. If set to 2 or 3, the source is the corresponding v4l2 video output device. The default is the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.h]hXOutput video source. If set to 0 or 1, the source is the corresponding card input and the v4l2 output devices are disabled. If set to 2 or 3, the source is the corresponding v4l2 video output device. The default is the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj0 ubjn)}(hhh](jr)}(h 0 - input 0h]h 0 - input 0}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjA hhhKubjr)}(h 1 - input 1h]h 1 - input 1}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjA hhhKubjr)}(h2 - v4l2 output 0h]h2 - v4l2 output 0}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjA hhhKubjr)}(h3 - v4l2 output 1h]h3 - v4l2 output 1}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjA hhhKubeh}(h]h ]h"]h$]h&]uh1jmhj0 ubh)}(h]*Note: This parameter can not be changed while ANY of the input/output v4l2 devices is open.*h]jV)}(hj h]h[Note: This parameter can not be changed while ANY of the input/output v4l2 devices is open.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj0 ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj hhubj5)}(hX**display_width** (RW): Display width. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default width is 1280. *Note: This parameter can not be changed while the output v4l2 device is open.* h](j;)}(h**display_width** (RW):h](jA)}(h**display_width**h]h display_width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh](h)}(hDisplay width. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default width is 1280.h]hDisplay width. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default width is 1280.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hO*Note: This parameter can not be changed while the output v4l2 device is open.*h]jV)}(hj h]hMNote: This parameter can not be changed while the output v4l2 device is open.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj hhubj5)}(hX**display_height** (RW): Display height. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default height is 640. *Note: This parameter can not be changed while the output v4l2 device is open.* h](j;)}(h**display_height** (RW):h](jA)}(h**display_height**h]hdisplay_height}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh](h)}(hDisplay height. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default height is 640.h]hDisplay height. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default height is 640.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hO*Note: This parameter can not be changed while the output v4l2 device is open.*h]jV)}(hj, h]hMNote: This parameter can not be changed while the output v4l2 device is open.}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj* ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj hhubj5)}(hX**frame_rate** (RW): Output video signal frame rate limit in frames per second. Due to the limited output pixel clock steps, the card can not always generate a frame rate perfectly matching the value required by the connected display. Using this parameter one can limit the frame rate by "crippling" the signal so that the lines are not equal (the porches of the last line differ) but the signal appears like having the exact frame rate to the connected display. The default frame rate limit is 60Hz. h](j;)}(h**frame_rate** (RW):h](jA)}(h**frame_rate**h]h frame_rate}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjQ ubh (RW):}(hjQ hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhjM ubj[)}(hhh]h)}(hXOutput video signal frame rate limit in frames per second. Due to the limited output pixel clock steps, the card can not always generate a frame rate perfectly matching the value required by the connected display. Using this parameter one can limit the frame rate by "crippling" the signal so that the lines are not equal (the porches of the last line differ) but the signal appears like having the exact frame rate to the connected display. The default frame rate limit is 60Hz.h]hXOutput video signal frame rate limit in frames per second. Due to the limited output pixel clock steps, the card can not always generate a frame rate perfectly matching the value required by the connected display. Using this parameter one can limit the frame rate by “crippling” the signal so that the lines are not equal (the porches of the last line differ) but the signal appears like having the exact frame rate to the connected display. The default frame rate limit is 60Hz.}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjm ubah}(h]h ]h"]h$]h&]uh1jZhjM ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj hhubj5)}(h^**hsync_polarity** (RW): HSYNC signal polarity. | 0 - active low (default) | 1 - active high h](j;)}(h**hsync_polarity** (RW):h](jA)}(h**hsync_polarity**h]hhsync_polarity}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh](h)}(hHSYNC signal polarity.h]hHSYNC signal polarity.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubjn)}(hhh](jr)}(h0 - active low (default)h]h0 - active low (default)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhKubjr)}(h1 - active highh]h1 - active high}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jmhj ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj hhubj5)}(h^**vsync_polarity** (RW): VSYNC signal polarity. | 0 - active low (default) | 1 - active high h](j;)}(h**vsync_polarity** (RW):h](jA)}(h**vsync_polarity**h]hvsync_polarity}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhKhj ubj[)}(hhh](h)}(hVSYNC signal polarity.h]hVSYNC signal polarity.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubjn)}(hhh](jr)}(h0 - active low (default)h]h0 - active low (default)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhKubjr)}(h1 - active highh]h1 - active high}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jmhj ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhKhj hhubj5)}(hX**de_polarity** (RW): DE signal polarity. | 0 - active low | 1 - active high (default) h](j;)}(h**de_polarity** (RW):h](jA)}(h**de_polarity**h]h de_polarity}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjR ubh (RW):}(hjR hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMhjN ubj[)}(hhh](h)}(hDE signal polarity.h]hDE signal polarity.}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjn ubjn)}(hhh](jr)}(h0 - active lowh]h0 - active low}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhKubjr)}(h1 - active high (default)h]h1 - active high (default)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jmhjn ubeh}(h]h ]h"]h$]h&]uh1jZhjN ubeh}(h]h ]h"]h$]h&]uh1j4hhhMhj hhubj5)}(hX**pclk_frequency** (RW): Output pixel clock frequency. Allowed values are between 25000-190000(kHz) and there is a non-linear stepping between two consecutive allowed frequencies. The driver finds the nearest allowed frequency to the given value and sets it. When reading this property, you get the exact frequency set by the driver. The default frequency is 61150kHz. *Note: This parameter can not be changed while the output v4l2 device is open.* h](j;)}(h**pclk_frequency** (RW):h](jA)}(h**pclk_frequency**h]hpclk_frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhM hj ubj[)}(hhh](h)}(hXWOutput pixel clock frequency. Allowed values are between 25000-190000(kHz) and there is a non-linear stepping between two consecutive allowed frequencies. The driver finds the nearest allowed frequency to the given value and sets it. When reading this property, you get the exact frequency set by the driver. The default frequency is 61150kHz.h]hXWOutput pixel clock frequency. Allowed values are between 25000-190000(kHz) and there is a non-linear stepping between two consecutive allowed frequencies. The driver finds the nearest allowed frequency to the given value and sets it. When reading this property, you get the exact frequency set by the driver. The default frequency is 61150kHz.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hO*Note: This parameter can not be changed while the output v4l2 device is open.*h]jV)}(hj h]hMNote: This parameter can not be changed while the output v4l2 device is open.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj ubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubeh}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhM hj hhubj5)}(hT**hsync_width** (RW): Width of the HSYNC signal in pixels. The default value is 40. h](j;)}(h**hsync_width** (RW):h](jA)}(h**hsync_width**h]h hsync_width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhM hj ubj[)}(hhh]h)}(h=Width of the HSYNC signal in pixels. The default value is 40.h]h=Width of the HSYNC signal in pixels. The default value is 40.}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj$ ubah}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhM hj hhubj5)}(hY**vsync_width** (RW): Width of the VSYNC signal in video lines. The default value is 20. h](j;)}(h**vsync_width** (RW):h](jA)}(h**vsync_width**h]h vsync_width}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjE ubh (RW):}(hjE hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMhjA ubj[)}(hhh]h)}(hBWidth of the VSYNC signal in video lines. The default value is 20.h]hBWidth of the VSYNC signal in video lines. The default value is 20.}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhja ubah}(h]h ]h"]h$]h&]uh1jZhjA ubeh}(h]h ]h"]h$]h&]uh1j4hhhMhj hhubj5)}(h**hback_porch** (RW): Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The default value is 50. h](j;)}(h**hback_porch** (RW):h](jA)}(h**hback_porch**h]h hback_porch}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMhj~ ubj[)}(hhh]h)}(hNumber of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The default value is 50.h]hNumber of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The default value is 50.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jZhj~ ubeh}(h]h ]h"]h$]h&]uh1j4hhhMhj hhubj5)}(h**hfront_porch** (RW): Number of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The default value is 50. h](j;)}(h**hfront_porch** (RW):h](jA)}(h**hfront_porch**h]h hfront_porch}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMhj ubj[)}(hhh]h)}(hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The default value is 50.h]hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The default value is 50.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhMhj hhubj5)}(h**vback_porch** (RW): Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The default value is 31. h](j;)}(h**vback_porch** (RW):h](jA)}(h**vback_porch**h]h vback_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMhj ubj[)}(hhh]h)}(hNumber of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The default value is 31.h]hNumber of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The default value is 31.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jZhj ubeh}(h]h ]h"]h$]h&]uh1j4hhhMhj hhubj5)}(h**vfront_porch** (RW): Number of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The default value is 30. h](j;)}(h**vfront_porch** (RW):h](jA)}(h**vfront_porch**h]h vfront_porch}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj9ubh (RW):}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhM!hj5ubj[)}(hhh]h)}(hNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The default value is 30.h]hNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The default value is 30.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjUubah}(h]h ]h"]h$]h&]uh1jZhj5ubeh}(h]h ]h"]h$]h&]uh1j4hhhM!hj hhubeh}(h]h ]h"]h$]h&]uh1j/hj hhhhhNubeh}(h]#common-fpdl3-gmsl-output-parametersah ]h"]#common fpdl3/gmsl output parametersah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hFPDL3 specific input parametersh]hFPDL3 specific input parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM$ubj0)}(hhh]j5)}(hn**fpdl3_input_width** (RW): Number of deserializer input lines. | 0 - auto (default) | 1 - single | 2 - dual h](j;)}(h**fpdl3_input_width** (RW):h](jA)}(h**fpdl3_input_width**h]hfpdl3_input_width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhM+hjubj[)}(hhh](h)}(h#Number of deserializer input lines.h]h#Number of deserializer input lines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjubjn)}(hhh](jr)}(h0 - auto (default)h]h0 - auto (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h 1 - singleh]h 1 - single}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h2 - dualh]h2 - dual}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhM+hjubah}(h]h ]h"]h$]h&]uh1j/hjhhhhhNubeh}(h]fpdl3-specific-input-parametersah ]h"]fpdl3 specific input parametersah$]h&]uh1hhhhhhhhM$ubh)}(hhh](h)}(h FPDL3 specific output parametersh]h FPDL3 specific output parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM.ubj0)}(hhh]j5)}(hn**fpdl3_output_width** (RW): Number of serializer output lines. | 0 - auto (default) | 1 - single | 2 - dual h](j;)}(h**fpdl3_output_width** (RW):h](jA)}(h**fpdl3_output_width**h]hfpdl3_output_width}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj*ubh (RW):}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhM5hj&ubj[)}(hhh](h)}(h"Number of serializer output lines.h]h"Number of serializer output lines.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjFubjn)}(hhh](jr)}(h0 - auto (default)h]h0 - auto (default)}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjWhhhKubjr)}(h 1 - singleh]h 1 - single}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjWhhhKubjr)}(h2 - dualh]h2 - dual}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjWhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjFubeh}(h]h ]h"]h$]h&]uh1jZhj&ubeh}(h]h ]h"]h$]h&]uh1j4hhhM5hj#ubah}(h]h ]h"]h$]h&]uh1j/hjhhhhhNubeh}(h] fpdl3-specific-output-parametersah ]h"] fpdl3 specific output parametersah$]h&]uh1hhhhhhhhM.ubh)}(hhh](h)}(hGMSL specific input parametersh]hGMSL specific input parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM8ubj0)}(hhh](j5)}(hc**gmsl_mode** (RW): GMSL speed mode. | 0 - 12Gb/s (default) | 1 - 6Gb/s | 2 - 3Gb/s | 3 - 1.5Gb/s h](j;)}(h**gmsl_mode** (RW):h](jA)}(h **gmsl_mode**h]h gmsl_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhM@hjubj[)}(hhh](h)}(hGMSL speed mode.h]hGMSL speed mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubjn)}(hhh](jr)}(h0 - 12Gb/s (default)h]h0 - 12Gb/s (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h 1 - 6Gb/sh]h 1 - 6Gb/s}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h 2 - 3Gb/sh]h 2 - 3Gb/s}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h 3 - 1.5Gb/sh]h 3 - 1.5Gb/s}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhM@hjubj5)}(hX3**gmsl_stream_id** (RW): The GMSL multi-stream contains up to four video streams. This parameter selects which stream is captured by the video input. The value is the zero-based index of the stream. The default stream id is 0. *Note: This parameter can not be changed while the input v4l2 device is open.* h](j;)}(h**gmsl_stream_id** (RW):h](jA)}(h**gmsl_stream_id**h]hgmsl_stream_id}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj:ubh (RW):}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMHhj6ubj[)}(hhh](h)}(hThe GMSL multi-stream contains up to four video streams. This parameter selects which stream is captured by the video input. The value is the zero-based index of the stream. The default stream id is 0.h]hThe GMSL multi-stream contains up to four video streams. This parameter selects which stream is captured by the video input. The value is the zero-based index of the stream. The default stream id is 0.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjVubh)}(hN*Note: This parameter can not be changed while the input v4l2 device is open.*h]jV)}(hjih]hLNote: This parameter can not be changed while the input v4l2 device is open.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjgubah}(h]h ]h"]h$]h&]uh1hhhhMGhjVubeh}(h]h ]h"]h$]h&]uh1jZhj6ubeh}(h]h ]h"]h$]h&]uh1j4hhhMHhjhhubj5)}(h`**gmsl_fec** (RW): GMSL Forward Error Correction (FEC). | 0 - disabled | 1 - enabled (default) h](j;)}(h**gmsl_fec** (RW):h](jA)}(h **gmsl_fec**h]hgmsl_fec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMNhjubj[)}(hhh](h)}(h$GMSL Forward Error Correction (FEC).h]h$GMSL Forward Error Correction (FEC).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjubjn)}(hhh](jr)}(h 0 - disabledh]h 0 - disabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubjr)}(h1 - enabled (default)h]h1 - enabled (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhMNhjhhubeh}(h]h ]h"]h$]h&]uh1j/hjhhhhhNubeh}(h]gmsl-specific-input-parametersah ]h"]gmsl specific input parametersah$]h&]uh1hhhhhhhhM8ubeh}(h]sysfs-interfaceah ]h"]sysfs interfaceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMTD partitionsh]hMTD partitions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMQubj0)}(hhh]j5)}(hThe mgb4 driver creates a MTD device with two partitions: - mgb4-fw.X - FPGA firmware. - mgb4-data.X - Factory settings, e.g. card serial number. h](j;)}(h9The mgb4 driver creates a MTD device with two partitions:h]h9The mgb4 driver creates a MTD device with two partitions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j:hhhMUhjubj[)}(hhh]h bullet_list)}(hhh](h list_item)}(hmgb4-fw.X - FPGA firmware.h]h)}(hj4h]hmgb4-fw.X - FPGA firmware.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThj2ubah}(h]h ]h"]h$]h&]uh1j0hj-ubj1)}(h9mgb4-data.X - Factory settings, e.g. card serial number. h]h)}(h8mgb4-data.X - Factory settings, e.g. card serial number.h]h8mgb4-data.X - Factory settings, e.g. card serial number.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjIubah}(h]h ]h"]h$]h&]uh1j0hj-ubeh}(h]h ]h"]h$]h&]bullet-uh1j+hhhMThj(ubah}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhMUhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhNhNubh)}(hXThe *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is read-only. The *X* attached to the partition name represents the card number. Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may also have a third partition named *mgb4-flash* available in the system. This partition represents the whole, unpartitioned, card's FLASH memory and one should not fiddle with it...h](hThe }(hj{hhhNhNubjV)}(h *mgb4-fw*h]hmgb4-fw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubh3 partition is writable and is used for FW updates, }(hj{hhhNhNubjV)}(h *mgb4-data*h]h mgb4-data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubh is read-only. The }(hj{hhhNhNubjV)}(h*X*h]hX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubh attached to the partition name represents the card number. Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may also have a third partition named }(hj{hhhNhNubjV)}(h *mgb4-flash*h]h mgb4-flash}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhj{ubh available in the system. This partition represents the whole, unpartitioned, card’s FLASH memory and one should not fiddle with it...}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMWhjhhubeh}(h]mtd-partitionsah ]h"]mtd partitionsah$]h&]uh1hhhhhhhhMQubh)}(hhh](h)}(hIIO (triggers)h]hIIO (triggers)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM_ubh)}(hThe mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and signal level status capability. The following scan elements are available:h]hThe mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and signal level status capability. The following scan elements are available:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahjhhubj0)}(hhh](j5)}(h**activity**: The trigger levels and pending status. | bit 1 - trigger 1 pending | bit 2 - trigger 2 pending | bit 5 - trigger 1 level | bit 6 - trigger 2 level h](j;)}(h **activity**:h](jA)}(h **activity**h]hactivity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMjhjubj[)}(hhh](h)}(h&The trigger levels and pending status.h]h&The trigger levels and pending status.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjubjn)}(hhh](jr)}(hbit 1 - trigger 1 pendingh]hbit 1 - trigger 1 pending}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj,hhhKubjr)}(hbit 2 - trigger 2 pendingh]hbit 2 - trigger 2 pending}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj,hhhKubjr)}(hbit 5 - trigger 1 levelh]hbit 5 - trigger 1 level}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj,hhhKubjr)}(hbit 6 - trigger 2 levelh]hbit 6 - trigger 2 level}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hjKhj,hhhKubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1j4hhhMjhjubj5)}(h,**timestamp**: The trigger event timestamp. h](j;)}(h**timestamp**:h](jA)}(h **timestamp**h]h timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj}ubh:}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1j:hhhMmhjyubj[)}(hhh]h)}(hThe trigger event timestamp.h]hThe trigger event timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjubah}(h]h ]h"]h$]h&]uh1jZhjyubeh}(h]h ]h"]h$]h&]uh1j4hhhMmhjhhubeh}(h]h ]h"]h$]h&]uh1j/hjhhhhhNubh)}(hXThe iio device can operate either in "raw" mode where you can fetch the signal levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode. In the triggered buffer mode you can follow the signal level changes (activity bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you will also get the exact trigger event time that can be matched to a video frame (every mgb4 video frame has a timestamp with the same clock source).h]hXThe iio device can operate either in “raw” mode where you can fetch the signal levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode. In the triggered buffer mode you can follow the signal level changes (activity bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you will also get the exact trigger event time that can be matched to a video frame (every mgb4 video frame has a timestamp with the same clock source).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjhhubh)}(h*Note: although the activity sample always contains all the status bits, it makes no sense to get the pending bits in raw mode or the level bits in the triggered buffer mode - the values do not represent valid data in such case.*h]jV)}(hjh]hNote: although the activity sample always contains all the status bits, it makes no sense to get the pending bits in raw mode or the level bits in the triggered buffer mode - the values do not represent valid data in such case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jUhjubah}(h]h ]h"]h$]h&]uh1hhhhMvhjhhubeh}(h] iio-triggersah ]h"]iio (triggers)ah$]h&]uh1hhhhhhhhM_ubeh}(h]the-mgb4-driverah ]h"]the mgb4 driverah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjjjjj j j j}jzjj jjjjjjjju nametypes}(jjjj j}jjjjjuh}(jhjhj jj jjzj j jjjjjjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.