sphinx.addnodesdocument)}( rawsource children]( translations
LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba
attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/admin-guide/media/mgb4modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah }(h ]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah }(h ]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah }(h ]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah }(h ]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah }(h ]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/pt_BR/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah }(h ]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubeh }(h ]h ]h"]h$]h&]current_languageEnglishuh1h
hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah }(h ]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/admin-guide/media/mgb4.rsthKubh)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah }(h ]h ]h"]h$]h&]hhuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from
.
Processed by unicode2rstsubs.py, part of Docutils:
.h]hDerived from the Unicode character mappings available from
.
Processed by unicode2rstsubs.py, part of Docutils:
.}hhsbah }(h ]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsubstitution_definition)}(h*.. |amp| unicode:: U+00026 .. AMPERSANDh]h&}hhsbah }(h ]h ]h"]ampah$]h&]uh1hhhhKhhhhubh)}(h+.. |apos| unicode:: U+00027 .. APOSTROPHEh]h'}hhsbah }(h ]h ]h"]aposah$]h&]uh1hhhhKhhhhubh)}(h).. |ast| unicode:: U+0002A .. ASTERISKh]h*}hj sbah }(h ]h ]h"]astah$]h&]uh1hhhhK hhhhubh)}(h+.. |brvbar| unicode:: U+000A6 .. BROKEN BARh]h¦}hj sbah }(h ]h ]h"]brvbarah$]h&]uh1hhhhK
hhhhubh)}(h0.. |bsol| unicode:: U+0005C .. REVERSE SOLIDUSh]h\}hj# sbah }(h ]h ]h"]bsolah$]h&]uh1hhhhK hhhhubh)}(h*.. |cent| unicode:: U+000A2 .. CENT SIGNh]h¢}hj2 sbah }(h ]h ]h"]centah$]h&]uh1hhhhK hhhhubh)}(h&.. |colon| unicode:: U+0003A .. COLONh]h:}hjA sbah }(h ]h ]h"]colonah$]h&]uh1hhhhK
hhhhubh)}(h&.. |comma| unicode:: U+0002C .. COMMAh]h,}hjP sbah }(h ]h ]h"]commaah$]h&]uh1hhhhKhhhhubh)}(h... |commat| unicode:: U+00040 .. COMMERCIAL ATh]h@}hj_ sbah }(h ]h ]h"]commatah$]h&]uh1hhhhKhhhhubh)}(h/.. |copy| unicode:: U+000A9 .. COPYRIGHT SIGNh]h©}hjn sbah }(h ]h ]h"]copyah$]h&]uh1hhhhKhhhhubh)}(h... |curren| unicode:: U+000A4 .. CURRENCY SIGNh]h¤}hj} sbah }(h ]h ]h"]currenah$]h&]uh1hhhhKhhhhubh)}(h0.. |darr| unicode:: U+02193 .. DOWNWARDS ARROWh]h↓}hj sbah }(h ]h ]h"]darrah$]h&]uh1hhhhKhhhhubh)}(h,.. |deg| unicode:: U+000B0 .. DEGREE SIGNh]h°}hj sbah }(h ]h ]h"]degah$]h&]uh1hhhhKhhhhubh)}(h... |divide| unicode:: U+000F7 .. DIVISION SIGNh]h÷}hj sbah }(h ]h ]h"]divideah$]h&]uh1hhhhKhhhhubh)}(h,.. |dollar| unicode:: U+00024 .. DOLLAR SIGNh]h$}hj sbah }(h ]h ]h"]dollarah$]h&]uh1hhhhKhhhhubh)}(h,.. |equals| unicode:: U+0003D .. EQUALS SIGNh]h=}hj sbah }(h ]h ]h"]equalsah$]h&]uh1hhhhKhhhhubh)}(h1.. |excl| unicode:: U+00021 .. EXCLAMATION MARKh]h!}hj sbah }(h ]h ]h"]exclah$]h&]uh1hhhhKhhhhubh)}(h9.. |frac12| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hj sbah }(h ]h ]h"]frac12ah$]h&]uh1hhhhKhhhhubh)}(h<.. |frac14| unicode:: U+000BC .. VULGAR FRACTION ONE QUARTERh]h¼}hj sbah }(h ]h ]h"]frac14ah$]h&]uh1hhhhKhhhhubh)}(h;.. |frac18| unicode:: U+0215B .. VULGAR FRACTION ONE EIGHTHh]h⅛}hj sbah }(h ]h ]h"]frac18ah$]h&]uh1hhhhKhhhhubh)}(h?.. |frac34| unicode:: U+000BE .. VULGAR FRACTION THREE QUARTERSh]h¾}hj sbah }(h ]h ]h"]frac34ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac38| unicode:: U+0215C .. VULGAR FRACTION THREE EIGHTHSh]h⅜}hj" sbah }(h ]h ]h"]frac38ah$]h&]uh1hhhhK hhhhubh)}(h=.. |frac58| unicode:: U+0215D .. VULGAR FRACTION FIVE EIGHTHSh]h⅝}hj1 sbah }(h ]h ]h"]frac58ah$]h&]uh1hhhhK hhhhubh)}(h>.. |frac78| unicode:: U+0215E .. VULGAR FRACTION SEVEN EIGHTHSh]h⅞}hj@ sbah }(h ]h ]h"]frac78ah$]h&]uh1hhhhK hhhhubh)}(h2.. |gt| unicode:: U+0003E .. GREATER-THAN SIGNh]h>}hjO sbah }(h ]h ]h"]gtah$]h&]uh1hhhhK hhhhubh)}(h9.. |half| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hj^ sbah }(h ]h ]h"]halfah$]h&]uh1hhhhK hhhhubh)}(h/.. |horbar| unicode:: U+02015 .. HORIZONTAL BARh]h―}hjm sbah }(h ]h ]h"]horbarah$]h&]uh1hhhhK!hhhhubh)}(h'.. |hyphen| unicode:: U+02010 .. HYPHENh]h‐}hj| sbah }(h ]h ]h"]hyphenah$]h&]uh1hhhhK"hhhhubh)}(h:.. |iexcl| unicode:: U+000A1 .. INVERTED EXCLAMATION MARKh]h¡}hj sbah }(h ]h ]h"]iexclah$]h&]uh1hhhhK#hhhhubh)}(h7.. |iquest| unicode:: U+000BF .. INVERTED QUESTION MARKh]h¿}hj sbah }(h ]h ]h"]iquestah$]h&]uh1hhhhK$hhhhubh)}(hJ.. |laquo| unicode:: U+000AB .. LEFT-POINTING DOUBLE ANGLE QUOTATION MARKh]h«}hj sbah }(h ]h ]h"]laquoah$]h&]uh1hhhhK%hhhhubh)}(h0.. |larr| unicode:: U+02190 .. LEFTWARDS ARROWh]h←}hj sbah }(h ]h ]h"]larrah$]h&]uh1hhhhK&hhhhubh)}(h3.. |lcub| unicode:: U+0007B .. LEFT CURLY BRACKETh]h{}hj sbah }(h ]h ]h"]lcubah$]h&]uh1hhhhK'hhhhubh)}(h;.. |ldquo| unicode:: U+0201C .. LEFT DOUBLE QUOTATION MARKh]h“}hj sbah }(h ]h ]h"]ldquoah$]h&]uh1hhhhK(hhhhubh)}(h).. |lowbar| unicode:: U+0005F .. LOW LINEh]h_}hj sbah }(h ]h ]h"]lowbarah$]h&]uh1hhhhK)hhhhubh)}(h1.. |lpar| unicode:: U+00028 .. LEFT PARENTHESISh]h(}hj sbah }(h ]h ]h"]lparah$]h&]uh1hhhhK*hhhhubh)}(h4.. |lsqb| unicode:: U+0005B .. LEFT SQUARE BRACKETh]h[}hj sbah }(h ]h ]h"]lsqbah$]h&]uh1hhhhK+hhhhubh)}(h;.. |lsquo| unicode:: U+02018 .. LEFT SINGLE QUOTATION MARKh]h‘}hj sbah }(h ]h ]h"]lsquoah$]h&]uh1hhhhK,hhhhubh)}(h/.. |lt| unicode:: U+0003C .. LESS-THAN SIGNh]h<}hj! sbah }(h ]h ]h"]ltah$]h&]uh1hhhhK-hhhhubh)}(h+.. |micro| unicode:: U+000B5 .. MICRO SIGNh]hµ}hj0 sbah }(h ]h ]h"]microah$]h&]uh1hhhhK.hhhhubh)}(h+.. |middot| unicode:: U+000B7 .. MIDDLE DOTh]h·}hj? sbah }(h ]h ]h"]middotah$]h&]uh1hhhhK/hhhhubh)}(h/.. |nbsp| unicode:: U+000A0 .. NO-BREAK SPACEh]h }hjN sbah }(h ]h ]h"]nbspah$]h&]uh1hhhhK0hhhhubh)}(h).. |not| unicode:: U+000AC .. NOT SIGNh]h¬}hj] sbah }(h ]h ]h"]notah$]h&]uh1hhhhK1hhhhubh)}(h,.. |num| unicode:: U+00023 .. NUMBER SIGNh]h#}hjl sbah }(h ]h ]h"]numah$]h&]uh1hhhhK2hhhhubh)}(h).. |ohm| unicode:: U+02126 .. OHM SIGNh]hΩ}hj{ sbah }(h ]h ]h"]ohmah$]h&]uh1hhhhK3hhhhubh)}(h;.. |ordf| unicode:: U+000AA .. FEMININE ORDINAL INDICATORh]hª}hj sbah }(h ]h ]h"]ordfah$]h&]uh1hhhhK4hhhhubh)}(h<.. |ordm| unicode:: U+000BA .. MASCULINE ORDINAL INDICATORh]hº}hj sbah }(h ]h ]h"]ordmah$]h&]uh1hhhhK5hhhhubh)}(h-.. |para| unicode:: U+000B6 .. PILCROW SIGNh]h¶}hj sbah }(h ]h ]h"]paraah$]h&]uh1hhhhK6hhhhubh)}(h-.. |percnt| unicode:: U+00025 .. PERCENT SIGNh]h%}hj sbah }(h ]h ]h"]percntah$]h&]uh1hhhhK7hhhhubh)}(h*.. |period| unicode:: U+0002E .. FULL STOPh]h.}hj sbah }(h ]h ]h"]periodah$]h&]uh1hhhhK8hhhhubh)}(h*.. |plus| unicode:: U+0002B .. PLUS SIGNh]h+}hj sbah }(h ]h ]h"]plusah$]h&]uh1hhhhK9hhhhubh)}(h0.. |plusmn| unicode:: U+000B1 .. PLUS-MINUS SIGNh]h±}hj sbah }(h ]h ]h"]plusmnah$]h&]uh1hhhhK:hhhhubh)}(h+.. |pound| unicode:: U+000A3 .. POUND SIGNh]h£}hj sbah }(h ]h ]h"]poundah$]h&]uh1hhhhK;hhhhubh)}(h... |quest| unicode:: U+0003F .. QUESTION MARKh]h?}hj sbah }(h ]h ]h"]questah$]h&]uh1hhhhKhhhhubh)}(h1.. |rarr| unicode:: U+02192 .. RIGHTWARDS ARROWh]h→}hj/ sbah }(h ]h ]h"]rarrah$]h&]uh1hhhhK?hhhhubh)}(h4.. |rcub| unicode:: U+0007D .. RIGHT CURLY BRACKETh]h}}hj> sbah }(h ]h ]h"]rcubah$]h&]uh1hhhhK@hhhhubh)}(h<.. |rdquo| unicode:: U+0201D .. RIGHT DOUBLE QUOTATION MARKh]h”}hjM sbah }(h ]h ]h"]rdquoah$]h&]uh1hhhhKAhhhhubh)}(h0.. |reg| unicode:: U+000AE .. REGISTERED SIGNh]h®}hj\ sbah }(h ]h ]h"]regah$]h&]uh1hhhhKBhhhhubh)}(h2.. |rpar| unicode:: U+00029 .. RIGHT PARENTHESISh]h)}hjk sbah }(h ]h ]h"]rparah$]h&]uh1hhhhKChhhhubh)}(h5.. |rsqb| unicode:: U+0005D .. RIGHT SQUARE BRACKETh]h]}hjz sbah }(h ]h ]h"]rsqbah$]h&]uh1hhhhKDhhhhubh)}(h<.. |rsquo| unicode:: U+02019 .. RIGHT SINGLE QUOTATION MARKh]h’}hj sbah }(h ]h ]h"]rsquoah$]h&]uh1hhhhKEhhhhubh)}(h-.. |sect| unicode:: U+000A7 .. SECTION SIGNh]h§}hj sbah }(h ]h ]h"]sectah$]h&]uh1hhhhKFhhhhubh)}(h*.. |semi| unicode:: U+0003B .. SEMICOLONh]h;}hj sbah }(h ]h ]h"]semiah$]h&]uh1hhhhKGhhhhubh)}(h,.. |shy| unicode:: U+000AD .. SOFT HYPHENh]h}hj sbah }(h ]h ]h"]shyah$]h&]uh1hhhhKHhhhhubh)}(h(.. |sol| unicode:: U+0002F .. SOLIDUSh]h/}hj sbah }(h ]h ]h"]solah$]h&]uh1hhhhKIhhhhubh)}(h,.. |sung| unicode:: U+0266A .. EIGHTH NOTEh]h♪}hj sbah }(h ]h ]h"]sungah$]h&]uh1hhhhKJhhhhubh)}(h0.. |sup1| unicode:: U+000B9 .. SUPERSCRIPT ONEh]h¹}hj sbah }(h ]h ]h"]sup1ah$]h&]uh1hhhhKKhhhhubh)}(h0.. |sup2| unicode:: U+000B2 .. SUPERSCRIPT TWOh]h²}hj sbah }(h ]h ]h"]sup2ah$]h&]uh1hhhhKLhhhhubh)}(h2.. |sup3| unicode:: U+000B3 .. SUPERSCRIPT THREEh]h³}hj sbah }(h ]h ]h"]sup3ah$]h&]uh1hhhhKMhhhhubh)}(h4.. |times| unicode:: U+000D7 .. MULTIPLICATION SIGNh]h×}hj sbah }(h ]h ]h"]timesah$]h&]uh1hhhhKNhhhhubh)}(h0.. |trade| unicode:: U+02122 .. TRADE MARK SIGNh]h™}hj sbah }(h ]h ]h"]tradeah$]h&]uh1hhhhKOhhhhubh)}(h... |uarr| unicode:: U+02191 .. UPWARDS ARROWh]h↑}hj. sbah }(h ]h ]h"]uarrah$]h&]uh1hhhhKPhhhhubh)}(h... |verbar| unicode:: U+0007C .. VERTICAL LINEh]h|}hj= sbah }(h ]h ]h"]verbarah$]h&]uh1hhhhKQhhhhubh)}(h*.. |yen| unicode:: U+000A5 .. YEN SIGN
h]h¥}hjL sbah }(h ]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(hThe mgb4 driverh]hThe mgb4 driver}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj] hhhhhKubhdefinition_list)}(hhh]hdefinition_list_item)}(hiCopyright |copy| 2023 - 2025 Digiteq Automotive
author: Martin Tůma
h](hterm)}(h/Copyright |copy| 2023 - 2025 Digiteq Automotiveh](h
Copyright }(hj} hhhNhNubh©}(hj} hhhNhNubh 2023 - 2025 Digiteq Automotive}(hj} hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK hjw ubh
definition)}(hhh]h paragraph)}(h8author: Martin Tůma h](hauthor: Martin Tůma <}(hj hhhNhNubh reference)}(h!martin.tuma@digiteqautomotive.comh]h!martin.tuma@digiteqautomotive.com}(hj hhhNhNubah }(h ]h ]h"]h$]h&]refuri(mailto:martin.tuma@digiteqautomotive.comuh1j hj ubh>}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j hhhK hj ubah }(h ]h ]h"]h$]h&]uh1j hjw ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK hjr ubah }(h ]h ]h"]h$]h&]uh1jp hj] hhhhhNubj )}(hThis is a v4l2 device driver for the Digiteq Automotive FrameGrabber 4, a PCIe
card capable of capturing and generating FPD-Link III and GMSL2/3 video streams
as used in the automotive industry.h]hThis is a v4l2 device driver for the Digiteq Automotive FrameGrabber 4, a PCIe
card capable of capturing and generating FPD-Link III and GMSL2/3 video streams
as used in the automotive industry.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK hj] hhubj\ )}(hhh](ja )}(hsysfs interfaceh]hsysfs interface}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj hhhhhKubj )}(hThe mgb4 driver provides a sysfs interface, that is used to configure video
stream related parameters (some of them must be set properly before the v4l2
device can be opened) and obtain the video device/stream status.h]hThe mgb4 driver provides a sysfs interface, that is used to configure video
stream related parameters (some of them must be set properly before the v4l2
device can be opened) and obtain the video device/stream status.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj hhubj )}(hThere are two types of parameters - global / PCI card related, found under
``/sys/class/video4linux/videoX/device`` and module specific found under
``/sys/class/video4linux/videoX``.h](hKThere are two types of parameters - global / PCI card related, found under
}(hj hhhNhNubhliteral)}(h(``/sys/class/video4linux/videoX/device``h]h$/sys/class/video4linux/videoX/device}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh! and module specific found under
}(hj hhhNhNubj )}(h!``/sys/class/video4linux/videoX``h]h /sys/class/video4linux/videoX}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j hhhKhj hhubj\ )}(hhh](ja )}(h Global (PCI card) parametersh]h Global (PCI card) parameters}(hj4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj1 hhhhhKubjq )}(hhh](jv )}(hX **module_type** (R):
Module type.
| 0 - No module present
| 1 - FPDL3
| 2 - GMSL3 (one serializer, two daisy chained deserializers)
| 3 - GMSL3 (one serializer, two deserializers)
| 4 - GMSL3 (two deserializers with two daisy chain outputs)
| 6 - GMSL1
| 8 - GMSL3 coax
h](j| )}(h**module_type** (R):h](hstrong)}(h**module_type**h]h module_type}(hjO hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjI ubh (R):}(hjI hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK&hjE ubj )}(hhh](j )}(h Module type.h]h Module type.}(hjj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK hjg ubh
line_block)}(hhh](hh)}(h0 - No module presenth]h0 - No module present}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1hindentK hjz hhhK ubj} )}(h 1 - FPDL3h]h 1 - FPDL3}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjz hhhK ubj} )}(h;2 - GMSL3 (one serializer, two daisy chained deserializers)h]h;2 - GMSL3 (one serializer, two daisy chained deserializers)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjz hhhK ubj} )}(h-3 - GMSL3 (one serializer, two deserializers)h]h-3 - GMSL3 (one serializer, two deserializers)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjz hhhK ubj} )}(h:4 - GMSL3 (two deserializers with two daisy chain outputs)h]h:4 - GMSL3 (two deserializers with two daisy chain outputs)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjz hhhK ubj} )}(h 6 - GMSL1h]h 6 - GMSL1}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjz hhhK ubj} )}(h8 - GMSL3 coaxh]h8 - GMSL3 coax}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjz hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hjg ubeh }(h ]h ]h"]h$]h&]uh1j hjE ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK&hjB ubjv )}(hQ**module_version** (R):
Module version number. Zero in case of a missing module.
h](j| )}(h**module_version** (R):h](jN )}(h**module_version**h]hmodule_version}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (R):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK)hj ubj )}(hhh]j )}(h8Module version number. Zero in case of a missing module.h]h8Module version number. Zero in case of a missing module.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK)hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK)hjB hhubjv )}(hE**fw_type** (R):
Firmware type.
| 1 - FPDL3
| 2 - GMSL3
| 3 - GMSL1
h](j| )}(h**fw_type** (R):h](jN )}(h **fw_type**h]hfw_type}(hj8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj4 ubh (R):}(hj4 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK0hj0 ubj )}(hhh](j )}(hFirmware type.h]hFirmware type.}(hjS hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK,hjP ubjy )}(hhh](j} )}(h 1 - FPDL3h]h 1 - FPDL3}(hjd hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hja hhhK ubj} )}(h 2 - GMSL3h]h 2 - GMSL3}(hjr hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hja hhhK ubj} )}(h 3 - GMSL1h]h 3 - GMSL1}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hja hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hjP ubeh }(h ]h ]h"]h$]h&]uh1j hj0 ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK0hjB hhubjv )}(h-**fw_version** (R):
Firmware version number.
h](j| )}(h**fw_version** (R):h](jN )}(h**fw_version**h]h
fw_version}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (R):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK3hj ubj )}(hhh]j )}(hFirmware version number.h]hFirmware version number.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK3hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK3hjB hhubjv )}(h**serial_number** (R):
Card serial number. The format is::
PRODUCT-REVISION-SERIES-SERIAL
where each component is a 8b number.
h](j| )}(h**serial_number** (R):h](jN )}(h**serial_number**h]h
serial_number}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (R):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK:hj ubj )}(hhh](j )}(h#Card serial number. The format is::h]h"Card serial number. The format is:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK6hj ubh
literal_block)}(h PRODUCT-REVISION-SERIES-SERIALh]h PRODUCT-REVISION-SERIES-SERIAL}hj sbah }(h ]h ]h"]h$]h&]hhuh1j hhhK8hj ubj )}(h$where each component is a 8b number.h]h$where each component is a 8b number.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK:hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK:hjB hhubeh }(h ]h ]h"]h$]h&]uh1jp hj1 hhhhhNubeh }(h ]global-pci-card-parametersah ]h"] global (pci card) parametersah$]h&]uh1j[ hj hhhhhKubj\ )}(hhh](ja )}(h"Common FPDL3/GMSL input parametersh]h"Common FPDL3/GMSL input parameters}(hjI hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hjF hhhhhK=ubjq )}(hhh](jv )}(h/**input_id** (R):
Input number ID, zero based.
h](j| )}(h**input_id** (R):h](jN )}(h **input_id**h]hinput_id}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj^ ubh (R):}(hj^ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhK@hjZ ubj )}(hhh]j )}(h Input number ID, zero based.h]h Input number ID, zero based.}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK@hjz ubah }(h ]h ]h"]h$]h&]uh1j hjZ ubeh }(h ]h ]h"]h$]h&]uh1ju hhhK@hjW ubjv )}(hb**oldi_lane_width** (RW):
Number of deserializer output lanes.
| 0 - single
| 1 - dual (default)
h](j| )}(h**oldi_lane_width** (RW):h](jN )}(h**oldi_lane_width**h]holdi_lane_width}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKFhj ubj )}(hhh](j )}(h$Number of deserializer output lanes.h]h$Number of deserializer output lanes.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKChj ubjy )}(hhh](j} )}(h
0 - singleh]h
0 - single}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h1 - dual (default)h]h1 - dual (default)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKFhjW hhubjv )}(h**color_mapping** (RW):
Mapping of the incoming bits in the signal to the colour bits of the pixels.
| 0 - OLDI/JEIDA
| 1 - SPWG/VESA (default)
| 2 - ZDML
h](j| )}(h**color_mapping** (RW):h](jN )}(h**color_mapping**h]h
color_mapping}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKMhj ubj )}(hhh](j )}(hLMapping of the incoming bits in the signal to the colour bits of the pixels.h]hLMapping of the incoming bits in the signal to the colour bits of the pixels.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKIhj ubjy )}(hhh](j} )}(h0 - OLDI/JEIDAh]h0 - OLDI/JEIDA}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj* hhhK ubj} )}(h1 - SPWG/VESA (default)h]h1 - SPWG/VESA (default)}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj* hhhK ubj} )}(h2 - ZDMLh]h2 - ZDML}(hjI hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj* hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKMhjW hhubjv )}(hXG **link_status** (R):
Video link status. If the link is locked, chips are properly connected and
communicating at the same speed and protocol. The link can be locked without
an active video stream.
A value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2
VIDIOC_ENUMINPUT status bits.
| 0 - unlocked
| 1 - locked
h](j| )}(h**link_status** (R):h](jN )}(h**link_status**h]h link_status}(hjq hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjm ubh (R):}(hjm hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKXhji ubj )}(hhh](j )}(hVideo link status. If the link is locked, chips are properly connected and
communicating at the same speed and protocol. The link can be locked without
an active video stream.h]hVideo link status. If the link is locked, chips are properly connected and
communicating at the same speed and protocol. The link can be locked without
an active video stream.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKPhj ubj )}(hcA value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2
VIDIOC_ENUMINPUT status bits.h]hcA value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2
VIDIOC_ENUMINPUT status bits.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKThj ubjy )}(hhh](j} )}(h 0 - unlockedh]h 0 - unlocked}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h
1 - lockedh]h
1 - locked}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hji ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKXhjW hhubjv )}(hX **stream_status** (R):
Video stream status. A stream is detected if the link is locked, the input
pixel clock is running and the DE signal is moving.
A value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2
VIDIOC_ENUMINPUT status bits.
| 0 - not detected
| 1 - detected
h](j| )}(h**stream_status** (R):h](jN )}(h**stream_status**h]h
stream_status}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (R):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKbhj ubj )}(hhh](j )}(h~Video stream status. A stream is detected if the link is locked, the input
pixel clock is running and the DE signal is moving.h]h~Video stream status. A stream is detected if the link is locked, the input
pixel clock is running and the DE signal is moving.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK[hj ubj )}(heA value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2
VIDIOC_ENUMINPUT status bits.h]heA value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2
VIDIOC_ENUMINPUT status bits.}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK^hj ubjy )}(hhh](j} )}(h0 - not detectedh]h0 - not detected}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj
hhhK ubj} )}(h 1 - detectedh]h 1 - detected}(hj)
hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj
hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKbhjW hhubjv )}(h**video_width** (R):
Video stream width. This is the actual width as detected by the HW.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width
field of the v4l2_bt_timings struct.
h](j| )}(h**video_width** (R):h](jN )}(h**video_width**h]h video_width}(hjQ
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjM
ubh (R):}(hjM
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhhjI
ubj )}(hhh](j )}(hCVideo stream width. This is the actual width as detected by the HW.h]hCVideo stream width. This is the actual width as detected by the HW.}(hjl
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKehji
ubj )}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width
field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width
field of the v4l2_bt_timings struct.}(hjz
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKghji
ubeh }(h ]h ]h"]h$]h&]uh1j hjI
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhhjW hhubjv )}(h**video_height** (R):
Video stream height. This is the actual height as detected by the HW.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height
field of the v4l2_bt_timings struct.
h](j| )}(h**video_height** (R):h](jN )}(h**video_height**h]h video_height}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj
ubh (R):}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKnhj
ubj )}(hhh](j )}(hEVideo stream height. This is the actual height as detected by the HW.h]hEVideo stream height. This is the actual height as detected by the HW.}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKkhj
ubj )}(hqThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height
field of the v4l2_bt_timings struct.h]hqThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height
field of the v4l2_bt_timings struct.}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKmhj
ubeh }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKnhjW hhubjv )}(hX **vsync_status** (R):
The type of VSYNC pulses as detected by the video format detector.
The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
the polarities field of the v4l2_bt_timings struct.
| 0 - active low
| 1 - active high
| 2 - not available
h](j| )}(h**vsync_status** (R):h](jN )}(h**vsync_status**h]h vsync_status}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj
ubh (R):}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKxhj
ubj )}(hhh](j )}(hBThe type of VSYNC pulses as detected by the video format detector.h]hBThe type of VSYNC pulses as detected by the video format detector.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKqhj
ubj )}(hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
the polarities field of the v4l2_bt_timings struct.h]hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
the polarities field of the v4l2_bt_timings struct.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKshj
ubjy )}(hhh](j} )}(h0 - active lowh]h0 - active low}(hj! hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h1 - active highh]h1 - active high}(hj/ hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h2 - not availableh]h2 - not available}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj
ubeh }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKxhjW hhubjv )}(hX **hsync_status** (R):
The type of HSYNC pulses as detected by the video format detector.
The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
the polarities field of the v4l2_bt_timings struct.
| 0 - active low
| 1 - active high
| 2 - not available
h](j| )}(h**hsync_status** (R):h](jN )}(h**hsync_status**h]h hsync_status}(hje hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hja ubh (R):}(hja hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj] ubj )}(hhh](j )}(hBThe type of HSYNC pulses as detected by the video format detector.h]hBThe type of HSYNC pulses as detected by the video format detector.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK{hj} ubj )}(hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
the polarities field of the v4l2_bt_timings struct.h]hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
the polarities field of the v4l2_bt_timings struct.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhK}hj} ubjy )}(hhh](j} )}(h0 - active lowh]h0 - active low}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h1 - active highh]h1 - active high}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h2 - not availableh]h2 - not available}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj} ubeh }(h ]h ]h"]h$]h&]uh1j hj] ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hXU **vsync_gap_length** (RW):
If the incoming video signal does not contain synchronization VSYNC and
HSYNC pulses, these must be generated internally in the FPGA to achieve
the correct frame ordering. This value indicates, how many "empty" pixels
(pixels with deasserted Data Enable signal) are necessary to generate the
internal VSYNC pulse.
h](j| )}(h**vsync_gap_length** (RW):h](jN )}(h**vsync_gap_length**h]hvsync_gap_length}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj ubj )}(hhh]j )}(hX9 If the incoming video signal does not contain synchronization VSYNC and
HSYNC pulses, these must be generated internally in the FPGA to achieve
the correct frame ordering. This value indicates, how many "empty" pixels
(pixels with deasserted Data Enable signal) are necessary to generate the
internal VSYNC pulse.h]hX= If the incoming video signal does not contain synchronization VSYNC and
HSYNC pulses, these must be generated internally in the FPGA to achieve
the correct frame ordering. This value indicates, how many “empty” pixels
(pixels with deasserted Data Enable signal) are necessary to generate the
internal VSYNC pulse.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX **hsync_gap_length** (RW):
If the incoming video signal does not contain synchronization VSYNC and
HSYNC pulses, these must be generated internally in the FPGA to achieve
the correct frame ordering. This value indicates, how many "empty" pixels
(pixels with deasserted Data Enable signal) are necessary to generate the
internal HSYNC pulse. The value must be greater than 1 and smaller than
vsync_gap_length.
h](j| )}(h**hsync_gap_length** (RW):h](jN )}(h**hsync_gap_length**h]hhsync_gap_length}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj ubj )}(hhh]j )}(hX} If the incoming video signal does not contain synchronization VSYNC and
HSYNC pulses, these must be generated internally in the FPGA to achieve
the correct frame ordering. This value indicates, how many "empty" pixels
(pixels with deasserted Data Enable signal) are necessary to generate the
internal HSYNC pulse. The value must be greater than 1 and smaller than
vsync_gap_length.h]hX If the incoming video signal does not contain synchronization VSYNC and
HSYNC pulses, these must be generated internally in the FPGA to achieve
the correct frame ordering. This value indicates, how many “empty” pixels
(pixels with deasserted Data Enable signal) are necessary to generate the
internal HSYNC pulse. The value must be greater than 1 and smaller than
vsync_gap_length.}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj8 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX **pclk_frequency** (R):
Input pixel clock frequency in kHz.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the pixelclock field of the v4l2_bt_timings struct.
*Note: The frequency_range parameter must be set properly first to get
a valid frequency here.*
h](j| )}(h**pclk_frequency** (R):h](jN )}(h**pclk_frequency**h]hpclk_frequency}(hj] hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjY ubh (R):}(hjY hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhjU ubj )}(hhh](j )}(h#Input pixel clock frequency in kHz.h]h#Input pixel clock frequency in kHz.}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhju ubj )}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the pixelclock field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the pixelclock field of the v4l2_bt_timings struct.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhju ubj )}(h_*Note: The frequency_range parameter must be set properly first to get
a valid frequency here.*h]hemphasis)}(hj h]h]Note: The frequency_range parameter must be set properly first to get
a valid frequency here.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j hhhKhju ubeh }(h ]h ]h"]h$]h&]uh1j hjU ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(h**hsync_width** (R):
Width of the HSYNC signal in PCLK clock ticks.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hsync field of the v4l2_bt_timings struct.
h](j| )}(h**hsync_width** (R):h](jN )}(h**hsync_width**h]h hsync_width}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (R):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj ubj )}(hhh](j )}(h.Width of the HSYNC signal in PCLK clock ticks.h]h.Width of the HSYNC signal in PCLK clock ticks.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubj )}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hsync field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hsync field of the v4l2_bt_timings struct.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(h**vsync_width** (R):
Width of the VSYNC signal in PCLK clock ticks.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vsync field of the v4l2_bt_timings struct.
h](j| )}(h**vsync_width** (R):h](jN )}(h**vsync_width**h]h vsync_width}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj
ubh (R):}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj
ubj )}(hhh](j )}(h.Width of the VSYNC signal in PCLK clock ticks.h]h.Width of the VSYNC signal in PCLK clock ticks.}(hj'
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj$
ubj )}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vsync field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vsync field of the v4l2_bt_timings struct.}(hj5
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj$
ubeh }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX **hback_porch** (R):
Number of PCLK pulses between deassertion of the HSYNC signal and the first
valid pixel in the video line (marked by DE=1).
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hbackporch field of the v4l2_bt_timings struct.
h](j| )}(h**hback_porch** (R):h](jN )}(h**hback_porch**h]h hback_porch}(hjW
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjS
ubh (R):}(hjS
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhjO
ubj )}(hhh](j )}(h{Number of PCLK pulses between deassertion of the HSYNC signal and the first
valid pixel in the video line (marked by DE=1).h]h{Number of PCLK pulses between deassertion of the HSYNC signal and the first
valid pixel in the video line (marked by DE=1).}(hjr
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhjo
ubj )}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hbackporch field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hbackporch field of the v4l2_bt_timings struct.}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhjo
ubeh }(h ]h ]h"]h$]h&]uh1j hjO
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX **hfront_porch** (R):
Number of PCLK pulses between the end of the last valid pixel in the video
line (marked by DE=1) and assertion of the HSYNC signal.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hfrontporch field of the v4l2_bt_timings struct.
h](j| )}(h**hfront_porch** (R):h](jN )}(h**hfront_porch**h]h hfront_porch}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj
ubh (R):}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj
ubj )}(hhh](j )}(hNumber of PCLK pulses between the end of the last valid pixel in the video
line (marked by DE=1) and assertion of the HSYNC signal.h]hNumber of PCLK pulses between the end of the last valid pixel in the video
line (marked by DE=1) and assertion of the HSYNC signal.}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj
ubj )}(hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hfrontporch field of the v4l2_bt_timings struct.h]hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the hfrontporch field of the v4l2_bt_timings struct.}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj
ubeh }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX
**vback_porch** (R):
Number of video lines between deassertion of the VSYNC signal and the video
line with the first valid pixel (marked by DE=1).
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vbackporch field of the v4l2_bt_timings struct.
h](j| )}(h**vback_porch** (R):h](jN )}(h**vback_porch**h]h vback_porch}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj
ubh (R):}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj
ubj )}(hhh](j )}(h}Number of video lines between deassertion of the VSYNC signal and the video
line with the first valid pixel (marked by DE=1).h]h}Number of video lines between deassertion of the VSYNC signal and the video
line with the first valid pixel (marked by DE=1).}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubj )}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vbackporch field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vbackporch field of the v4l2_bt_timings struct.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubeh }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX **vfront_porch** (R):
Number of video lines between the end of the last valid pixel line (marked
by DE=1) and assertion of the VSYNC signal.
The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vfrontporch field of the v4l2_bt_timings struct.
h](j| )}(h**vfront_porch** (R):h](jN )}(h**vfront_porch**h]h vfront_porch}(hj8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj4 ubh (R):}(hj4 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj0 ubj )}(hhh](j )}(hvNumber of video lines between the end of the last valid pixel line (marked
by DE=1) and assertion of the VSYNC signal.h]hvNumber of video lines between the end of the last valid pixel line (marked
by DE=1) and assertion of the VSYNC signal.}(hjS hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhjP ubj )}(hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vfrontporch field of the v4l2_bt_timings struct.h]hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
the vfrontporch field of the v4l2_bt_timings struct.}(hja hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhjP ubeh }(h ]h ]h"]h$]h&]uh1j hj0 ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubjv )}(hX~ **frequency_range** (RW)
PLL frequency range of the OLDI input clock generator. The PLL frequency is
derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to
"dual".
| 0 - PLL < 50MHz (default)
| 1 - PLL >= 50MHz
*Note: This parameter can not be changed while the input v4l2 device is
open.*
h](j| )}(h**frequency_range** (RW)h](jN )}(h**frequency_range**h]hfrequency_range}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW)}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj{ ubj )}(hhh](j )}(hPLL frequency range of the OLDI input clock generator. The PLL frequency is
derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to
"dual".h]hPLL frequency range of the OLDI input clock generator. The PLL frequency is
derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
oldi_lane_width is set to “single” and PCLK/2 if oldi_lane_width is set to
“dual”.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubjy )}(hhh](j} )}(h0 - PLL < 50MHz (default)h]h0 - PLL < 50MHz (default)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h1 - PLL >= 50MHzh]h1 - PLL >= 50MHz}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubj )}(hN*Note: This parameter can not be changed while the input v4l2 device is
open.*h]j )}(hj h]hLNote: This parameter can not be changed while the input v4l2 device is
open.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubeh }(h ]h ]h"]h$]h&]uh1j hj{ ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhjW hhubeh }(h ]h ]h"]h$]h&]uh1jp hjF hhhhhNubeh }(h ]"common-fpdl3-gmsl-input-parametersah ]h"]"common fpdl3/gmsl input parametersah$]h&]uh1j[ hj hhhhhK=ubj\ )}(hhh](ja )}(h#Common FPDL3/GMSL output parametersh]h#Common FPDL3/GMSL output parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj hhhhhKubjq )}(hhh](jv )}(h1**output_id** (R):
Output number ID, zero based.
h](j| )}(h**output_id** (R):h](jN )}(h
**output_id**h]h output_id}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (R):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj ubj )}(hhh]j )}(h Output number ID, zero based.h]h Output number ID, zero based.}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj6 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhj ubjv )}(hX **video_source** (RW):
Output video source. If set to 0 or 1, the source is the corresponding card
input and the v4l2 output devices are disabled. If set to 2 or 3, the source
is the corresponding v4l2 video output device. The default is
the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.
| 0 - input 0
| 1 - input 1
| 2 - v4l2 output 0
| 3 - v4l2 output 1
*Note: This parameter can not be changed while ANY of the input/output v4l2
devices is open.*
h](j| )}(h**video_source** (RW):h](jN )}(h**video_source**h]h video_source}(hj[ hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjW ubh (RW):}(hjW hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhjS ubj )}(hhh](j )}(hX Output video source. If set to 0 or 1, the source is the corresponding card
input and the v4l2 output devices are disabled. If set to 2 or 3, the source
is the corresponding v4l2 video output device. The default is
the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.h]hX Output video source. If set to 0 or 1, the source is the corresponding card
input and the v4l2 output devices are disabled. If set to 2 or 3, the source
is the corresponding v4l2 video output device. The default is
the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhjs ubjy )}(hhh](j} )}(h 0 - input 0h]h 0 - input 0}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h 1 - input 1h]h 1 - input 1}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h2 - v4l2 output 0h]h2 - v4l2 output 0}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h3 - v4l2 output 1h]h3 - v4l2 output 1}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hjs ubj )}(h]*Note: This parameter can not be changed while ANY of the input/output v4l2
devices is open.*h]j )}(hj h]h[Note: This parameter can not be changed while ANY of the input/output v4l2
devices is open.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j hhhKhjs ubeh }(h ]h ]h"]h$]h&]uh1j hjS ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhj hhubjv )}(hX **display_width** (RW):
Display width. There is no autodetection of the connected display, so the
proper value must be set before the start of streaming. The default width
is 1280.
*Note: This parameter can not be changed while the output v4l2 device is
open.*
h](j| )}(h**display_width** (RW):h](jN )}(h**display_width**h]h
display_width}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj ubj )}(hhh](j )}(hDisplay width. There is no autodetection of the connected display, so the
proper value must be set before the start of streaming. The default width
is 1280.h]hDisplay width. There is no autodetection of the connected display, so the
proper value must be set before the start of streaming. The default width
is 1280.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubj )}(hO*Note: This parameter can not be changed while the output v4l2 device is
open.*h]j )}(hj h]hMNote: This parameter can not be changed while the output v4l2 device is
open.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhj hhubjv )}(hX **display_height** (RW):
Display height. There is no autodetection of the connected display, so the
proper value must be set before the start of streaming. The default height
is 640.
*Note: This parameter can not be changed while the output v4l2 device is
open.*
h](j| )}(h**display_height** (RW):h](jN )}(h**display_height**h]hdisplay_height}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj@ ubh (RW):}(hj@ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj< ubj )}(hhh](j )}(hDisplay height. There is no autodetection of the connected display, so the
proper value must be set before the start of streaming. The default height
is 640.h]hDisplay height. There is no autodetection of the connected display, so the
proper value must be set before the start of streaming. The default height
is 640.}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj\ ubj )}(hO*Note: This parameter can not be changed while the output v4l2 device is
open.*h]j )}(hjo h]hMNote: This parameter can not be changed while the output v4l2 device is
open.}(hjq hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjm ubah }(h ]h ]h"]h$]h&]uh1j hhhKhj\ ubeh }(h ]h ]h"]h$]h&]uh1j hj< ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhj hhubjv )}(h**color_mapping** (RW):
Mapping of the outgoing bits in the signal to the colour bits of the pixels.
| 0 - OLDI/JEIDA
| 1 - SPWG/VESA (default)
| 2 - ZDML
h](j| )}(h**color_mapping** (RW):h](jN )}(h**color_mapping**h]h
color_mapping}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhKhj ubj )}(hhh](j )}(hLMapping of the outgoing bits in the signal to the colour bits of the pixels.h]hLMapping of the outgoing bits in the signal to the colour bits of the pixels.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubjy )}(hhh](j} )}(h0 - OLDI/JEIDAh]h0 - OLDI/JEIDA}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h1 - SPWG/VESA (default)h]h1 - SPWG/VESA (default)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h2 - ZDMLh]h2 - ZDML}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhKhj hhubjv )}(hX **frame_rate** (RW):
Output video signal frame rate limit in frames per second. Due to
the limited output pixel clock steps, the card can not always generate
a frame rate perfectly matching the value required by the connected display.
Using this parameter one can limit the frame rate by "crippling" the signal
so that the lines are not equal (the porches of the last line differ) but
the signal appears like having the exact frame rate to the connected display.
The default frame rate limit is 60Hz.
h](j| )}(h**frame_rate** (RW):h](jN )}(h**frame_rate**h]h
frame_rate}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMhj ubj )}(hhh]j )}(hX Output video signal frame rate limit in frames per second. Due to
the limited output pixel clock steps, the card can not always generate
a frame rate perfectly matching the value required by the connected display.
Using this parameter one can limit the frame rate by "crippling" the signal
so that the lines are not equal (the porches of the last line differ) but
the signal appears like having the exact frame rate to the connected display.
The default frame rate limit is 60Hz.h]hX Output video signal frame rate limit in frames per second. Due to
the limited output pixel clock steps, the card can not always generate
a frame rate perfectly matching the value required by the connected display.
Using this parameter one can limit the frame rate by “crippling” the signal
so that the lines are not equal (the porches of the last line differ) but
the signal appears like having the exact frame rate to the connected display.
The default frame rate limit is 60Hz.}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMhj hhubjv )}(h^**hsync_polarity** (RW):
HSYNC signal polarity.
| 0 - active low (default)
| 1 - active high
h](j| )}(h**hsync_polarity** (RW):h](jN )}(h**hsync_polarity**h]hhsync_polarity}(hjE hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjA ubh (RW):}(hjA hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMhj= ubj )}(hhh](j )}(hHSYNC signal polarity.h]hHSYNC signal polarity.}(hj` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMhj] ubjy )}(hhh](j} )}(h0 - active low (default)h]h0 - active low (default)}(hjq hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjn hhhK ubj} )}(h1 - active highh]h1 - active high}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjn hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj] ubeh }(h ]h ]h"]h$]h&]uh1j hj= ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMhj hhubjv )}(h^**vsync_polarity** (RW):
VSYNC signal polarity.
| 0 - active low (default)
| 1 - active high
h](j| )}(h**vsync_polarity** (RW):h](jN )}(h**vsync_polarity**h]hvsync_polarity}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMhj ubj )}(hhh](j )}(hVSYNC signal polarity.h]hVSYNC signal polarity.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM hj ubjy )}(hhh](j} )}(h0 - active low (default)h]h0 - active low (default)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h1 - active highh]h1 - active high}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMhj hhubjv )}(hX**de_polarity** (RW):
DE signal polarity.
| 0 - active low
| 1 - active high (default)
h](j| )}(h**de_polarity** (RW):h](jN )}(h**de_polarity**h]h de_polarity}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMhj ubj )}(hhh](j )}(hDE signal polarity.h]hDE signal polarity.}(hj$ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMhj! ubjy )}(hhh](j} )}(h0 - active lowh]h0 - active low}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj2 hhhK ubj} )}(h1 - active high (default)h]h1 - active high (default)}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj2 hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj! ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMhj hhubjv )}(hX **pclk_frequency** (RW):
Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
and there is a non-linear stepping between two consecutive allowed
frequencies. The driver finds the nearest allowed frequency to the given
value and sets it. When reading this property, you get the exact
frequency set by the driver. The default frequency is 61150kHz.
*Note: This parameter can not be changed while the output v4l2 device is
open.*
h](j| )}(h**pclk_frequency** (RW):h](jN )}(h**pclk_frequency**h]hpclk_frequency}(hjk hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjg ubh (RW):}(hjg hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM hjc ubj )}(hhh](j )}(hXW Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
and there is a non-linear stepping between two consecutive allowed
frequencies. The driver finds the nearest allowed frequency to the given
value and sets it. When reading this property, you get the exact
frequency set by the driver. The default frequency is 61150kHz.h]hXW Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
and there is a non-linear stepping between two consecutive allowed
frequencies. The driver finds the nearest allowed frequency to the given
value and sets it. When reading this property, you get the exact
frequency set by the driver. The default frequency is 61150kHz.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hO*Note: This parameter can not be changed while the output v4l2 device is
open.*h]j )}(hj h]hMNote: This parameter can not be changed while the output v4l2 device is
open.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j hhhM hj ubeh }(h ]h ]h"]h$]h&]uh1j hjc ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM hj hhubjv )}(hT**hsync_width** (RW):
Width of the HSYNC signal in pixels. The default value is 40.
h](j| )}(h**hsync_width** (RW):h](jN )}(h**hsync_width**h]h hsync_width}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM!hj ubj )}(hhh]j )}(h=Width of the HSYNC signal in pixels. The default value is 40.h]h=Width of the HSYNC signal in pixels. The default value is 40.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM!hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM!hj hhubjv )}(hY**vsync_width** (RW):
Width of the VSYNC signal in video lines. The default value is 20.
h](j| )}(h**vsync_width** (RW):h](jN )}(h**vsync_width**h]h vsync_width}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM$hj ubj )}(hhh]j )}(hBWidth of the VSYNC signal in video lines. The default value is 20.h]hBWidth of the VSYNC signal in video lines. The default value is 20.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM$hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM$hj hhubjv )}(h**hback_porch** (RW):
Number of PCLK pulses between deassertion of the HSYNC signal and the first
valid pixel in the video line (marked by DE=1). The default value is 50.
h](j| )}(h**hback_porch** (RW):h](jN )}(h**hback_porch**W h]h hback_porch}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj5 ubh (RW):}(hj5 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM(hj1 ubj )}(hhh]j )}(hNumber of PCLK pulses between deassertion of the HSYNC signal and the first
valid pixel in the video line (marked by DE=1). The default value is 50.h]hNumber of PCLK pulses between deassertion of the HSYNC signal and the first
valid pixel in the video line (marked by DE=1). The default value is 50.}(hjT hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM'hjQ ubah }(h ]h ]h"]h$]h&]uh1j hj1 ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM(hj hhubjv )}(h**hfront_porch** (RW):
Number of PCLK pulses between the end of the last valid pixel in the video
line (marked by DE=1) and assertion of the HSYNC signal. The default value
is 50.
h](j| )}(h**hfront_porch** (RW):h](jN )}(h**hfront_porch**h]h hfront_porch}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjr ubh (RW):}(hjr hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM-hjn ubj )}(hhh]j )}(hNumber of PCLK pulses between the end of the last valid pixel in the video
line (marked by DE=1) and assertion of the HSYNC signal. The default value
is 50.h]hNumber of PCLK pulses between the end of the last valid pixel in the video
line (marked by DE=1) and assertion of the HSYNC signal. The default value
is 50.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM+hj ubah }(h ]h ]h"]h$]h&]uh1j hjn ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM-hj hhubjv )}(h**vback_porch** (RW):
Number of video lines between deassertion of the VSYNC signal and the video
line with the first valid pixel (marked by DE=1). The default value is 31.
h](j| )}(h**vback_porch** (RW):h](jN )}(h**vback_porch**h]h vback_porch}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM1hj ubj )}(hhh]j )}(hNumber of video lines between deassertion of the VSYNC signal and the video
line with the first valid pixel (marked by DE=1). The default value is 31.h]hNumber of video lines between deassertion of the VSYNC signal and the video
line with the first valid pixel (marked by DE=1). The default value is 31.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM0hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM1hj hhubjv )}(h**vfront_porch** (RW):
Number of video lines between the end of the last valid pixel line (marked
by DE=1) and assertion of the VSYNC signal. The default value is 30.
h](j| )}(h**vfront_porch** (RW):h](jN )}(h**vfront_porch**h]h vfront_porch}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM5hj ubj )}(hhh]j )}(hNumber of video lines between the end of the last valid pixel line (marked
by DE=1) and assertion of the VSYNC signal. The default value is 30.h]hNumber of video lines between the end of the last valid pixel line (marked
by DE=1) and assertion of the VSYNC signal. The default value is 30.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM4hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM5hj hhubeh }(h ]h ]h"]h$]h&]uh1jp hj hhhhhNubeh }(h ]#common-fpdl3-gmsl-output-parametersah ]h"]#common fpdl3/gmsl output parametersah$]h&]uh1j[ hj hhhhhKubj\ )}(hhh](ja )}(h FPDL3 specific input parametersh]h FPDL3 specific input parameters}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj3 hhhhhM8ubjq )}(hhh]jv )}(hn**fpdl3_input_width** (RW):
Number of deserializer input lines.
| 0 - auto (default)
| 1 - single
| 2 - dual
h](j| )}(h**fpdl3_input_width** (RW):h](jN )}(h**fpdl3_input_width**h]hfpdl3_input_width}(hjO hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjK ubh (RW):}(hjK hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM?hjG ubj )}(hhh](j )}(h#Number of deserializer input lines.h]h#Number of deserializer input lines.}(hjj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM;hjg ubjy )}(hhh](j} )}(h0 - auto (default)h]h0 - auto (default)}(hj{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjx hhhK ubj} )}(h
1 - singleh]h
1 - single}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjx hhhK ubj} )}(h2 - dualh]h2 - dual}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjx hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hjg ubeh }(h ]h ]h"]h$]h&]uh1j hjG ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM?hjD ubah }(h ]h ]h"]h$]h&]uh1jp hj3 hhhhhNubeh }(h ] fpdl3-specific-input-parametersah ]h"] fpdl3 specific input parametersah$]h&]uh1j[ hj hhhhhM8ubj\ )}(hhh](ja )}(h FPDL3 specific output parametersh]h FPDL3 specific output parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj hhhhhMBubjq )}(hhh]jv )}(hn**fpdl3_output_width** (RW):
Number of serializer output lines.
| 0 - auto (default)
| 1 - single
| 2 - dual
h](j| )}(h **fpdl3_output_width** (RW):h](jN )}(h**fpdl3_output_width**h]hfpdl3_output_width}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMIhj ubj )}(hhh](j )}(h"Number of serializer output lines.h]h"Number of serializer output lines.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMEhj ubjy )}(hhh](j} )}(h0 - auto (default)h]h0 - auto (default)}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj
hhhK ubj} )}(h
1 - singleh]h
1 - single}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj
hhhK ubj} )}(h2 - dualh]h2 - dual}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj
hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMIhj ubah }(h ]h ]h"]h$]h&]uh1jp hj hhhhhNubeh }(h ] fpdl3-specific-output-parametersah ]h"] fpdl3 specific output parametersah$]h&]uh1j[ hj hhhhhMBubj\ )}(hhh](ja )}(h GMSL specific input parametersh]h GMSL specific input parameters}(hjZ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hjW hhhhhMLubjq )}(hhh](jv )}(hc**gmsl_mode** (RW):
GMSL speed mode.
| 0 - 12Gb/s (default)
| 1 - 6Gb/s
| 2 - 3Gb/s
| 3 - 1.5Gb/s
h](j| )}(h**gmsl_mode** (RW):h](jN )}(h
**gmsl_mode**h]h gmsl_mode}(hjs hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjo ubh (RW):}(hjo hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMThjk ubj )}(hhh](j )}(hGMSL speed mode.h]hGMSL speed mode.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMOhj ubjy )}(hhh](j} )}(h0 - 12Gb/s (default)h]h0 - 12Gb/s (default)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h 1 - 6Gb/sh]h 1 - 6Gb/s}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h 2 - 3Gb/sh]h 2 - 3Gb/s}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(h 3 - 1.5Gb/sh]h 3 - 1.5Gb/s}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hjk ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMThjh ubjv )}(hX3 **gmsl_stream_id** (RW):
The GMSL multi-stream contains up to four video streams. This parameter
selects which stream is captured by the video input. The value is the
zero-based index of the stream. The default stream id is 0.
*Note: This parameter can not be changed while the input v4l2 device is
open.*
h](j| )}(h**gmsl_stream_id** (RW):h](jN )}(h**gmsl_stream_id**h]hgmsl_stream_id}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh (RW):}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM\hj ubj )}(hhh](j )}(hThe GMSL multi-stream contains up to four video streams. This parameter
selects which stream is captured by the video input. The value is the
zero-based index of the stream. The default stream id is 0.h]hThe GMSL multi-stream contains up to four video streams. This parameter
selects which stream is captured by the video input. The value is the
zero-based index of the stream. The default stream id is 0.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMWhj ubj )}(hN*Note: This parameter can not be changed while the input v4l2 device is
open.*h]j )}(hj h]hLNote: This parameter can not be changed while the input v4l2 device is
open.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j hhhM[hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM\hjh hhubjv )}(h`**gmsl_fec** (RW):
GMSL Forward Error Correction (FEC).
| 0 - disabled
| 1 - enabled (default)
h](j| )}(h**gmsl_fec** (RW):h](jN )}(h **gmsl_fec**h]hgmsl_fec}(hjE hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hjA ubh (RW):}(hjA hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMbhj= ubj )}(hhh](j )}(h$GMSL Forward Error Correction (FEC).h]h$GMSL Forward Error Correction (FEC).}(hj` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhM_hj] ubjy )}(hhh](j} )}(h 0 - disabledh]h 0 - disabled}(hjq hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjn hhhK ubj} )}(h1 - enabled (default)h]h1 - enabled (default)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hjn hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj] ubeh }(h ]h ]h"]h$]h&]uh1j hj= ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMbhjh hhubeh }(h ]h ]h"]h$]h&]uh1jp hjW hhhhhNubeh }(h ] gmsl-specific-input-parametersah ]h"] gmsl specific input parametersah$]h&]uh1j[ hj hhhhhMLubeh }(h ]sysfs-interfaceah ]h"]sysfs interfaceah$]h&]uh1j[ hj] hhhhhKubj\ )}(hhh](ja )}(hMTD partitionsh]hMTD partitions}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj hhhhhMeubjq )}(hhh]jv )}(hThe mgb4 driver creates a MTD device with two partitions:
- mgb4-fw.X - FPGA firmware.
- mgb4-data.X - Factory settings, e.g. card serial number.
h](j| )}(h9The mgb4 driver creates a MTD device with two partitions:h]h9The mgb4 driver creates a MTD device with two partitions:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j{ hhhMihj ubj )}(hhh]h bullet_list)}(hhh](h list_item)}(hmgb4-fw.X - FPGA firmware.h]j )}(hj h]hmgb4-fw.X - FPGA firmware.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMhhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h9mgb4-data.X - Factory settings, e.g. card serial number.
h]j )}(h8mgb4-data.X - Factory settings, e.g. card serial number.h]h8mgb4-data.X - Factory settings, e.g. card serial number.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMihj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]bullet-uh1j hhhMhhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMihj ubah }(h ]h ]h"]h$]h&]uh1jp hj hhhNhNubj )}(hX The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is
read-only. The *X* attached to the partition name represents the card number.
Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may
also have a third partition named *mgb4-flash* available in the system. This
partition represents the whole, unpartitioned, card's FLASH memory and one should
not fiddle with it...h](hThe }(hj. hhhNhNubj )}(h *mgb4-fw*h]hmgb4-fw}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj. ubh3 partition is writable and is used for FW updates, }(hj. hhhNhNubj )}(h *mgb4-data*h]h mgb4-data}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj. ubh is
read-only. The }(hj. hhhNhNubj )}(h*X*h]hX}(hjZ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj. ubh attached to the partition name represents the card number.
Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may
also have a third partition named }(hj. hhhNhNubj )}(h *mgb4-flash*h]h
mgb4-flash}(hjl hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj. ubh available in the system. This
partition represents the whole, unpartitioned, card’s FLASH memory and one should
not fiddle with it...}(hj. hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j hhhMkhj hhubeh }(h ]mtd-partitionsah ]h"]mtd partitionsah$]h&]uh1j[ hj] hhhhhMeubj\ )}(hhh](ja )}(hIIO (triggers)h]hIIO (triggers)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j` hj hhhhhMsubj )}(hThe mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and
signal level status capability. The following scan elements are available:h]hThe mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and
signal level status capability. The following scan elements are available:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMuhj hhubjq )}(hhh](jv )}(h**activity**:
The trigger levels and pending status.
| bit 1 - trigger 1 pending
| bit 2 - trigger 2 pending
| bit 5 - trigger 1 level
| bit 6 - trigger 2 level
h](j| )}(h
**activity**:h](jN )}(h **activity**h]hactivity}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj ubh:}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhM~hj ubj )}(hhh](j )}(h&The trigger levels and pending status.h]h&The trigger levels and pending status.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMyhj ubjy )}(hhh](j} )}(hbit 1 - trigger 1 pendingh]hbit 1 - trigger 1 pending}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(hbit 2 - trigger 2 pendingh]hbit 2 - trigger 2 pending}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(hbit 5 - trigger 1 levelh]hbit 5 - trigger 1 level}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubj} )}(hbit 6 - trigger 2 levelh]hbit 6 - trigger 2 level}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1hj K hj hhhK ubeh }(h ]h ]h"]h$]h&]uh1jx hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1ju hhhM~hj ubjv )}(h,**timestamp**:
The trigger event timestamp.
h](j| )}(h**timestamp**:h](jN )}(h
**timestamp**h]h timestamp}(hj4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1jM hj0 ubh:}(hj0 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j{ hhhMhj, ubj )}(hhh]j )}(h The trigger event timestamp.h]h The trigger event timestamp.}(hjO hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMhjL ubah }(h ]h ]h"]h$]h&]uh1j hj, ubeh }(h ]h ]h"]h$]h&]uh1ju hhhMhj hhubeh }(h ]h ]h"]h$]h&]uh1jp hj hhhhhNubj )}(hX The iio device can operate either in "raw" mode where you can fetch the signal
levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode.
In the triggered buffer mode you can follow the signal level changes (activity
bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you
will also get the exact trigger event time that can be matched to a video frame
(every mgb4 video frame has a timestamp with the same clock source).h]hX The iio device can operate either in “raw” mode where you can fetch the signal
levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode.
In the triggered buffer mode you can follow the signal level changes (activity
bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you
will also get the exact trigger event time that can be matched to a video frame
(every mgb4 video frame has a timestamp with the same clock source).}(hjo hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hhhMhj hhubj )}(h*Note: although the activity sample always contains all the status bits, it makes
no sense to get the pending bits in raw mode or the level bits in the triggered
buffer mode - the values do not represent valid data in such case.*h]j )}(hj h]hNote: although the activity sample always contains all the status bits, it makes
no sense to get the pending bits in raw mode or the level bits in the triggered
buffer mode - the values do not represent valid data in such case.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj} ubah }(h ]h ]h"]h$]h&]uh1j hhhMhj hhubeh }(h ] iio-triggersah ]h"]iio (triggers)ah$]h&]uh1j[ hj] hhhhhMsubeh }(h ]the-mgb4-driverah ]h"]the mgb4 driverah$]h&]uh1j[ hhhhhhhKubeh }(h ]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(j` N generatorN datestampN source_linkN
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timesj tradej+ uarrj: verbarjI yenjX urefnames}refids}nameids}(j j j j jC j@ j j j0 j- j j jT jQ j j j j j j u nametypes}(j j jC j j0 j jT j j j uh }(j j] j j j@ j1 j jF j- j j j3 jQ j j jW j j j j u
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