sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/admin-guide/media/mgb4modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/admin-guide/media/mgb4modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/admin-guide/media/mgb4.rsthKubh)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from . 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COMMAh]h,}hj<sbah}(h]h ]h"]commaah$]h&]uh1hhhhKhhhhubh)}(h... |commat| unicode:: U+00040 .. COMMERCIAL ATh]h@}hjKsbah}(h]h ]h"]commatah$]h&]uh1hhhhKhhhhubh)}(h/.. |copy| unicode:: U+000A9 .. COPYRIGHT SIGNh]h©}hjZsbah}(h]h ]h"]copyah$]h&]uh1hhhhKhhhhubh)}(h... |curren| unicode:: U+000A4 .. CURRENCY SIGNh]h¤}hjisbah}(h]h ]h"]currenah$]h&]uh1hhhhKhhhhubh)}(h0.. |darr| unicode:: U+02193 .. DOWNWARDS ARROWh]h↓}hjxsbah}(h]h ]h"]darrah$]h&]uh1hhhhKhhhhubh)}(h,.. |deg| unicode:: U+000B0 .. DEGREE SIGNh]h°}hjsbah}(h]h ]h"]degah$]h&]uh1hhhhKhhhhubh)}(h... |divide| unicode:: U+000F7 .. DIVISION SIGNh]h÷}hjsbah}(h]h ]h"]divideah$]h&]uh1hhhhKhhhhubh)}(h,.. |dollar| unicode:: U+00024 .. DOLLAR SIGNh]h$}hjsbah}(h]h ]h"]dollarah$]h&]uh1hhhhKhhhhubh)}(h,.. |equals| unicode:: U+0003D .. EQUALS SIGNh]h=}hjsbah}(h]h ]h"]equalsah$]h&]uh1hhhhKhhhhubh)}(h1.. |excl| unicode:: U+00021 .. EXCLAMATION MARKh]h!}hjsbah}(h]h ]h"]exclah$]h&]uh1hhhhKhhhhubh)}(h9.. |frac12| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjsbah}(h]h ]h"]frac12ah$]h&]uh1hhhhKhhhhubh)}(h<.. |frac14| unicode:: U+000BC .. VULGAR FRACTION ONE QUARTERh]h¼}hjsbah}(h]h ]h"]frac14ah$]h&]uh1hhhhKhhhhubh)}(h;.. |frac18| unicode:: U+0215B .. VULGAR FRACTION ONE EIGHTHh]h⅛}hjsbah}(h]h ]h"]frac18ah$]h&]uh1hhhhKhhhhubh)}(h?.. |frac34| unicode:: U+000BE .. VULGAR FRACTION THREE QUARTERSh]h¾}hjsbah}(h]h ]h"]frac34ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac38| unicode:: U+0215C .. VULGAR FRACTION THREE EIGHTHSh]h⅜}hjsbah}(h]h ]h"]frac38ah$]h&]uh1hhhhKhhhhubh)}(h=.. |frac58| unicode:: U+0215D .. VULGAR FRACTION FIVE EIGHTHSh]h⅝}hjsbah}(h]h ]h"]frac58ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac78| unicode:: U+0215E .. VULGAR FRACTION SEVEN EIGHTHSh]h⅞}hj,sbah}(h]h ]h"]frac78ah$]h&]uh1hhhhKhhhhubh)}(h2.. |gt| unicode:: U+0003E .. GREATER-THAN SIGNh]h>}hj;sbah}(h]h ]h"]gtah$]h&]uh1hhhhKhhhhubh)}(h9.. |half| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjJsbah}(h]h ]h"]halfah$]h&]uh1hhhhK hhhhubh)}(h/.. |horbar| unicode:: U+02015 .. HORIZONTAL BARh]h―}hjYsbah}(h]h ]h"]horbarah$]h&]uh1hhhhK!hhhhubh)}(h'.. |hyphen| unicode:: U+02010 .. HYPHENh]h‐}hjhsbah}(h]h ]h"]hyphenah$]h&]uh1hhhhK"hhhhubh)}(h:.. |iexcl| unicode:: U+000A1 .. INVERTED EXCLAMATION MARKh]h¡}hjwsbah}(h]h ]h"]iexclah$]h&]uh1hhhhK#hhhhubh)}(h7.. |iquest| unicode:: U+000BF .. INVERTED QUESTION MARKh]h¿}hjsbah}(h]h ]h"]iquestah$]h&]uh1hhhhK$hhhhubh)}(hJ.. |laquo| unicode:: U+000AB .. LEFT-POINTING DOUBLE ANGLE QUOTATION MARKh]h«}hjsbah}(h]h ]h"]laquoah$]h&]uh1hhhhK%hhhhubh)}(h0.. |larr| unicode:: U+02190 .. LEFTWARDS ARROWh]h←}hjsbah}(h]h ]h"]larrah$]h&]uh1hhhhK&hhhhubh)}(h3.. |lcub| unicode:: U+0007B .. LEFT CURLY BRACKETh]h{}hjsbah}(h]h ]h"]lcubah$]h&]uh1hhhhK'hhhhubh)}(h;.. |ldquo| unicode:: U+0201C .. LEFT DOUBLE QUOTATION MARKh]h“}hjsbah}(h]h ]h"]ldquoah$]h&]uh1hhhhK(hhhhubh)}(h).. |lowbar| unicode:: U+0005F .. LOW LINEh]h_}hjsbah}(h]h ]h"]lowbarah$]h&]uh1hhhhK)hhhhubh)}(h1.. |lpar| unicode:: U+00028 .. LEFT PARENTHESISh]h(}hjsbah}(h]h ]h"]lparah$]h&]uh1hhhhK*hhhhubh)}(h4.. |lsqb| unicode:: U+0005B .. LEFT SQUARE BRACKETh]h[}hjsbah}(h]h ]h"]lsqbah$]h&]uh1hhhhK+hhhhubh)}(h;.. |lsquo| unicode:: U+02018 .. LEFT SINGLE QUOTATION MARKh]h‘}hjsbah}(h]h ]h"]lsquoah$]h&]uh1hhhhK,hhhhubh)}(h/.. |lt| unicode:: U+0003C .. LESS-THAN SIGNh]h<}hj sbah}(h]h ]h"]ltah$]h&]uh1hhhhK-hhhhubh)}(h+.. |micro| unicode:: U+000B5 .. MICRO SIGNh]hµ}hjsbah}(h]h ]h"]microah$]h&]uh1hhhhK.hhhhubh)}(h+.. |middot| unicode:: U+000B7 .. MIDDLE DOTh]h·}hj+sbah}(h]h ]h"]middotah$]h&]uh1hhhhK/hhhhubh)}(h/.. |nbsp| unicode:: U+000A0 .. NO-BREAK SPACEh]h }hj:sbah}(h]h ]h"]nbspah$]h&]uh1hhhhK0hhhhubh)}(h).. |not| unicode:: U+000AC .. NOT SIGNh]h¬}hjIsbah}(h]h ]h"]notah$]h&]uh1hhhhK1hhhhubh)}(h,.. |num| unicode:: U+00023 .. NUMBER SIGNh]h#}hjXsbah}(h]h ]h"]numah$]h&]uh1hhhhK2hhhhubh)}(h).. |ohm| unicode:: U+02126 .. OHM SIGNh]hΩ}hjgsbah}(h]h ]h"]ohmah$]h&]uh1hhhhK3hhhhubh)}(h;.. |ordf| unicode:: U+000AA .. FEMININE ORDINAL INDICATORh]hª}hjvsbah}(h]h ]h"]ordfah$]h&]uh1hhhhK4hhhhubh)}(h<.. |ordm| unicode:: U+000BA .. MASCULINE ORDINAL INDICATORh]hº}hjsbah}(h]h ]h"]ordmah$]h&]uh1hhhhK5hhhhubh)}(h-.. |para| unicode:: U+000B6 .. PILCROW SIGNh]h¶}hjsbah}(h]h ]h"]paraah$]h&]uh1hhhhK6hhhhubh)}(h-.. |percnt| unicode:: U+00025 .. PERCENT SIGNh]h%}hjsbah}(h]h ]h"]percntah$]h&]uh1hhhhK7hhhhubh)}(h*.. |period| unicode:: U+0002E .. FULL STOPh]h.}hjsbah}(h]h ]h"]periodah$]h&]uh1hhhhK8hhhhubh)}(h*.. |plus| unicode:: U+0002B .. PLUS SIGNh]h+}hjsbah}(h]h ]h"]plusah$]h&]uh1hhhhK9hhhhubh)}(h0.. |plusmn| unicode:: U+000B1 .. PLUS-MINUS SIGNh]h±}hjsbah}(h]h ]h"]plusmnah$]h&]uh1hhhhK:hhhhubh)}(h+.. |pound| unicode:: U+000A3 .. POUND SIGNh]h£}hjsbah}(h]h ]h"]poundah$]h&]uh1hhhhK;hhhhubh)}(h... |quest| unicode:: U+0003F .. QUESTION MARKh]h?}hjsbah}(h]h ]h"]questah$]h&]uh1hhhhKhhhhubh)}(h1.. |rarr| unicode:: U+02192 .. RIGHTWARDS ARROWh]h→}hjsbah}(h]h ]h"]rarrah$]h&]uh1hhhhK?hhhhubh)}(h4.. |rcub| unicode:: U+0007D .. RIGHT CURLY BRACKETh]h}}hj*sbah}(h]h ]h"]rcubah$]h&]uh1hhhhK@hhhhubh)}(h<.. |rdquo| unicode:: U+0201D .. RIGHT DOUBLE QUOTATION MARKh]h”}hj9sbah}(h]h ]h"]rdquoah$]h&]uh1hhhhKAhhhhubh)}(h0.. |reg| unicode:: U+000AE .. REGISTERED SIGNh]h®}hjHsbah}(h]h ]h"]regah$]h&]uh1hhhhKBhhhhubh)}(h2.. |rpar| unicode:: U+00029 .. RIGHT PARENTHESISh]h)}hjWsbah}(h]h ]h"]rparah$]h&]uh1hhhhKChhhhubh)}(h5.. |rsqb| unicode:: U+0005D .. RIGHT SQUARE BRACKETh]h]}hjfsbah}(h]h ]h"]rsqbah$]h&]uh1hhhhKDhhhhubh)}(h<.. |rsquo| unicode:: U+02019 .. RIGHT SINGLE QUOTATION MARKh]h’}hjusbah}(h]h ]h"]rsquoah$]h&]uh1hhhhKEhhhhubh)}(h-.. |sect| unicode:: U+000A7 .. SECTION SIGNh]h§}hjsbah}(h]h ]h"]sectah$]h&]uh1hhhhKFhhhhubh)}(h*.. |semi| unicode:: U+0003B .. SEMICOLONh]h;}hjsbah}(h]h ]h"]semiah$]h&]uh1hhhhKGhhhhubh)}(h,.. |shy| unicode:: U+000AD .. SOFT HYPHENh]h­}hjsbah}(h]h ]h"]shyah$]h&]uh1hhhhKHhhhhubh)}(h(.. |sol| unicode:: U+0002F .. SOLIDUSh]h/}hjsbah}(h]h ]h"]solah$]h&]uh1hhhhKIhhhhubh)}(h,.. |sung| unicode:: U+0266A .. EIGHTH NOTEh]h♪}hjsbah}(h]h ]h"]sungah$]h&]uh1hhhhKJhhhhubh)}(h0.. |sup1| unicode:: U+000B9 .. SUPERSCRIPT ONEh]h¹}hjsbah}(h]h ]h"]sup1ah$]h&]uh1hhhhKKhhhhubh)}(h0.. |sup2| unicode:: U+000B2 .. SUPERSCRIPT TWOh]h²}hjsbah}(h]h ]h"]sup2ah$]h&]uh1hhhhKLhhhhubh)}(h2.. |sup3| unicode:: U+000B3 .. SUPERSCRIPT THREEh]h³}hjsbah}(h]h ]h"]sup3ah$]h&]uh1hhhhKMhhhhubh)}(h4.. |times| unicode:: U+000D7 .. MULTIPLICATION SIGNh]h×}hjsbah}(h]h ]h"]timesah$]h&]uh1hhhhKNhhhhubh)}(h0.. |trade| unicode:: U+02122 .. TRADE MARK SIGNh]h™}hj sbah}(h]h ]h"]tradeah$]h&]uh1hhhhKOhhhhubh)}(h... |uarr| unicode:: U+02191 .. UPWARDS ARROWh]h↑}hjsbah}(h]h ]h"]uarrah$]h&]uh1hhhhKPhhhhubh)}(h... |verbar| unicode:: U+0007C .. VERTICAL LINEh]h|}hj)sbah}(h]h ]h"]verbarah$]h&]uh1hhhhKQhhhhubh)}(h*.. |yen| unicode:: U+000A5 .. YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(hThe mgb4 driverh]hThe mgb4 driver}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubhdefinition_list)}(hhh]hdefinition_list_item)}(hiCopyright |copy| 2023 - 2025 Digiteq Automotive author: Martin Tůma h](hterm)}(h/Copyright |copy| 2023 - 2025 Digiteq Automotiveh](h Copyright }(hjihhhNhNubh©}(hjihhhNhNubh 2023 - 2025 Digiteq Automotive}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK hjcubh definition)}(hhh]h paragraph)}(h8author: Martin Tůma h](hauthor: Martin Tůma <}(hjhhhNhNubh reference)}(h!martin.tuma@digiteqautomotive.comh]h!martin.tuma@digiteqautomotive.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refuri(mailto:martin.tuma@digiteqautomotive.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jahhhK hj^ubah}(h]h ]h"]h$]h&]uh1j\hjIhhhhhNubj)}(hThis is a v4l2 device driver for the Digiteq Automotive FrameGrabber 4, a PCIe card capable of capturing and generating FPD-Link III and GMSL2/3 video streams as used in the automotive industry.h]hThis is a v4l2 device driver for the Digiteq Automotive FrameGrabber 4, a PCIe card capable of capturing and generating FPD-Link III and GMSL2/3 video streams as used in the automotive industry.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK hjIhhubjH)}(hhh](jM)}(hsysfs interfaceh]hsysfs interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj)}(hThe mgb4 driver provides a sysfs interface, that is used to configure video stream related parameters (some of them must be set properly before the v4l2 device can be opened) and obtain the video device/stream status.h]hThe mgb4 driver provides a sysfs interface, that is used to configure video stream related parameters (some of them must be set properly before the v4l2 device can be opened) and obtain the video device/stream status.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hThere are two types of parameters - global / PCI card related, found under ``/sys/class/video4linux/videoX/device`` and module specific found under ``/sys/class/video4linux/videoX``.h](hKThere are two types of parameters - global / PCI card related, found under }(hjhhhNhNubhliteral)}(h(``/sys/class/video4linux/videoX/device``h]h$/sys/class/video4linux/videoX/device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh! and module specific found under }(hjhhhNhNubj)}(h!``/sys/class/video4linux/videoX``h]h/sys/class/video4linux/videoX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubjH)}(hhh](jM)}(hGlobal (PCI card) parametersh]hGlobal (PCI card) parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj])}(hhh](jb)}(hX**module_type** (R): Module type. | 0 - No module present | 1 - FPDL3 | 2 - GMSL3 (one serializer, two daisy chained deserializers) | 3 - GMSL3 (one serializer, two deserializers) | 4 - GMSL3 (two deserializers with two daisy chain outputs) | 6 - GMSL1 | 8 - GMSL3 coax h](jh)}(h**module_type** (R):h](hstrong)}(h**module_type**h]h module_type}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj5ubh (R):}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK&hj1ubj)}(hhh](j)}(h Module type.h]h Module type.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjSubh line_block)}(hhh](hh)}(h0 - No module presenth]h0 - No module present}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjfhhhKubji)}(h 1 - FPDL3h]h 1 - FPDL3}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjfhhhKubji)}(h;2 - GMSL3 (one serializer, two daisy chained deserializers)h]h;2 - GMSL3 (one serializer, two daisy chained deserializers)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjfhhhKubji)}(h-3 - GMSL3 (one serializer, two deserializers)h]h-3 - GMSL3 (one serializer, two deserializers)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjfhhhKubji)}(h:4 - GMSL3 (two deserializers with two daisy chain outputs)h]h:4 - GMSL3 (two deserializers with two daisy chain outputs)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjfhhhKubji)}(h 6 - GMSL1h]h 6 - GMSL1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjfhhhKubji)}(h8 - GMSL3 coaxh]h8 - GMSL3 coax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjfhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjSubeh}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jahhhK&hj.ubjb)}(hQ**module_version** (R): Module version number. Zero in case of a missing module. h](jh)}(h**module_version** (R):h](j:)}(h**module_version**h]hmodule_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK)hjubj)}(hhh]j)}(h8Module version number. Zero in case of a missing module.h]h8Module version number. Zero in case of a missing module.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhK)hj.hhubjb)}(hE**fw_type** (R): Firmware type. | 1 - FPDL3 | 2 - GMSL3 | 3 - GMSL1 h](jh)}(h**fw_type** (R):h](j:)}(h **fw_type**h]hfw_type}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK0hjubj)}(hhh](j)}(hFirmware type.h]hFirmware type.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK,hj<ubje)}(hhh](ji)}(h 1 - FPDL3h]h 1 - FPDL3}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubji)}(h 2 - GMSL3h]h 2 - GMSL3}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubji)}(h 3 - GMSL1h]h 3 - GMSL1}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubeh}(h]h ]h"]h$]h&]uh1jdhj<ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhK0hj.hhubjb)}(h-**fw_version** (R): Firmware version number. h](jh)}(h**fw_version** (R):h](j:)}(h**fw_version**h]h fw_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK3hjubj)}(hhh]j)}(hFirmware version number.h]hFirmware version number.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhK3hj.hhubjb)}(h**serial_number** (R): Card serial number. The format is:: PRODUCT-REVISION-SERIES-SERIAL where each component is a 8b number. h](jh)}(h**serial_number** (R):h](j:)}(h**serial_number**h]h serial_number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK:hjubj)}(hhh](j)}(h#Card serial number. The format is::h]h"Card serial number. The format is:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK6hjubh literal_block)}(hPRODUCT-REVISION-SERIES-SERIALh]hPRODUCT-REVISION-SERIES-SERIAL}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK8hjubj)}(h$where each component is a 8b number.h]h$where each component is a 8b number.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK:hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhK:hj.hhubeh}(h]h ]h"]h$]h&]uh1j\hjhhhhhNubeh}(h]global-pci-card-parametersah ]h"]global (pci card) parametersah$]h&]uh1jGhjhhhhhKubjH)}(hhh](jM)}(h"Common FPDL3/GMSL input parametersh]h"Common FPDL3/GMSL input parameters}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj2hhhhhK=ubj])}(hhh](jb)}(h/**input_id** (R): Input number ID, zero based. h](jh)}(h**input_id** (R):h](j:)}(h **input_id**h]hinput_id}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjJubh (R):}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhK@hjFubj)}(hhh]j)}(hInput number ID, zero based.h]hInput number ID, zero based.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK@hjfubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jahhhK@hjCubjb)}(hb**oldi_lane_width** (RW): Number of deserializer output lanes. | 0 - single | 1 - dual (default) h](jh)}(h**oldi_lane_width** (RW):h](j:)}(h**oldi_lane_width**h]holdi_lane_width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKFhjubj)}(hhh](j)}(h$Number of deserializer output lanes.h]h$Number of deserializer output lanes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKChjubje)}(hhh](ji)}(h 0 - singleh]h 0 - single}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h1 - dual (default)h]h1 - dual (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhKFhjChhubjb)}(h**color_mapping** (RW): Mapping of the incoming bits in the signal to the colour bits of the pixels. | 0 - OLDI/JEIDA | 1 - SPWG/VESA (default) h](jh)}(h**color_mapping** (RW):h](j:)}(h**color_mapping**h]h color_mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKLhjubj)}(hhh](j)}(hLMapping of the incoming bits in the signal to the colour bits of the pixels.h]hLMapping of the incoming bits in the signal to the colour bits of the pixels.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKIhj ubje)}(hhh](ji)}(h0 - OLDI/JEIDAh]h0 - OLDI/JEIDA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h1 - SPWG/VESA (default)h]h1 - SPWG/VESA (default)}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jdhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhKLhjChhubjb)}(hXG**link_status** (R): Video link status. If the link is locked, chips are properly connected and communicating at the same speed and protocol. The link can be locked without an active video stream. A value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2 VIDIOC_ENUMINPUT status bits. | 0 - unlocked | 1 - locked h](jh)}(h**link_status** (R):h](j:)}(h**link_status**h]h link_status}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjK ubh (R):}(hjK hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKWhjG ubj)}(hhh](j)}(hVideo link status. If the link is locked, chips are properly connected and communicating at the same speed and protocol. The link can be locked without an active video stream.h]hVideo link status. If the link is locked, chips are properly connected and communicating at the same speed and protocol. The link can be locked without an active video stream.}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKOhjg ubj)}(hcA value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2 VIDIOC_ENUMINPUT status bits.h]hcA value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2 VIDIOC_ENUMINPUT status bits.}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKShjg ubje)}(hhh](ji)}(h 0 - unlockedh]h 0 - unlocked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h 1 - lockedh]h 1 - locked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jdhjg ubeh}(h]h ]h"]h$]h&]uh1jhjG ubeh}(h]h ]h"]h$]h&]uh1jahhhKWhjChhubjb)}(hX **stream_status** (R): Video stream status. A stream is detected if the link is locked, the input pixel clock is running and the DE signal is moving. A value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2 VIDIOC_ENUMINPUT status bits. | 0 - not detected | 1 - detected h](jh)}(h**stream_status** (R):h](j:)}(h**stream_status**h]h stream_status}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKahj ubj)}(hhh](j)}(h~Video stream status. A stream is detected if the link is locked, the input pixel clock is running and the DE signal is moving.h]h~Video stream status. A stream is detected if the link is locked, the input pixel clock is running and the DE signal is moving.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKZhj ubj)}(heA value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2 VIDIOC_ENUMINPUT status bits.h]heA value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2 VIDIOC_ENUMINPUT status bits.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK]hj ubje)}(hhh](ji)}(h0 - not detectedh]h0 - not detected}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h 1 - detectedh]h 1 - detected}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jdhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKahjChhubjb)}(h**video_width** (R): Video stream width. This is the actual width as detected by the HW. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width field of the v4l2_bt_timings struct. h](jh)}(h**video_width** (R):h](j:)}(h**video_width**h]h video_width}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj+ ubh (R):}(hj+ hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKghj' ubj)}(hhh](j)}(hCVideo stream width. This is the actual width as detected by the HW.h]hCVideo stream width. This is the actual width as detected by the HW.}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKdhjG ubj)}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width field of the v4l2_bt_timings struct.}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKfhjG ubeh}(h]h ]h"]h$]h&]uh1jhj' ubeh}(h]h ]h"]h$]h&]uh1jahhhKghjChhubjb)}(h**video_height** (R): Video stream height. This is the actual height as detected by the HW. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height field of the v4l2_bt_timings struct. h](jh)}(h**video_height** (R):h](j:)}(h**video_height**h]h video_height}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjv ubh (R):}(hjv hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKmhjr ubj)}(hhh](j)}(hEVideo stream height. This is the actual height as detected by the HW.h]hEVideo stream height. This is the actual height as detected by the HW.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKjhj ubj)}(hqThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height field of the v4l2_bt_timings struct.h]hqThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the height field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKlhj ubeh}(h]h ]h"]h$]h&]uh1jhjr ubeh}(h]h ]h"]h$]h&]uh1jahhhKmhjChhubjb)}(hX**vsync_status** (R): The type of VSYNC pulses as detected by the video format detector. The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct. | 0 - active low | 1 - active high | 2 - not available h](jh)}(h**vsync_status** (R):h](j:)}(h**vsync_status**h]h vsync_status}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKwhj ubj)}(hhh](j)}(hBThe type of VSYNC pulses as detected by the video format detector.h]hBThe type of VSYNC pulses as detected by the video format detector.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKphj ubj)}(hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.h]hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKrhj ubje)}(hhh](ji)}(h0 - active lowh]h0 - active low}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h1 - active highh]h1 - active high}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h2 - not availableh]h2 - not available}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jdhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKwhjChhubjb)}(hX**hsync_status** (R): The type of HSYNC pulses as detected by the video format detector. The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct. | 0 - active low | 1 - active high | 2 - not available h](jh)}(h**hsync_status** (R):h](j:)}(h**hsync_status**h]h hsync_status}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj? ubh (R):}(hj? hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj; ubj)}(hhh](j)}(hBThe type of HSYNC pulses as detected by the video format detector.h]hBThe type of HSYNC pulses as detected by the video format detector.}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKzhj[ ubj)}(hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.h]hThe value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in the polarities field of the v4l2_bt_timings struct.}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK|hj[ ubje)}(hhh](ji)}(h0 - active lowh]h0 - active low}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjz hhhKubji)}(h1 - active highh]h1 - active high}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjz hhhKubji)}(h2 - not availableh]h2 - not available}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjz hhhKubeh}(h]h ]h"]h$]h&]uh1jdhj[ ubeh}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hXU**vsync_gap_length** (RW): If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal VSYNC pulse. h](jh)}(h**vsync_gap_length** (RW):h](j:)}(h**vsync_gap_length**h]hvsync_gap_length}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj ubj)}(hhh]j)}(hX9If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal VSYNC pulse.h]hX=If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many “empty” pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal VSYNC pulse.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX**hsync_gap_length** (RW): If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal HSYNC pulse. The value must be greater than 1 and smaller than vsync_gap_length. h](jh)}(h**hsync_gap_length** (RW):h](j:)}(h**hsync_gap_length**h]hhsync_gap_length}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (RW):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj ubj)}(hhh]j)}(hX}If the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many "empty" pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal HSYNC pulse. The value must be greater than 1 and smaller than vsync_gap_length.h]hXIf the incoming video signal does not contain synchronization VSYNC and HSYNC pulses, these must be generated internally in the FPGA to achieve the correct frame ordering. This value indicates, how many “empty” pixels (pixels with deasserted Data Enable signal) are necessary to generate the internal HSYNC pulse. The value must be greater than 1 and smaller than vsync_gap_length.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX**pclk_frequency** (R): Input pixel clock frequency in kHz. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the pixelclock field of the v4l2_bt_timings struct. *Note: The frequency_range parameter must be set properly first to get a valid frequency here.* h](jh)}(h**pclk_frequency** (R):h](j:)}(h**pclk_frequency**h]hpclk_frequency}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj7 ubh (R):}(hj7 hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj3 ubj)}(hhh](j)}(h#Input pixel clock frequency in kHz.h]h#Input pixel clock frequency in kHz.}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjS ubj)}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the pixelclock field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the pixelclock field of the v4l2_bt_timings struct.}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjS ubj)}(h_*Note: The frequency_range parameter must be set properly first to get a valid frequency here.*h]hemphasis)}(hjt h]h]Note: The frequency_range parameter must be set properly first to get a valid frequency here.}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjr ubah}(h]h ]h"]h$]h&]uh1jhhhKhjS ubeh}(h]h ]h"]h$]h&]uh1jhj3 ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(h**hsync_width** (R): Width of the HSYNC signal in PCLK clock ticks. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hsync field of the v4l2_bt_timings struct. h](jh)}(h**hsync_width** (R):h](j:)}(h**hsync_width**h]h hsync_width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj ubj)}(hhh](j)}(h.Width of the HSYNC signal in PCLK clock ticks.h]h.Width of the HSYNC signal in PCLK clock ticks.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hsync field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hsync field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(h**vsync_width** (R): Width of the VSYNC signal in PCLK clock ticks. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vsync field of the v4l2_bt_timings struct. h](jh)}(h**vsync_width** (R):h](j:)}(h**vsync_width**h]h vsync_width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj ubj)}(hhh](j)}(h.Width of the VSYNC signal in PCLK clock ticks.h]h.Width of the VSYNC signal in PCLK clock ticks.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vsync field of the v4l2_bt_timings struct.h]hpThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vsync field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX**hback_porch** (R): Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hbackporch field of the v4l2_bt_timings struct. h](jh)}(h**hback_porch** (R):h](j:)}(h**hback_porch**h]h hback_porch}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj1 ubh (R):}(hj1 hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj- ubj)}(hhh](j)}(h{Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1).h]h{Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1).}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjM ubj)}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hbackporch field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hbackporch field of the v4l2_bt_timings struct.}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjM ubeh}(h]h ]h"]h$]h&]uh1jhj- ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX**hfront_porch** (R): Number of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hfrontporch field of the v4l2_bt_timings struct. h](jh)}(h**hfront_porch** (R):h](j:)}(h**hfront_porch**h]h hfront_porch}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj| ubh (R):}(hj| hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjx ubj)}(hhh](j)}(hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal.h]hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hfrontporch field of the v4l2_bt_timings struct.h]hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the hfrontporch field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhjx ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX **vback_porch** (R): Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vbackporch field of the v4l2_bt_timings struct. h](jh)}(h**vback_porch** (R):h](j:)}(h**vback_porch**h]h vback_porch}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh (R):}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj ubj)}(hhh](j)}(h}Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1).h]h}Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vbackporch field of the v4l2_bt_timings struct.h]huThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vbackporch field of the v4l2_bt_timings struct.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX**vfront_porch** (R): Number of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vfrontporch field of the v4l2_bt_timings struct. h](jh)}(h**vfront_porch** (R):h](j:)}(h**vfront_porch**h]h vfront_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjubj)}(hhh](j)}(hvNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal.h]hvNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj.ubj)}(hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vfrontporch field of the v4l2_bt_timings struct.h]hvThe value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the vfrontporch field of the v4l2_bt_timings struct.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubjb)}(hX~**frequency_range** (RW) PLL frequency range of the OLDI input clock generator. The PLL frequency is derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to "dual". | 0 - PLL < 50MHz (default) | 1 - PLL >= 50MHz *Note: This parameter can not be changed while the input v4l2 device is open.* h](jh)}(h**frequency_range** (RW)h](j:)}(h**frequency_range**h]hfrequency_range}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj]ubh (RW)}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjYubj)}(hhh](j)}(hPLL frequency range of the OLDI input clock generator. The PLL frequency is derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to "dual".h]hPLL frequency range of the OLDI input clock generator. The PLL frequency is derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if oldi_lane_width is set to “single” and PCLK/2 if oldi_lane_width is set to “dual”.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjyubje)}(hhh](ji)}(h0 - PLL < 50MHz (default)h]h0 - PLL < 50MHz (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h1 - PLL >= 50MHzh]h1 - PLL >= 50MHz}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjyubj)}(hN*Note: This parameter can not be changed while the input v4l2 device is open.*h]jw )}(hjh]hLNote: This parameter can not be changed while the input v4l2 device is open.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubah}(h]h ]h"]h$]h&]uh1jhhhKhjyubeh}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jahhhKhjChhubeh}(h]h ]h"]h$]h&]uh1j\hj2hhhhhNubeh}(h]"common-fpdl3-gmsl-input-parametersah ]h"]"common fpdl3/gmsl input parametersah$]h&]uh1jGhjhhhhhK=ubjH)}(hhh](jM)}(h#Common FPDL3/GMSL output parametersh]h#Common FPDL3/GMSL output parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj])}(hhh](jb)}(h1**output_id** (R): Output number ID, zero based. h](jh)}(h**output_id** (R):h](j:)}(h **output_id**h]h output_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (R):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjubj)}(hhh]j)}(hOutput number ID, zero based.h]hOutput number ID, zero based.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhKhjubjb)}(hX**video_source** (RW): Output video source. If set to 0 or 1, the source is the corresponding card input and the v4l2 output devices are disabled. If set to 2 or 3, the source is the corresponding v4l2 video output device. The default is the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2. | 0 - input 0 | 1 - input 1 | 2 - v4l2 output 0 | 3 - v4l2 output 1 *Note: This parameter can not be changed while ANY of the input/output v4l2 devices is open.* h](jh)}(h**video_source** (RW):h](j:)}(h**video_source**h]h video_source}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj5ubh (RW):}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhj1ubj)}(hhh](j)}(hXOutput video source. If set to 0 or 1, the source is the corresponding card input and the v4l2 output devices are disabled. If set to 2 or 3, the source is the corresponding v4l2 video output device. The default is the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.h]hXOutput video source. If set to 0 or 1, the source is the corresponding card input and the v4l2 output devices are disabled. If set to 2 or 3, the source is the corresponding v4l2 video output device. The default is the corresponding v4l2 output, i.e. 2 for OUT1 and 3 for OUT2.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjQubje)}(hhh](ji)}(h 0 - input 0h]h 0 - input 0}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjbhhhKubji)}(h 1 - input 1h]h 1 - input 1}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjbhhhKubji)}(h2 - v4l2 output 0h]h2 - v4l2 output 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjbhhhKubji)}(h3 - v4l2 output 1h]h3 - v4l2 output 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjbhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjQubj)}(h]*Note: This parameter can not be changed while ANY of the input/output v4l2 devices is open.*h]jw )}(hjh]h[Note: This parameter can not be changed while ANY of the input/output v4l2 devices is open.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubah}(h]h ]h"]h$]h&]uh1jhhhKhjQubeh}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jahhhKhjhhubjb)}(hX**display_width** (RW): Display width. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default width is 1280. *Note: This parameter can not be changed while the output v4l2 device is open.* h](jh)}(h**display_width** (RW):h](j:)}(h**display_width**h]h display_width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjubj)}(hhh](j)}(hDisplay width. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default width is 1280.h]hDisplay width. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default width is 1280.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hO*Note: This parameter can not be changed while the output v4l2 device is open.*h]jw )}(hjh]hMNote: This parameter can not be changed while the output v4l2 device is open.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhKhjhhubjb)}(hX**display_height** (RW): Display height. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default height is 640. *Note: This parameter can not be changed while the output v4l2 device is open.* h](jh)}(h**display_height** (RW):h](j:)}(h**display_height**h]hdisplay_height}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjubj)}(hhh](j)}(hDisplay height. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default height is 640.h]hDisplay height. There is no autodetection of the connected display, so the proper value must be set before the start of streaming. The default height is 640.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj:ubj)}(hO*Note: This parameter can not be changed while the output v4l2 device is open.*h]jw )}(hjMh]hMNote: This parameter can not be changed while the output v4l2 device is open.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjKubah}(h]h ]h"]h$]h&]uh1jhhhKhj:ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhKhjhhubjb)}(hX**frame_rate** (RW): Output video signal frame rate limit in frames per second. Due to the limited output pixel clock steps, the card can not always generate a frame rate perfectly matching the value required by the connected display. Using this parameter one can limit the frame rate by "crippling" the signal so that the lines are not equal (the porches of the last line differ) but the signal appears like having the exact frame rate to the connected display. The default frame rate limit is 60Hz. h](jh)}(h**frame_rate** (RW):h](j:)}(h**frame_rate**h]h frame_rate}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjrubh (RW):}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhKhjnubj)}(hhh]j)}(hXOutput video signal frame rate limit in frames per second. Due to the limited output pixel clock steps, the card can not always generate a frame rate perfectly matching the value required by the connected display. Using this parameter one can limit the frame rate by "crippling" the signal so that the lines are not equal (the porches of the last line differ) but the signal appears like having the exact frame rate to the connected display. The default frame rate limit is 60Hz.h]hXOutput video signal frame rate limit in frames per second. Due to the limited output pixel clock steps, the card can not always generate a frame rate perfectly matching the value required by the connected display. Using this parameter one can limit the frame rate by “crippling” the signal so that the lines are not equal (the porches of the last line differ) but the signal appears like having the exact frame rate to the connected display. The default frame rate limit is 60Hz.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jahhhKhjhhubjb)}(h^**hsync_polarity** (RW): HSYNC signal polarity. | 0 - active low (default) | 1 - active high h](jh)}(h**hsync_polarity** (RW):h](j:)}(h**hsync_polarity**h]hhsync_polarity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMhjubj)}(hhh](j)}(hHSYNC signal polarity.h]hHSYNC signal polarity.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubje)}(hhh](ji)}(h0 - active low (default)h]h0 - active low (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h1 - active highh]h1 - active high}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhMhjhhubjb)}(h^**vsync_polarity** (RW): VSYNC signal polarity. | 0 - active low (default) | 1 - active high h](jh)}(h**vsync_polarity** (RW):h](j:)}(h**vsync_polarity**h]hvsync_polarity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMhj ubj)}(hhh](j)}(hVSYNC signal polarity.h]hVSYNC signal polarity.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-ubje)}(hhh](ji)}(h0 - active low (default)h]h0 - active low (default)}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj>hhhKubji)}(h1 - active highh]h1 - active high}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj>hhhKubeh}(h]h ]h"]h$]h&]uh1jdhj-ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jahhhMhjhhubjb)}(hX**de_polarity** (RW): DE signal polarity. | 0 - active low | 1 - active high (default) h](jh)}(h**de_polarity** (RW):h](j:)}(h**de_polarity**h]h de_polarity}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjsubh (RW):}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhM hjoubj)}(hhh](j)}(hDE signal polarity.h]hDE signal polarity.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubje)}(hhh](ji)}(h0 - active lowh]h0 - active low}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h1 - active high (default)h]h1 - active high (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjubeh}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jahhhM hjhhubjb)}(hX**pclk_frequency** (RW): Output pixel clock frequency. Allowed values are between 25000-190000(kHz) and there is a non-linear stepping between two consecutive allowed frequencies. The driver finds the nearest allowed frequency to the given value and sets it. When reading this property, you get the exact frequency set by the driver. The default frequency is 61150kHz. *Note: This parameter can not be changed while the output v4l2 device is open.* h](jh)}(h**pclk_frequency** (RW):h](j:)}(h**pclk_frequency**h]hpclk_frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMhjubj)}(hhh](j)}(hXWOutput pixel clock frequency. Allowed values are between 25000-190000(kHz) and there is a non-linear stepping between two consecutive allowed frequencies. The driver finds the nearest allowed frequency to the given value and sets it. When reading this property, you get the exact frequency set by the driver. The default frequency is 61150kHz.h]hXWOutput pixel clock frequency. Allowed values are between 25000-190000(kHz) and there is a non-linear stepping between two consecutive allowed frequencies. The driver finds the nearest allowed frequency to the given value and sets it. When reading this property, you get the exact frequency set by the driver. The default frequency is 61150kHz.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hO*Note: This parameter can not be changed while the output v4l2 device is open.*h]jw )}(hjh]hMNote: This parameter can not be changed while the output v4l2 device is open.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhMhjhhubjb)}(hT**hsync_width** (RW): Width of the HSYNC signal in pixels. The default value is 40. h](jh)}(h**hsync_width** (RW):h](j:)}(h**hsync_width**h]h hsync_width}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj)ubh (RW):}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMhj%ubj)}(hhh]j)}(h=Width of the HSYNC signal in pixels. The default value is 40.h]h=Width of the HSYNC signal in pixels. The default value is 40.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jahhhMhjhhubjb)}(hY**vsync_width** (RW): Width of the VSYNC signal in video lines. The default value is 20. h](jh)}(h**vsync_width** (RW):h](j:)}(h**vsync_width**h]h vsync_width}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjfubh (RW):}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMhjbubj)}(hhh]j)}(hBWidth of the VSYNC signal in video lines. The default value is 20.h]hBWidth of the VSYNC signal in video lines. The default value is 20.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jahhhMhjhhubjb)}(h**hback_porch** (RW): Number of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The default value is 50. h](jh)}(h**hback_porch** (RW):h](j:)}(h**hback_porch**h]h hback_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhM hjubj)}(hhh]j)}(hNumber of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The default value is 50.h]hNumber of PCLK pulses between deassertion of the HSYNC signal and the first valid pixel in the video line (marked by DE=1). The default value is 50.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhM hjhhubjb)}(h**hfront_porch** (RW): Number of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The default value is 50. h](jh)}(h**hfront_porch** (RW):h](j:)}(h**hfront_porch**h]h hfront_porch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhM%hjubj)}(hhh]j)}(hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The default value is 50.h]hNumber of PCLK pulses between the end of the last valid pixel in the video line (marked by DE=1) and assertion of the HSYNC signal. The default value is 50.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjube@Qh}(h]h ]h"]h$]h&]uh1jahhhM%hjhhubjb)}(h**vback_porch** (RW): Number of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The default value is 31. h](jh)}(h**vback_porch** (RW):h](j:)}(h**vback_porch**h]h vback_porch}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhM)hjubj)}(hhh]j)}(hNumber of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The default value is 31.h]hNumber of video lines between deassertion of the VSYNC signal and the video line with the first valid pixel (marked by DE=1). The default value is 31.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM(hj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhM)hjhhubjb)}(h**vfront_porch** (RW): Number of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The default value is 30. h](jh)}(h**vfront_porch** (RW):h](j:)}(h**vfront_porch**h]h vfront_porch}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjZubh (RW):}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhM-hjVubj)}(hhh]j)}(hNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The default value is 30.h]hNumber of video lines between the end of the last valid pixel line (marked by DE=1) and assertion of the VSYNC signal. The default value is 30.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM,hjvubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jahhhM-hjhhubeh}(h]h ]h"]h$]h&]uh1j\hjhhhhhNubeh}(h]#common-fpdl3-gmsl-output-parametersah ]h"]#common fpdl3/gmsl output parametersah$]h&]uh1jGhjhhhhhKubjH)}(hhh](jM)}(hFPDL3 specific input parametersh]hFPDL3 specific input parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhM0ubj])}(hhh]jb)}(hn**fpdl3_input_width** (RW): Number of deserializer input lines. | 0 - auto (default) | 1 - single | 2 - dual h](jh)}(h**fpdl3_input_width** (RW):h](j:)}(h**fpdl3_input_width**h]hfpdl3_input_width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhM7hjubj)}(hhh](j)}(h#Number of deserializer input lines.h]h#Number of deserializer input lines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM3hjubje)}(hhh](ji)}(h0 - auto (default)h]h0 - auto (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h 1 - singleh]h 1 - single}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h2 - dualh]h2 - dual}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhM7hjubah}(h]h ]h"]h$]h&]uh1j\hjhhhhhNubeh}(h]fpdl3-specific-input-parametersah ]h"]fpdl3 specific input parametersah$]h&]uh1jGhjhhhhhM0ubjH)}(hhh](jM)}(h FPDL3 specific output parametersh]h FPDL3 specific output parameters}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj3hhhhhM:ubj])}(hhh]jb)}(hn**fpdl3_output_width** (RW): Number of serializer output lines. | 0 - auto (default) | 1 - single | 2 - dual h](jh)}(h**fpdl3_output_width** (RW):h](j:)}(h**fpdl3_output_width**h]hfpdl3_output_width}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjKubh (RW):}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMAhjGubj)}(hhh](j)}(h"Number of serializer output lines.h]h"Number of serializer output lines.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM=hjgubje)}(hhh](ji)}(h0 - auto (default)h]h0 - auto (default)}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjxhhhKubji)}(h 1 - singleh]h 1 - single}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjxhhhKubji)}(h2 - dualh]h2 - dual}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjxhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjgubeh}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jahhhMAhjDubah}(h]h ]h"]h$]h&]uh1j\hj3hhhhhNubeh}(h] fpdl3-specific-output-parametersah ]h"] fpdl3 specific output parametersah$]h&]uh1jGhjhhhhhM:ubjH)}(hhh](jM)}(hGMSL specific input parametersh]hGMSL specific input parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhMDubj])}(hhh](jb)}(hc**gmsl_mode** (RW): GMSL speed mode. | 0 - 12Gb/s (default) | 1 - 6Gb/s | 2 - 3Gb/s | 3 - 1.5Gb/s h](jh)}(h**gmsl_mode** (RW):h](j:)}(h **gmsl_mode**h]h gmsl_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMLhjubj)}(hhh](j)}(hGMSL speed mode.h]hGMSL speed mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMGhjubje)}(hhh](ji)}(h0 - 12Gb/s (default)h]h0 - 12Gb/s (default)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h 1 - 6Gb/sh]h 1 - 6Gb/s}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h 2 - 3Gb/sh]h 2 - 3Gb/s}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubji)}(h 3 - 1.5Gb/sh]h 3 - 1.5Gb/s}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhj hhhKubeh}(h]h ]h"]h$]h&]uh1jdhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhMLhjubjb)}(hX3**gmsl_stream_id** (RW): The GMSL multi-stream contains up to four video streams. This parameter selects which stream is captured by the video input. The value is the zero-based index of the stream. The default stream id is 0. *Note: This parameter can not be changed while the input v4l2 device is open.* h](jh)}(h**gmsl_stream_id** (RW):h](j:)}(h**gmsl_stream_id**h]hgmsl_stream_id}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj[ubh (RW):}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMThjWubj)}(hhh](j)}(hThe GMSL multi-stream contains up to four video streams. This parameter selects which stream is captured by the video input. The value is the zero-based index of the stream. The default stream id is 0.h]hThe GMSL multi-stream contains up to four video streams. This parameter selects which stream is captured by the video input. The value is the zero-based index of the stream. The default stream id is 0.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMOhjwubj)}(hN*Note: This parameter can not be changed while the input v4l2 device is open.*h]jw )}(hjh]hLNote: This parameter can not be changed while the input v4l2 device is open.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubah}(h]h ]h"]h$]h&]uh1jhhhMShjwubeh}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jahhhMThjhhubjb)}(h`**gmsl_fec** (RW): GMSL Forward Error Correction (FEC). | 0 - disabled | 1 - enabled (default) h](jh)}(h**gmsl_fec** (RW):h](j:)}(h **gmsl_fec**h]hgmsl_fec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh (RW):}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMZhjubj)}(hhh](j)}(h$GMSL Forward Error Correction (FEC).h]h$GMSL Forward Error Correction (FEC).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMWhjubje)}(hhh](ji)}(h 0 - disabledh]h 0 - disabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubji)}(h1 - enabled (default)h]h1 - enabled (default)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jdhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhMZhjhhubeh}(h]h ]h"]h$]h&]uh1j\hjhhhhhNubeh}(h]gmsl-specific-input-parametersah ]h"]gmsl specific input parametersah$]h&]uh1jGhjhhhhhMDubeh}(h]sysfs-interfaceah ]h"]sysfs interfaceah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(hMTD partitionsh]hMTD partitions}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj#hhhhhM]ubj])}(hhh]jb)}(hThe mgb4 driver creates a MTD device with two partitions: - mgb4-fw.X - FPGA firmware. - mgb4-data.X - Factory settings, e.g. card serial number. h](jh)}(h9The mgb4 driver creates a MTD device with two partitions:h]h9The mgb4 driver creates a MTD device with two partitions:}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jghhhMahj7ubj)}(hhh]h bullet_list)}(hhh](h list_item)}(hmgb4-fw.X - FPGA firmware.h]j)}(hjUh]hmgb4-fw.X - FPGA firmware.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM`hjSubah}(h]h ]h"]h$]h&]uh1jQhjNubjR)}(h9mgb4-data.X - Factory settings, e.g. card serial number. h]j)}(h8mgb4-data.X - Factory settings, e.g. card serial number.h]h8mgb4-data.X - Factory settings, e.g. card serial number.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMahjjubah}(h]h ]h"]h$]h&]uh1jQhjNubeh}(h]h ]h"]h$]h&]bullet-uh1jLhhhM`hjIubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jahhhMahj4ubah}(h]h ]h"]h$]h&]uh1j\hj#hhhNhNubj)}(hXThe *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is read-only. The *X* attached to the partition name represents the card number. Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may also have a third partition named *mgb4-flash* available in the system. This partition represents the whole, unpartitioned, card's FLASH memory and one should not fiddle with it...h](hThe }(hjhhhNhNubjw )}(h *mgb4-fw*h]hmgb4-fw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubh3 partition is writable and is used for FW updates, }(hjhhhNhNubjw )}(h *mgb4-data*h]h mgb4-data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubh is read-only. The }(hjhhhNhNubjw )}(h*X*h]hX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubh attached to the partition name represents the card number. Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may also have a third partition named }(hjhhhNhNubjw )}(h *mgb4-flash*h]h mgb4-flash}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubh available in the system. This partition represents the whole, unpartitioned, card’s FLASH memory and one should not fiddle with it...}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMchj#hhubeh}(h]mtd-partitionsah ]h"]mtd partitionsah$]h&]uh1jGhjIhhhhhM]ubjH)}(hhh](jM)}(hIIO (triggers)h]hIIO (triggers)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhMkubj)}(hThe mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and signal level status capability. The following scan elements are available:h]hThe mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and signal level status capability. The following scan elements are available:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMmhjhhubj])}(hhh](jb)}(h**activity**: The trigger levels and pending status. | bit 1 - trigger 1 pending | bit 2 - trigger 2 pending | bit 5 - trigger 1 level | bit 6 - trigger 2 level h](jh)}(h **activity**:h](j:)}(h **activity**h]hactivity}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j9hj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMvhjubj)}(hhh](j)}(h&The trigger levels and pending status.h]h&The trigger levels and pending status.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMqhj<ubje)}(hhh](ji)}(hbit 1 - trigger 1 pendingh]hbit 1 - trigger 1 pending}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubji)}(hbit 2 - trigger 2 pendingh]hbit 2 - trigger 2 pending}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubji)}(hbit 5 - trigger 1 levelh]hbit 5 - trigger 1 level}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubji)}(hbit 6 - trigger 2 levelh]hbit 6 - trigger 2 level}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hjxKhjMhhhKubeh}(h]h ]h"]h$]h&]uh1jdhj<ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhMvhjubjb)}(h,**timestamp**: The trigger event timestamp. h](jh)}(h**timestamp**:h](j:)}(h **timestamp**h]h timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j9hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jghhhMyhjubj)}(hhh]j)}(hThe trigger event timestamp.h]hThe trigger event timestamp.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMyhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jahhhMyhjhhubeh}(h]h ]h"]h$]h&]uh1j\hjhhhhhNubj)}(hXThe iio device can operate either in "raw" mode where you can fetch the signal levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode. In the triggered buffer mode you can follow the signal level changes (activity bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you will also get the exact trigger event time that can be matched to a video frame (every mgb4 video frame has a timestamp with the same clock source).h]hXThe iio device can operate either in “raw” mode where you can fetch the signal levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode. In the triggered buffer mode you can follow the signal level changes (activity bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you will also get the exact trigger event time that can be matched to a video frame (every mgb4 video frame has a timestamp with the same clock source).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM{hjhhubj)}(h*Note: although the activity sample always contains all the status bits, it makes no sense to get the pending bits in raw mode or the level bits in the triggered buffer mode - the values do not represent valid data in such case.*h]jw )}(hjh]hNote: although the activity sample always contains all the status bits, it makes no sense to get the pending bits in raw mode or the level bits in the triggered buffer mode - the values do not represent valid data in such case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jv hjubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubeh}(h] iio-triggersah ]h"]iio (triggers)ah$]h&]uh1jGhjIhhhhhMkubeh}(h]the-mgb4-driverah ]h"]the mgb4 driverah$]h&]uh1jGhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(jLN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj5error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}(hhhhhhj jjjj*jj9j-jHj<jWjKjfjZjujijjxjjjjjjjjjjjjjjjjj jjjj)jj8j,jGj;jVjJjejYjtjhjjwjjjjjjjjjjjjjjjjj jjj j(jj7j+jFj:jUjIjdjXjsjgjjvjjjjjjjjjjjjjjjjj jjj j'jj6j*jEj9jTjHjcjWjrjfjjujjjjjjjjjjjjjjjjjjjj j&jj5j)jDj8usubstitution_names}(amphߌaposhasthbrvbarj bsoljcentj*colonj9commajHcommatjWcopyjfcurrenjudarrjdegjdividejdollarjequalsjexcljfrac12jfrac14jfrac18jfrac34j frac38jfrac58j)frac78j8gtjGhalfjVhorbarjehyphenjtiexcljiquestjlaquojlarrjlcubjldquojlowbarjlparjlsqbjlsquoj ltjmicroj(middotj7nbspjFnotjUnumjdohmjsordfjordmjparajpercntjperiodjplusjplusmnjpoundjquestjquotj raquojrarrj'rcubj6rdquojEregjTrparjcrsqbjrrsquojsectjsemijshyjsoljsungjsup1jsup2jsup3jtimesjtradejuarrj&verbarj5yenjDurefnames}refids}nameids}(jj j jj/j,jjjjj0j-jjjjjjjju nametypes}(jj j/jjj0jjjjuh}(j jIjjj,jjj2jjj-jjj3jjjj#jju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log](Documentation/admin-guide/media/mgb4.rst(NNNNta decorationNhhub.