jsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget7/translations/zh_CN/admin-guide/hw-vuln/tsx_async_abortmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/zh_TW/admin-guide/hw-vuln/tsx_async_abortmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/it_IT/admin-guide/hw-vuln/tsx_async_abortmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/ja_JP/admin-guide/hw-vuln/tsx_async_abortmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/ko_KR/admin-guide/hw-vuln/tsx_async_abortmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/sp_SP/admin-guide/hw-vuln/tsx_async_abortmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhQ/var/lib/git/docbuild/linux/Documentation/admin-guide/hw-vuln/tsx_async_abort.rsthKubhsection)}(hhh](htitle)}(hTAA - TSX Asynchronous Aborth]hTAA - TSX Asynchronous Abort}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hTAA is a hardware vulnerability that allows unprivileged speculative access to data which is available in various CPU internal buffers by using asynchronous aborts within an Intel TSX transactional region.h]hTAA is a hardware vulnerability that allows unprivileged speculative access to data which is available in various CPU internal buffers by using asynchronous aborts within an Intel TSX transactional region.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hAffected processorsh]hAffected processors}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hXBThis vulnerability only affects Intel processors that support Intel Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8) is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations also mitigate against TAA.h]hXBThis vulnerability only affects Intel processors that support Intel Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8) is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations also mitigate against TAA.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hWhether a processor is affected or not can be read out from the TAA vulnerability file in sysfs. See :ref:`tsx_async_abort_sys_info`.h](heWhether a processor is affected or not can be read out from the TAA vulnerability file in sysfs. See }(hhhhhNhNubh)}(h:ref:`tsx_async_abort_sys_info`h]hinline)}(hjh]htsx_async_abort_sys_info}(hjhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc#admin-guide/hw-vuln/tsx_async_abort refdomainjreftyperef refexplicitrefwarn reftargettsx_async_abort_sys_infouh1hhhhKhhubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]affected-processorsah ]h"]affected processorsah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h Related CVEsh]h Related CVEs}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhKubh)}(h5The following CVE entry is related to this TAA issue:h]h5The following CVE entry is related to this TAA issue:}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj7hhubh block_quote)}(hX============== ===== =================================================== CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. ============== ===== =================================================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jfhjcubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jfhjcubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK3uh1jfhjcubhtbody)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hCVE-2019-11135h]hCVE-2019-11135}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTAAh]hTAA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTSX Asynchronous Abort (TAA) condition on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access.h]hTSX Asynchronous Abort (TAA) condition on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]colsKuh1jahj^ubah}(h]h ]h"]h$]h&]uh1j\hjXubah}(h]h ]h"]h$]h&]uh1jVhhhKhj7hhubeh}(h] related-cvesah ]h"] related cvesah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hProblemh]hProblem}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK$ubh)}(hWhen performing store, load or L1 refill operations, processors write data into temporary microarchitectural structures (buffers). The data in those buffers can be forwarded to load operations as an optimization.h]hWhen performing store, load or L1 refill operations, processors write data into temporary microarchitectural structures (buffers). The data in those buffers can be forwarded to load operations as an optimization.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh)}(hX,Intel TSX is an extension to the x86 instruction set architecture that adds hardware transactional memory support to improve performance of multi-threaded software. TSX lets the processor expose and exploit concurrency hidden in an application due to dynamically avoiding unnecessary synchronization.h]hX,Intel TSX is an extension to the x86 instruction set architecture that adds hardware transactional memory support to improve performance of multi-threaded software. TSX lets the processor expose and exploit concurrency hidden in an application due to dynamically avoiding unnecessary synchronization.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjhhubh)}(hXvTSX supports atomic memory transactions that are either committed (success) or aborted. During an abort, operations that happened within the transactional region are rolled back. An asynchronous abort takes place, among other options, when a different thread accesses a cache line that is also used within the transactional region when that access might lead to a data race.h]hXvTSX supports atomic memory transactions that are either committed (success) or aborted. During an abort, operations that happened within the transactional region are rolled back. An asynchronous abort takes place, among other options, when a different thread accesses a cache line that is also used within the transactional region when that access might lead to a data race.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjhhubh)}(hImmediately after an uncompleted asynchronous abort, certain speculatively executed loads may read data from those internal buffers and pass it to dependent operations. This can be then used to infer the value via a cache side channel attack.h]hImmediately after an uncompleted asynchronous abort, certain speculatively executed loads may read data from those internal buffers and pass it to dependent operations. This can be then used to infer the value via a cache side channel attack.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjhhubh)}(hiBecause the buffers are potentially shared between Hyper-Threads cross Hyper-Thread attacks are possible.h]hiBecause the buffers are potentially shared between Hyper-Threads cross Hyper-Thread attacks are possible.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjhhubh)}(hThe victim of a malicious actor does not need to make use of TSX. Only the attacker needs to begin a TSX transaction and raise an asynchronous abort which in turn potentially leaks data stored in the buffers.h]hThe victim of a malicious actor does not need to make use of TSX. Only the attacker needs to begin a TSX transaction and raise an asynchronous abort which in turn potentially leaks data stored in the buffers.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjhhubh)}(hMore detailed technical information is available in the TAA specific x86 architecture section: :ref:`Documentation/arch/x86/tsx_async_abort.rst `.h](h_More detailed technical information is available in the TAA specific x86 architecture section: }(hjchhhNhNubh)}(hC:ref:`Documentation/arch/x86/tsx_async_abort.rst `h]j)}(hjmh]h*Documentation/arch/x86/tsx_async_abort.rst}(hjohhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]refdocj refdomainjyreftyperef refexplicitrefwarnj#tsx_async_abortuh1hhhhKAhjcubh.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKAhjhhubeh}(h]problemah ]h"]problemah$]h&]uh1hhhhhhhhK$ubh)}(hhh](h)}(hAttack scenariosh]hAttack scenarios}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKFubh)}(hsAttacks against the TAA vulnerability can be implemented from unprivileged applications running on hosts or guests.h]hsAttacks against the TAA vulnerability can be implemented from unprivileged applications running on hosts or guests.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubh)}(hX"As for MDS, the attacker has no control over the memory addresses that can be leaked. Only the victim is responsible for bringing data to the CPU. As a result, the malicious actor has to sample as much data as possible and then postprocess it to try to infer any useful information from it.h]hX"As for MDS, the attacker has no control over the memory addresses that can be leaked. Only the victim is responsible for bringing data to the CPU. As a result, the malicious actor has to sample as much data as possible and then postprocess it to try to infer any useful information from it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjhhubh)}(h}A potential attacker only has read access to the data. Also, there is no direct privilege escalation by using this technique.h]h}A potential attacker only has read access to the data. Also, there is no direct privilege escalation by using this technique.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjhhubhtarget)}(h.. _tsx_async_abort_sys_info:h]h}(h]h ]h"]h$]h&]refidtsx-async-abort-sys-infouh1jhKThjhhhhubeh}(h]attack-scenariosah ]h"]attack scenariosah$]h&]uh1hhhhhhhhKFubh)}(hhh](h)}(hTAA system informationh]hTAA system information}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKWubh)}(hThe Linux kernel provides a sysfs interface to enumerate the current TAA status of mitigated systems. The relevant sysfs file is:h]hThe Linux kernel provides a sysfs interface to enumerate the current TAA status of mitigated systems. The relevant sysfs file is:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjhhubh)}(h7/sys/devices/system/cpu/vulnerabilities/tsx_async_aborth]h7/sys/devices/system/cpu/vulnerabilities/tsx_async_abort}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjhhubh)}(h%The possible values in this file are:h]h%The possible values in this file are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubj])}(hhh]jb)}(hhh](jg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK2uh1jfhj,ubjg)}(hhh]h}(h]h ]h"]h$]h&]j8K2uh1jfhj,ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h 'Vulnerable'h]h‘Vulnerable’}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjHubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hbThe CPU is affected by this vulnerability and the microcode and kernel mitigation are not applied.h]hbThe CPU is affected by this vulnerability and the microcode and kernel mitigation are not applied.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchj_ubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(h7'Vulnerable: Clear CPU buffers attempted, no microcode'h]h;‘Vulnerable: Clear CPU buffers attempted, no microcode’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh](h)}(hkThe processor is vulnerable but microcode is not updated. The mitigation is enabled on a best effort basis.h]hkThe processor is vulnerable but microcode is not updated. The mitigation is enabled on a best effort basis.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjubh)}(hXIf the processor is vulnerable but the availability of the microcode based mitigation mechanism is not advertised via CPUID, the kernel selects a best effort mitigation mode. This mode invokes the mitigation instructions without a guarantee that they clear the CPU buffers.h]hXIf the processor is vulnerable but the availability of the microcode based mitigation mechanism is not advertised via CPUID, the kernel selects a best effort mitigation mode. This mode invokes the mitigation instructions without a guarantee that they clear the CPU buffers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjubh)}(hXThis is done to address virtualization scenarios where the host has the microcode update applied, but the hypervisor is not yet updated to expose the CPUID to the guest. If the host has updated microcode the protection takes effect; otherwise a few CPU cycles are wasted pointlessly.h]hXThis is done to address virtualization scenarios where the host has the microcode update applied, but the hypervisor is not yet updated to expose the CPUID to the guest. If the host has updated microcode the protection takes effect; otherwise a few CPU cycles are wasted pointlessly.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubeh}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(h'Mitigation: Clear CPU buffers'h]h#‘Mitigation: Clear CPU buffers’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hJThe microcode has been updated to clear the buffers. TSX is still enabled.h]hJThe microcode has been updated to clear the buffers. TSX is still enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(h'Mitigation: TSX disabled'h]h‘Mitigation: TSX disabled’}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTSX is disabled.h]hTSX is disabled.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh](j)}(hhh]h)}(h'Not affected'h]h‘Not affected’}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhj@ubah}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh]h)}(h&The CPU is not affected by this issue.h]h&The CPU is not affected by this issue.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjWubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]colsKuh1jahj)ubah}(h]h ]h"]h$]h&]uh1j\hjhhhNhNubeh}(h](taa-system-informationjeh ]h"](taa system informationtsx_async_abort_sys_infoeh$]h&]uh1hhhhhhhhKWexpect_referenced_by_name}jjsexpect_referenced_by_id}jjsubh)}(hhh](h)}(hMitigation mechanismh]hMitigation mechanism}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKzubh)}(hThe kernel detects the affected CPUs and the presence of the microcode which is required. If a CPU is affected and the microcode is available, then the kernel enables the mitigation by default.h]hThe kernel detects the affected CPUs and the presence of the microcode which is required. If a CPU is affected and the microcode is available, then the kernel enables the mitigation by default.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjhhubh)}(hThe mitigation can be controlled at boot time via a kernel command line option. See :ref:`taa_mitigation_control_command_line`.h](hTThe mitigation can be controlled at boot time via a kernel command line option. See }(hjhhhNhNubh)}(h*:ref:`taa_mitigation_control_command_line`h]j)}(hjh]h#taa_mitigation_control_command_line}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnj##taa_mitigation_control_command_lineuh1hhhhKhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hVirtualization mitigationh]hVirtualization mitigation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hAffected systems where the host has TAA microcode and TAA is mitigated by having disabled TSX previously, are not vulnerable regardless of the status of the VMs.h]hAffected systems where the host has TAA microcode and TAA is mitigated by having disabled TSX previously, are not vulnerable regardless of the status of the VMs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hIn all other cases, if the host either does not have the TAA microcode or the kernel is not mitigated, the system might be vulnerable.h]hIn all other cases, if the host either does not have the TAA microcode or the kernel is not mitigated, the system might be vulnerable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h(.. _taa_mitigation_control_command_line:h]h}(h]h ]h"]h$]h&]j#taa-mitigation-control-command-lineuh1jhKhjhhhhubeh}(h]virtualization-mitigationah ]h"]virtualization mitigationah$]h&]uh1hhjhhhhhKubeh}(h]mitigation-mechanismah ]h"]mitigation mechanismah$]h&]uh1hhhhhhhhKzubh)}(hhh](h)}(h-Mitigation control on the kernel command lineh]h-Mitigation control on the kernel command line}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhhhKubh)}(hThe kernel command line allows to control the TAA mitigations at boot time with the option "tsx_async_abort=". The valid arguments for this option are:h]hThe kernel command line allows to control the TAA mitigations at boot time with the option “tsx_async_abort=”. The valid arguments for this option are:}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubjW)}(hX============ ============================================================= off This option disables the TAA mitigation on affected platforms. If the system has TSX enabled (see next parameter) and the CPU is affected, the system is vulnerable. full TAA mitigation is enabled. If TSX is enabled, on an affected system it will clear CPU buffers on ring transitions. On systems which are MDS-affected and deploy MDS mitigation, TAA is also mitigated. Specifying this option on those systems will have no effect. full,nosmt The same as tsx_async_abort=full, with SMT disabled on vulnerable CPUs that have TSX enabled. This is the complete mitigation. When TSX is disabled, SMT is not disabled because CPU is not vulnerable to cross-thread TAA attacks. ============ ============================================================= h]j])}(hhh]jb)}(hhh](jg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jfhjSubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jfhjSubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hoffh]hoff}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjpubah}(h]h ]h"]h$]h&]uh1jhjmubj)}(hhh]h)}(hThis option disables the TAA mitigation on affected platforms. If the system has TSX enabled (see next parameter) and the CPU is affected, the system is vulnerable.h]hThis option disables the TAA mitigation on affected platforms. If the system has TSX enabled (see next parameter) and the CPU is affected, the system is vulnerable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh](j)}(hhh]h)}(hfullh]hfull}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hXTAA mitigation is enabled. If TSX is enabled, on an affected system it will clear CPU buffers on ring transitions. On systems which are MDS-affected and deploy MDS mitigation, TAA is also mitigated. Specifying this option on those systems will have no effect.h]hXTAA mitigation is enabled. If TSX is enabled, on an affected system it will clear CPU buffers on ring transitions. On systems which are MDS-affected and deploy MDS mitigation, TAA is also mitigated. Specifying this option on those systems will have no effect.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh](j)}(hhh]h)}(h full,nosmth]h full,nosmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hThe same as tsx_async_abort=full, with SMT disabled on vulnerable CPUs that have TSX enabled. This is the complete mitigation. When TSX is disabled, SMT is not disabled because CPU is not vulnerable to cross-thread TAA attacks.h]hThe same as tsx_async_abort=full, with SMT disabled on vulnerable CPUs that have TSX enabled. This is the complete mitigation. When TSX is disabled, SMT is not disabled because CPU is not vulnerable to cross-thread TAA attacks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]colsKuh1jahjPubah}(h]h ]h"]h$]h&]uh1j\hjLubah}(h]h ]h"]h$]h&]uh1jVhhhKhj-hhubh)}(hXNot specifying this option is equivalent to "tsx_async_abort=full". For processors that are affected by both TAA and MDS, specifying just "tsx_async_abort=off" without an accompanying "mds=off" will have no effect as the same mitigation is used for both vulnerabilities.h]hXNot specifying this option is equivalent to “tsx_async_abort=full”. For processors that are affected by both TAA and MDS, specifying just “tsx_async_abort=off” without an accompanying “mds=off” will have no effect as the same mitigation is used for both vulnerabilities.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubh)}(hThe kernel command line also allows to control the TSX feature using the parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used to control the TSX feature and the enumeration of the TSX feature bits (RTM and HLE) in CPUID.h]hThe kernel command line also allows to control the TSX feature using the parameter “tsx=” on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used to control the TSX feature and the enumeration of the TSX feature bits (RTM and HLE) in CPUID.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubh)}(hThe valid options are:h]hThe valid options are:}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubjW)}(hX============ ============================================================= off Disables TSX on the system. Note that this option takes effect only on newer CPUs which are not vulnerable to MDS, i.e., have MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get the new IA32_TSX_CTRL MSR through a microcode update. This new MSR allows for the reliable deactivation of the TSX functionality. on Enables TSX. Although there are mitigations for all known security vulnerabilities, TSX has been known to be an accelerator for several previous speculation-related CVEs, and so there may be unknown security risks associated with leaving it enabled. auto Disables TSX if X86_BUG_TAA is present, otherwise enables TSX on the system. ============ ============================================================= h]j])}(hhh]jb)}(hhh](jg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jfhj\ubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthKEuh1jfhj\ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hoffh]hoff}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh](h)}(hDisables TSX on the system.h]hDisables TSX on the system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hXNote that this option takes effect only on newer CPUs which are not vulnerable to MDS, i.e., have MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get the new IA32_TSX_CTRL MSR through a microcode update. This new MSR allows for the reliable deactivation of the TSX functionality.h]hXNote that this option takes effect only on newer CPUs which are not vulnerable to MDS, i.e., have MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get the new IA32_TSX_CTRL MSR through a microcode update. This new MSR allows for the reliable deactivation of the TSX functionality.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh](j)}(hhh]h)}(honh]hon}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](h)}(h Enables TSX.h]h Enables TSX.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hAlthough there are mitigations for all known security vulnerabilities, TSX has been known to be an accelerator for several previous speculation-related CVEs, and so there may be unknown security risks associated with leaving it enabled.h]hAlthough there are mitigations for all known security vulnerabilities, TSX has been known to be an accelerator for several previous speculation-related CVEs, and so there may be unknown security risks associated with leaving it enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh](j)}(hhh]h)}(hautoh]hauto}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hLDisables TSX if X86_BUG_TAA is present, otherwise enables TSX on the system.h]hLDisables TSX if X86_BUG_TAA is present, otherwise enables TSX on the system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]colsKuh1jahjYubah}(h]h ]h"]h$]h&]uh1j\hjUubah}(h]h ]h"]h$]h&]uh1jVhhhKhj-hhubh)}(h6Not specifying this option is equivalent to "tsx=off".h]h:Not specifying this option is equivalent to “tsx=off”.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubh)}(hThe following combinations of the "tsx_async_abort" and "tsx" are possible. For affected platforms tsx=auto is equivalent to tsx=off and the result will be:h]hThe following combinations of the “tsx_async_abort” and “tsx” are possible. For affected platforms tsx=auto is equivalent to tsx=off and the result will be:}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubjW)}(hX|========= ========================== ========================================= tsx=on tsx_async_abort=full The system will use VERW to clear CPU buffers. Cross-thread attacks are still possible on SMT machines. tsx=on tsx_async_abort=full,nosmt As above, cross-thread attacks on SMT mitigated. tsx=on tsx_async_abort=off The system is vulnerable. tsx=off tsx_async_abort=full TSX might be disabled if microcode provides a TSX control MSR. If so, system is not vulnerable. tsx=off tsx_async_abort=full,nosmt Ditto tsx=off tsx_async_abort=off ditto ========= ========================== ========================================= h]j])}(hhh]jb)}(hhh](jg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jfhjsubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jfhjsubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK)uh1jfhjsubj)}(hhh](j)}(hhh](j)}(hhh]h)}(htsx=onh]htsx=on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(htsx_async_abort=fullh]htsx_async_abort=full}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hgThe system will use VERW to clear CPU buffers. Cross-thread attacks are still possible on SMT machines.h]hgThe system will use VERW to clear CPU buffers. Cross-thread attacks are still possible on SMT machines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htsx=onh]htsx=on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(htsx_async_abort=full,nosmth]htsx_async_abort=full,nosmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h0As above, cross-thread attacks on SMT mitigated.h]h0As above, cross-thread attacks on SMT mitigated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htsx=onh]htsx=on}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]h)}(htsx_async_abort=offh]htsx_async_abort=off}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]h)}(hThe system is vulnerable.h]hThe system is vulnerable.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htsx=offh]htsx=off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(htsx_async_abort=fullh]htsx_async_abort=full}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h_TSX might be disabled if microcode provides a TSX control MSR. If so, system is not vulnerable.h]h_TSX might be disabled if microcode provides a TSX control MSR. If so, system is not vulnerable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htsx=offh]htsx=off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(htsx_async_abort=full,nosmth]htsx_async_abort=full,nosmt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hDittoh]hDitto}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(htsx=offh]htsx=off}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(htsx_async_abort=offh]htsx_async_abort=off}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj7 ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hdittoh]hditto}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjN ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]colsKuh1jahjpubah}(h]h ]h"]h$]h&]uh1j\hjlubah}(h]h ]h"]h$]h&]uh1jVhhhKhj-hhubh)}(hFor unaffected platforms "tsx=on" and "tsx_async_abort=full" does not clear CPU buffers. For platforms without TSX control (MSR_IA32_ARCH_CAPABILITIES.MDS_NO=0) "tsx" command line argument has no effect.h]hFor unaffected platforms “tsx=on” and “tsx_async_abort=full” does not clear CPU buffers. For platforms without TSX control (MSR_IA32_ARCH_CAPABILITIES.MDS_NO=0) “tsx” command line argument has no effect.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubh)}(hFor the affected platforms below table indicates the mitigation status for the combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO and TSX_CTRL_MSR.h]hFor the affected platforms below table indicates the mitigation status for the combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO and TSX_CTRL_MSR.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubjW)}(hX======= ========= ============= ======================================== MDS_NO MD_CLEAR TSX_CTRL_MSR Status ======= ========= ============= ======================================== 0 0 0 Vulnerable (needs microcode) 0 1 0 MDS and TAA mitigated via VERW 1 1 0 MDS fixed, TAA vulnerable if TSX enabled because MD_CLEAR has no meaning and VERW is not guaranteed to clear buffers 1 X 1 MDS fixed, TAA can be mitigated by VERW or TSX_CTRL_MSR ======= ========= ============= ======================================== h]j])}(hhh]jb)}(hhh](jg)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jfhj ubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jfhj ubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jfhj ubjg)}(hhh]h}(h]h ]h"]h$]h&]colwidthK(uh1jfhj ubhthead)}(hhh]j)}(hhh](j)}(hhh]h)}(hMDS_NOh]hMDS_NO}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hMD_CLEARh]hMD_CLEAR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h TSX_CTRL_MSRh]h TSX_CTRL_MSR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hStatush]hStatus}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h0h]h0}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjH ubah}(h]h ]h"]h$]h&]uh1jhjE ubj)}(hhh]h)}(hjM h]h0}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj_ ubah}(h]h ]h"]h$]h&]uh1jhjE ubj)}(hhh]h)}(hjM h]h0}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhju ubah}(h]h ]h"]h$]h&]uh1jhjE ubj)}(hhh]h)}(hVulnerable (needs microcode)h]hVulnerable (needs microcode)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjE ubeh}(h]h ]h"]h$]h&]uh1jhjB ubj)}(hhh](j)}(hhh]h)}(hjM h]h0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h1h]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hjM h]h0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hMDS and TAA mitigated via VERWh]hMDS and TAA mitigated via VERW}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjB ubj)}(hhh](j)}(hhh]h)}(hj h]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hj h]h1}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hjM h]h0}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj: ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(htMDS fixed, TAA vulnerable if TSX enabled because MD_CLEAR has no meaning and VERW is not guaranteed to clear buffersh]htMDS fixed, TAA vulnerable if TSX enabled because MD_CLEAR has no meaning and VERW is not guaranteed to clear buffers}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjP ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjB ubj)}(hhh](j)}(hhh]h)}(hj h]h1}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjp ubah}(h]h ]h"]h$]h&]uh1jhjm ubj)}(hhh]h)}(hXh]hX}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjm ubj)}(hhh]h)}(hj h]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjm ubj)}(hhh]h)}(h7MDS fixed, TAA can be mitigated by VERW or TSX_CTRL_MSRh]h7MDS fixed, TAA can be mitigated by VERW or TSX_CTRL_MSR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjm ubeh}(h]h ]h"]h$]h&]uh1jhjB ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jahj ubah}(h]h ]h"]h$]h&]uh1j\hj ubah}(h]h ]h"]h$]h&]uh1jVhhhKhj-hhubeh}(h](-mitigation-control-on-the-kernel-command-linejeh ]h"](-mitigation control on the kernel command line#taa_mitigation_control_command_lineeh$]h&]uh1hhhhhhhhKj}j jsj}jjsubh)}(hhh](h)}(hMitigation selection guideh]hMitigation selection guide}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hhh](h)}(h1. Trusted userspace and guestsh]h1. Trusted userspace and guests}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hIf all user space applications are from a trusted source and do not execute untrusted code which is supplied externally, then the mitigation can be disabled. The same applies to virtualized environments with trusted guests.h]hIf all user space applications are from a trusted source and do not execute untrusted code which is supplied externally, then the mitigation can be disabled. The same applies to virtualized environments with trusted guests.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]trusted-userspace-and-guestsah ]h"]1. trusted userspace and guestsah$]h&]uh1hhj hhhhhKubh)}(hhh](h)}(h!2. Untrusted userspace and guestsh]h!2. Untrusted userspace and guests}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj, hhhhhKubh)}(hIf there are untrusted applications or guests on the system, enabling TSX might allow a malicious actor to leak data from the host or from other processes running on the same physical core.h]hIf there are untrusted applications or guests on the system, enabling TSX might allow a malicious actor to leak data from the host or from other processes running on the same physical core.}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj, hhubh)}(hIf the microcode is available and the TSX is disabled on the host, attacks are prevented in a virtualized environment as well, even if the VMs do not explicitly enable the mitigation.h]hIf the microcode is available and the TSX is disabled on the host, attacks are prevented in a virtualized environment as well, even if the VMs do not explicitly enable the mitigation.}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj, hhubj)}(h.. _taa_default_mitigations:h]h}(h]h ]h"]h$]h&]jtaa-default-mitigationsuh1jhMhj, hhhhubeh}(h]untrusted-userspace-and-guestsah ]h"]!2. untrusted userspace and guestsah$]h&]uh1hhj hhhhhKubeh}(h]mitigation-selection-guideah ]h"]mitigation selection guideah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDefault mitigationsh]hDefault mitigations}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt hhhhhM ubh)}(h9The kernel's default action for vulnerable processors is:h]h;The kernel’s default action for vulnerable processors is:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjt hhubjW)}(h?- Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).h]h bullet_list)}(hhh]h list_item)}(h=Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).h]h)}(hj h]h=Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]bullet-uh1j hhhMhj ubah}(h]h ]h"]h$]h&]uh1jVhhhMhjt hhubeh}(h](default-mitigationsjc eh ]h"](default mitigationstaa_default_mitigationseh$]h&]uh1hhhhhhhhM j}j jY sj}jc jY subeh}(h]taa-tsx-asynchronous-abortah ]h"]taa - tsx asynchronous abortah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}(j]jaj]jajc ]jY aunameids}(j j j4j1jjjjjjjjjjj*j'j"jj jj j jq jn j) j& ji jf j jc j j u nametypes}(j j4jjjjjj*j"j j jq j) ji j j uh}(j hj1hjj7jjjjjjjjj'jjjjj-j j-jn j j& j jf j, jc jt j jt u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages](hsystem_message)}(hhh]h)}(hhh]h>Hyperlink target "tsx-async-abort-sys-info" is not referenced.}hjd sbah}(h]h ]h"]h$]h&]uh1hhja ubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKTuh1j_ ubj` )}(hhh]h)}(hhh]hIHyperlink target "taa-mitigation-control-command-line" is not referenced.}hj sbah}(h]h ]h"]h$]h&]uh1hhj| ubah}(h]h ]h"]h$]h&]levelKtypejy sourcehlineKuh1j_ ubj` )}(hhh]h)}(hhh]h=Hyperlink target "taa-default-mitigations" is not referenced.}hj sbah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]levelKtypejy sourcehlineMuh1j_ ube transformerN include_log] decorationNhhub.