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YEN SIGN h]h¥}hjLsbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h2Reliability, Availability and Serviceability (RAS)h]h2Reliability, Availability and Serviceability (RAS)}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj]hhhhhKubh paragraph)}(hPThis documents different aspects of the RAS functionality present in the kernel.h]hPThis documents different aspects of the RAS functionality present in the kernel.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj]hhubj\)}(hhh](ja)}(h RAS conceptsh]h RAS concepts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK ubjq)}(hrReliability, Availability and Serviceability (RAS) is a concept used on servers meant to measure their robustness.h]hrReliability, Availability and Serviceability (RAS) is a concept used on servers meant to measure their robustness.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hReliability is the probability that a system will produce correct outputs. * Generally measured as Mean Time Between Failures (MTBF) * Enhanced by features that help to avoid, detect and repair hardware faults h](hterm)}(h Reliabilityh]h Reliability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubh definition)}(hhh](jq)}(h>is the probability that a system will produce correct outputs.h]h>is the probability that a system will produce correct outputs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubh bullet_list)}(hhh](h list_item)}(h7Generally measured as Mean Time Between Failures (MTBF)h]jq)}(hjh]h7Generally measured as Mean Time Between Failures (MTBF)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hKEnhanced by features that help to avoid, detect and repair hardware faults h]jq)}(hJEnhanced by features that help to avoid, detect and repair hardware faultsh]hJEnhanced by features that help to avoid, detect and repair hardware faults}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hAvailability is the probability that a system is operational at a given time * Generally measured as a percentage of downtime per a period of time * Often uses mechanisms to detect and correct hardware faults in runtime; h](j)}(h Availabilityh]h Availability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh](jq)}(h?is the probability that a system is operational at a given timeh]h?is the probability that a system is operational at a given time}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj)ubj)}(hhh](j)}(hCGenerally measured as a percentage of downtime per a period of timeh]jq)}(hj?h]hCGenerally measured as a percentage of downtime per a period of time}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj=ubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hHOften uses mechanisms to detect and correct hardware faults in runtime; h]jq)}(hGOften uses mechanisms to detect and correct hardware faults in runtime;h]hGOften uses mechanisms to detect and correct hardware faults in runtime;}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjTubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]j j uh1jhhhKhj)ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hServiceability (or maintainability) is the simplicity and speed with which a system can be repaired or maintained * Generally measured on Mean Time Between Repair (MTBR) h](j)}(h#Serviceability (or maintainability)h]h#Serviceability (or maintainability)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK"hj~ubj)}(hhh](jq)}(hMis the simplicity and speed with which a system can be repaired or maintainedh]hMis the simplicity and speed with which a system can be repaired or maintained}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubj)}(hhh]j)}(h6Generally measured on Mean Time Between Repair (MTBR) h]jq)}(h5Generally measured on Mean Time Between Repair (MTBR)h]h5Generally measured on Mean Time Between Repair (MTBR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK"hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]j j uh1jhhhK"hjubeh}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhhhK"hjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj\)}(hhh](ja)}(h Improving RASh]h Improving RAS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK%ubjq)}(hXSIn order to reduce systems downtime, a system should be capable of detecting hardware errors, and, when possible correcting them in runtime. It should also provide mechanisms to detect hardware degradation, in order to warn the system administrator to take the action of replacing a component before it causes data loss or system downtime.h]hXSIn order to reduce systems downtime, a system should be capable of detecting hardware errors, and, when possible correcting them in runtime. It should also provide mechanisms to detect hardware degradation, in order to warn the system administrator to take the action of replacing a component before it causes data loss or system downtime.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK'hjhhubjq)}(h;Among the monitoring measures, the most usual ones include:h]h;Among the monitoring measures, the most usual ones include:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK-hjhhubj)}(hhh](j)}(hFCPU – detect errors at instruction execution and at L1/L2/L3 caches;h]jq)}(hjh]hFCPU – detect errors at instruction execution and at L1/L2/L3 caches;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hIMemory – add error correction logic (ECC) to detect and correct errors;h]jq)}(hjh]hIMemory – add error correction logic (ECC) to detect and correct errors;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK0hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h/I/O – add CRC checksums for transferred data;h]jq)}(hj4h]h/I/O – add CRC checksums for transferred data;}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK1hj2ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hoStorage – RAID, journal file systems, checksums, Self-Monitoring, Analysis and Reporting Technology (SMART). h]jq)}(hnStorage – RAID, journal file systems, checksums, Self-Monitoring, Analysis and Reporting Technology (SMART).h]hnStorage – RAID, journal file systems, checksums, Self-Monitoring, Analysis and Reporting Technology (SMART).}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK2hjIubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j j uh1jhhhK/hjhhubjq)}(hBy monitoring the number of occurrences of error detections, it is possible to identify if the probability of hardware errors is increasing, and, on such case, do a preventive maintenance to replace a degraded component while those errors are correctable.h]hBy monitoring the number of occurrences of error detections, it is possible to identify if the probability of hardware errors is increasing, and, on such case, do a preventive maintenance to replace a degraded component while those errors are correctable.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK5hjhhubeh}(h] improving-rasah ]h"] improving rasah$]h&]uh1j[hjhhhhhK%ubj\)}(hhh](ja)}(hTypes of errorsh]hTypes of errors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj}hhhhhK;ubjq)}(hX7Most mechanisms used on modern systems use technologies like Hamming Codes that allow error correction when the number of errors on a bit packet is below a threshold. If the number of errors is above, those mechanisms can indicate with a high degree of confidence that an error happened, but they can't correct.h]hX9Most mechanisms used on modern systems use technologies like Hamming Codes that allow error correction when the number of errors on a bit packet is below a threshold. If the number of errors is above, those mechanisms can indicate with a high degree of confidence that an error happened, but they can’t correct.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK=hj}hhubjq)}(hAlso, sometimes an error occur on a component that it is not used. For example, a part of the memory that it is not currently allocated.h]hAlso, sometimes an error occur on a component that it is not used. For example, a part of the memory that it is not currently allocated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKChj}hhubjq)}(h'That defines some categories of errors:h]h'That defines some categories of errors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKFhj}hhubj)}(hhh](j)}(h**Correctable Error (CE)** - the error detection mechanism detected and corrected the error. Such errors are usually not fatal, although some Kernel mechanisms allow the system administrator to consider them as fatal. h]jq)}(h**Correctable Error (CE)** - the error detection mechanism detected and corrected the error. Such errors are usually not fatal, although some Kernel mechanisms allow the system administrator to consider them as fatal.h](hstrong)}(h**Correctable Error (CE)**h]hCorrectable Error (CE)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - the error detection mechanism detected and corrected the error. Such errors are usually not fatal, although some Kernel mechanisms allow the system administrator to consider them as fatal.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKHhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h**Uncorrected Error (UE)** - the amount of errors happened above the error correction threshold, and the system was unable to auto-correct. h]jq)}(h**Uncorrected Error (UE)** - the amount of errors happened above the error correction threshold, and the system was unable to auto-correct.h](j)}(h**Uncorrected Error (UE)**h]hUncorrected Error (UE)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhq - the amount of errors happened above the error correction threshold, and the system was unable to auto-correct.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKLhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h**Fatal Error** - when an UE error happens on a critical component of the system (for example, a piece of the Kernel got corrupted by an UE), the only reliable way to avoid data corruption is to hang or reboot the machine. h]jq)}(h**Fatal Error** - when an UE error happens on a critical component of the system (for example, a piece of the Kernel got corrupted by an UE), the only reliable way to avoid data corruption is to hang or reboot the machine.h](j)}(h**Fatal Error**h]h Fatal Error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh - when an UE error happens on a critical component of the system (for example, a piece of the Kernel got corrupted by an UE), the only reliable way to avoid data corruption is to hang or reboot the machine.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKOhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX_**Non-fatal Error** - when an UE error happens on an unused component, like a CPU in power down state or an unused memory bank, the system may still run, eventually replacing the affected hardware by a hot spare, if available. Also, when an error happens on a userspace process, it is also possible to kill such process and let userspace restart it. h](jq)}(h**Non-fatal Error** - when an UE error happens on an unused component, like a CPU in power down state or an unused memory bank, the system may still run, eventually replacing the affected hardware by a hot spare, if available.h](j)}(h**Non-fatal Error**h]hNon-fatal Error}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubh - when an UE error happens on an unused component, like a CPU in power down state or an unused memory bank, the system may still run, eventually replacing the affected hardware by a hot spare, if available.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKShj/ubjq)}(hzAlso, when an error happens on a userspace process, it is also possible to kill such process and let userspace restart it.h]hzAlso, when an error happens on a userspace process, it is also possible to kill such process and let userspace restart it.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKXhj/ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j j uh1jhhhKHhj}hhubjq)}(hThe mechanism for handling non-fatal errors is usually complex and may require the help of some userspace application, in order to apply the policy desired by the system administrator.h]hThe mechanism for handling non-fatal errors is usually complex and may require the help of some userspace application, in order to apply the policy desired by the system administrator.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK[hj}hhubeh}(h]types-of-errorsah ]h"]types of errorsah$]h&]uh1j[hjhhhhhK;ubj\)}(hhh](ja)}(h$Identifying a bad hardware componenth]h$Identifying a bad hardware component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK`ubjq)}(hJust detecting a hardware flaw is usually not enough, as the system needs to pinpoint to the minimal replaceable unit (MRU) that should be exchanged to make the hardware reliable again.h]hJust detecting a hardware flaw is usually not enough, as the system needs to pinpoint to the minimal replaceable unit (MRU) that should be exchanged to make the hardware reliable again.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKbhjhhubjq)}(hSo, it requires not only error logging facilities, but also mechanisms that will translate the error message to the silkscreen or component label for the MRU.h]hSo, it requires not only error logging facilities, but also mechanisms that will translate the error message to the silkscreen or component label for the MRU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKfhjhhubjq)}(hX-Typically, it is very complex for memory, as modern CPUs interlace memory from different memory modules, in order to provide a better performance. The DMI BIOS usually have a list of memory module labels, with can be obtained using the ``dmidecode`` tool. For example, on a desktop machine, it shows::h](hTypically, it is very complex for memory, as modern CPUs interlace memory from different memory modules, in order to provide a better performance. The DMI BIOS usually have a list of memory module labels, with can be obtained using the }(hjhhhNhNubhliteral)}(h ``dmidecode``h]h dmidecode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh3 tool. For example, on a desktop machine, it shows:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKjhjhhubh literal_block)}(hXMMemory Device Total Width: 64 bits Data Width: 64 bits Size: 16384 MB Form Factor: SODIMM Set: None Locator: ChannelA-DIMM0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 2133 MHz Rank: 2 Configured Clock Speed: 2133 MHzh]hXMMemory Device Total Width: 64 bits Data Width: 64 bits Size: 16384 MB Form Factor: SODIMM Set: None Locator: ChannelA-DIMM0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 2133 MHz Rank: 2 Configured Clock Speed: 2133 MHz}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKohjhhubjq)}(hX8On the above example, a DDR4 SO-DIMM memory module is located at the system's memory labeled as "BANK 0", as given by the *bank locator* field. Please notice that, on such system, the *total width* is equal to the *data width*. It means that such memory module doesn't have error detection/correction mechanisms.h](hOn the above example, a DDR4 SO-DIMM memory module is located at the system’s memory labeled as “BANK 0”, as given by the }(hjhhhNhNubhemphasis)}(h*bank locator*h]h bank locator}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh0 field. Please notice that, on such system, the }(hjhhhNhNubj)}(h *total width*h]h total width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is equal to the }(hjhhhNhNubj)}(h *data width*h]h data width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX. It means that such memory module doesn’t have error detection/correction mechanisms.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhK}hjhhubjq)}(hUnfortunately, not all systems use the same field to specify the memory bank. On this example, from an older server, ``dmidecode`` shows::h](huUnfortunately, not all systems use the same field to specify the memory bank. On this example, from an older server, }(hj$ hhhNhNubj)}(h ``dmidecode``h]h dmidecode}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ ubh shows:}(hj$ hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhjhhubj)}(hXMemory Device Array Handle: 0x1000 Error Information Handle: Not Provided Total Width: 72 bits Data Width: 64 bits Size: 8192 MB Form Factor: DIMM Set: 1 Locator: DIMM_A1 Bank Locator: Not Specified Type: DDR3 Type Detail: Synchronous Registered (Buffered) Speed: 1600 MHz Rank: 2 Configured Clock Speed: 1600 MHzh]hXMemory Device Array Handle: 0x1000 Error Information Handle: Not Provided Total Width: 72 bits Data Width: 64 bits Size: 8192 MB Form Factor: DIMM Set: 1 Locator: DIMM_A1 Bank Locator: Not Specified Type: DDR3 Type Detail: Synchronous Registered (Buffered) Speed: 1600 MHz Rank: 2 Configured Clock Speed: 1600 MHz}hjD sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubjq)}(hXvThere, the DDR3 RDIMM memory module is located at the system's memory labeled as "DIMM_A1", as given by the *locator* field. Please notice that this memory module has 64 bits of *data width* and 72 bits of *total width*. So, it has 8 extra bits to be used by error detection and correction mechanisms. Such kind of memory is called Error-correcting code memory (ECC memory).h](hrThere, the DDR3 RDIMM memory module is located at the system’s memory labeled as “DIMM_A1”, as given by the }(hjR hhhNhNubj)}(h *locator*h]hlocator}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR ubh= field. Please notice that this memory module has 64 bits of }(hjR hhhNhNubj)}(h *data width*h]h data width}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR ubh and 72 bits of }(hjR hhhNhNubj)}(h *total width*h]h total width}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR ubh. So, it has 8 extra bits to be used by error detection and correction mechanisms. Such kind of memory is called Error-correcting code memory (ECC memory).}(hjR hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhjhhubjq)}(hTo make things even worse, it is not uncommon that systems with different labels on their system's board to use exactly the same BIOS, meaning that the labels provided by the BIOS won't match the real ones.h]hTo make things even worse, it is not uncommon that systems with different labels on their system’s board to use exactly the same BIOS, meaning that the labels provided by the BIOS won’t match the real ones.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubeh}(h]$identifying-a-bad-hardware-componentah ]h"]$identifying a bad hardware componentah$]h&]uh1j[hjhhhhhK`ubj\)}(hhh](ja)}(h ECC memoryh]h ECC memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubjq)}(hXGAs mentioned in the previous section, ECC memory has extra bits to be used for error correction. In the above example, a memory module has 64 bits of *data width*, and 72 bits of *total width*. The extra 8 bits which are used for the error detection and correction mechanisms are referred to as the *syndrome*\ [#f1]_\ [#f2]_.h](hAs mentioned in the previous section, ECC memory has extra bits to be used for error correction. In the above example, a memory module has 64 bits of }(hj hhhNhNubj)}(h *data width*h]h data width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, and 72 bits of }(hj hhhNhNubj)}(h *total width*h]h total width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhl. The extra 8 bits which are used for the error detection and correction mechanisms are referred to as the }(hj hhhNhNubj)}(h *syndrome*h]hsyndrome}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh }(hj hhhNhNubhfootnote_reference)}(h[#f1]_h]h1}(hj hhhNhNubah}(h]id1ah ]h"]h$]h&]autoKrefidf1docnameadmin-guide/RAS/mainuh1j hj resolvedKubh }hj sbj )}(h[#f2]_h]h2}(hj hhhNhNubah}(h]id2ah ]h"]h$]h&]j Kj f2j j uh1j hj j Kubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubjq)}(hX2So, when the cpu requests the memory controller to write a word with *data width*, the memory controller calculates the *syndrome* in real time, using Hamming code, or some other error correction code, like SECDED+, producing a code with *total width* size. Such code is then written on the memory modules.h](hESo, when the cpu requests the memory controller to write a word with }(hj0 hhhNhNubj)}(h *data width*h]h data width}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0 ubh', the memory controller calculates the }(hj0 hhhNhNubj)}(h *syndrome*h]hsyndrome}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0 ubhl in real time, using Hamming code, or some other error correction code, like SECDED+, producing a code with }(hj0 hhhNhNubj)}(h *total width*h]h total width}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0 ubh7 size. Such code is then written on the memory modules.}(hj0 hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubjq)}(hAt read, the *total width* bits code is converted back, using the same ECC code used on write, producing a word with *data width* and a *syndrome*. The word with *data width* is sent to the CPU, even when errors happen.h](h At read, the }(hjt hhhNhNubj)}(h *total width*h]h total width}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt ubh[ bits code is converted back, using the same ECC code used on write, producing a word with }(hjt hhhNhNubj)}(h *data width*h]h data width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt ubh and a }(hjt hhhNhNubj)}(h *syndrome*h]hsyndrome}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt ubh. The word with }(hjt hhhNhNubj)}(h *data width*h]h data width}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt ubh- is sent to the CPU, even when errors happen.}(hjt hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubjq)}(hThe memory controller also looks at the *syndrome* in order to check if there was an error, and if the ECC code was able to fix such error. If the error was corrected, a Corrected Error (CE) happened. If not, an Uncorrected Error (UE) happened.h](h(The memory controller also looks at the }(hj hhhNhNubj)}(h *syndrome*h]hsyndrome}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh in order to check if there was an error, and if the ECC code was able to fix such error. If the error was corrected, a Corrected Error (CE) happened. If not, an Uncorrected Error (UE) happened.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubjq)}(hX8The information about the CE/UE errors is stored on some special registers at the memory controller and can be accessed by reading such registers, either by BIOS, by some special CPUs or by Linux EDAC driver. On x86 64 bit CPUs, such errors can also be retrieved via the Machine Check Architecture (MCA)\ [#f3]_.h](hX1The information about the CE/UE errors is stored on some special registers at the memory controller and can be accessed by reading such registers, either by BIOS, by some special CPUs or by Linux EDAC driver. On x86 64 bit CPUs, such errors can also be retrieved via the Machine Check Architecture (MCA) }(hj hhhNhNubj )}(h[#f3]_h]h3}(hj hhhNhNubah}(h]id3ah ]h"]h$]h&]j Kj f3j j uh1j hj j Kubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubhfootnote)}(hXPlease notice that several memory controllers allow operation on a mode called "Lock-Step", where it groups two memory modules together, doing 128-bit reads/writes. That gives 16 bits for error correction, with significantly improves the error correction mechanism, at the expense that, when an error happens, there's no way to know what memory module is to blame. So, it has to blame both memory modules. h](hlabel)}(hhh]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj hhhNhNubjq)}(hXPlease notice that several memory controllers allow operation on a mode called "Lock-Step", where it groups two memory modules together, doing 128-bit reads/writes. That gives 16 bits for error correction, with significantly improves the error correction mechanism, at the expense that, when an error happens, there's no way to know what memory module is to blame. So, it has to blame both memory modules.h]hXPlease notice that several memory controllers allow operation on a mode called “Lock-Step”, where it groups two memory modules together, doing 128-bit reads/writes. That gives 16 bits for error correction, with significantly improves the error correction mechanism, at the expense that, when an error happens, there’s no way to know what memory module is to blame. So, it has to blame both memory modules.}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubeh}(h]j ah ]h"]f1ah$]h&]j aj Kj j uh1j hhhKhj hhubj )}(hXSome memory controllers also allow using memory in mirror mode. On such mode, the same data is written to two memory modules. At read, the system checks both memory modules, in order to check if both provide identical data. On such configuration, when an error happens, there's no way to know what memory module is to blame. So, it has to blame both memory modules (or 4 memory modules, if the system is also on Lock-step mode). h](j )}(hhh]h2}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj6 hhhNhNubjq)}(hXSome memory controllers also allow using memory in mirror mode. On such mode, the same data is written to two memory modules. At read, the system checks both memory modules, in order to check if both provide identical data. On such configuration, when an error happens, there's no way to know what memory module is to blame. So, it has to blame both memory modules (or 4 memory modules, if the system is also on Lock-step mode).h]hXSome memory controllers also allow using memory in mirror mode. On such mode, the same data is written to two memory modules. At read, the system checks both memory modules, in order to check if both provide identical data. On such configuration, when an error happens, there’s no way to know what memory module is to blame. So, it has to blame both memory modules (or 4 memory modules, if the system is also on Lock-step mode).}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj6 ubeh}(h]j% ah ]h"]f2ah$]h&]j aj Kj j uh1j hhhKhj hhubj )}(hFor more details about the Machine Check Architecture (MCA), please read Documentation/arch/x86/x86_64/machinecheck.rst at the Kernel tree. h](j )}(hhh]h3}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj\ hhhNhNubjq)}(hFor more details about the Machine Check Architecture (MCA), please read Documentation/arch/x86/x86_64/machinecheck.rst at the Kernel tree.h]hFor more details about the Machine Check Architecture (MCA), please read Documentation/arch/x86/x86_64/machinecheck.rst at the Kernel tree.}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj\ ubeh}(h]j ah ]h"]f3ah$]h&]j aj Kj j uh1j hhhKhj hhubeh}(h] ecc-memoryah ]h"] ecc memoryah$]h&]uh1j[hjhhhhhKubeh}(h] ras-conceptsah ]h"] ras conceptsah$]h&]uh1j[hj]hhhhhK ubj\)}(hhh](ja)}(h%EDAC - Error Detection And Correctionh]h%EDAC - Error Detection And Correction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubhnote)}(hX?"bluesmoke" was the name for this device driver subsystem when it was "out-of-tree" and maintained at http://bluesmoke.sourceforge.net. That site is mostly archaic now and can be used only for historical purposes. When the subsystem was pushed upstream for the first time, on Kernel 2.6.16, it was renamed to ``EDAC``.h](jq)}(h"bluesmoke" was the name for this device driver subsystem when it was "out-of-tree" and maintained at http://bluesmoke.sourceforge.net. That site is mostly archaic now and can be used only for historical purposes.h](hn“bluesmoke” was the name for this device driver subsystem when it was “out-of-tree” and maintained at }(hj hhhNhNubh reference)}(h http://bluesmoke.sourceforge.neth]h http://bluesmoke.sourceforge.net}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1j hj ubhO. That site is mostly archaic now and can be used only for historical purposes.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj ubjq)}(hhWhen the subsystem was pushed upstream for the first time, on Kernel 2.6.16, it was renamed to ``EDAC``.h](h_When the subsystem was pushed upstream for the first time, on Kernel 2.6.16, it was renamed to }(hj hhhNhNubj)}(h``EDAC``h]hEDAC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj ubeh}(h]h ]h"]h$]h&]uh1j hj hhhhhNubj\)}(hhh](ja)}(hPurposeh]hPurpose}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubjq)}(hThe ``edac`` kernel module's goal is to detect and report hardware errors that occur within the computer system running under linux.h](hThe }(hj hhhNhNubj)}(h``edac``h]hedac}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhz kernel module’s goal is to detect and report hardware errors that occur within the computer system running under linux.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubeh}(h]purposeah ]h"]purposeah$]h&]uh1j[hj hhhhhKubj\)}(hhh](ja)}(hMemoryh]hMemory}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj+ hhhhhKubjq)}(hMemory Correctable Errors (CE) and Uncorrectable Errors (UE) are the primary errors being harvested. These types of errors are harvested by the ``edac_mc`` device.h](hMemory Correctable Errors (CE) and Uncorrectable Errors (UE) are the primary errors being harvested. These types of errors are harvested by the }(hj< hhhNhNubj)}(h ``edac_mc``h]hedac_mc}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj< ubh device.}(hj< hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj+ hhubjq)}(hDetecting CE events, then harvesting those events and reporting them, **can** but must not necessarily be a predictor of future UE events. With CE events only, the system can and will continue to operate as no data has been damaged yet.h](hFDetecting CE events, then harvesting those events and reporting them, }(hj\ hhhNhNubj)}(h**can**h]hcan}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ ubh but must not necessarily be a predictor of future UE events. With CE events only, the system can and will continue to operate as no data has been damaged yet.}(hj\ hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj+ hhubjq)}(hHowever, preventive maintenance and proactive part replacement of memory modules exhibiting CEs can reduce the likelihood of the dreaded UE events and system panics.h]hHowever, preventive maintenance and proactive part replacement of memory modules exhibiting CEs can reduce the likelihood of the dreaded UE events and system panics.}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj+ hhubeh}(h]memoryah ]h"]memoryah$]h&]uh1j[hj hhhhhKubj\)}(hhh](ja)}(hOther hardware elementsh]hOther hardware elements}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubjq)}(hkA new feature for EDAC, the ``edac_device`` class of device, was added in the 2.6.23 version of the kernel.h](hA new feature for EDAC, the }(hj hhhNhNubj)}(h``edac_device``h]h edac_device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh@ class of device, was added in the 2.6.23 version of the kernel.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj hhubjq)}(hThis new device type allows for non-memory type of ECC hardware detectors to have their states harvested and presented to userspace via the sysfs interface.h]hThis new device type allows for non-memory type of ECC hardware detectors to have their states harvested and presented to userspace via the sysfs interface.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj hhubjq)}(hX7Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA engines, fabric switches, main data path switches, interconnections, and various other hardware data paths. If the hardware reports it, then an edac_device device probably can be constructed to harvest and present that to userspace.h]hX7Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA engines, fabric switches, main data path switches, interconnections, and various other hardware data paths. If the hardware reports it, then an edac_device device probably can be constructed to harvest and present that to userspace.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj hhubeh}(h]other-hardware-elementsah ]h"]other hardware elementsah$]h&]uh1j[hj hhhhhKubj\)}(hhh](ja)}(hPCI bus scanningh]hPCI bus scanning}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhMubjq)}(hIn addition, PCI devices are scanned for PCI Bus Parity and SERR Errors in order to determine if errors are occurring during data transfers.h]hIn addition, PCI devices are scanned for PCI Bus Parity and SERR Errors in order to determine if errors are occurring during data transfers.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj hhubjq)}(hXThe presence of PCI Parity errors must be examined with a grain of salt. There are several add-in adapters that do **not** follow the PCI specification with regards to Parity generation and reporting. The specification says the vendor should tie the parity status bits to 0 if they do not intend to generate parity. Some vendors do not do this, and thus the parity bit can "float" giving false positives.h](hsThe presence of PCI Parity errors must be examined with a grain of salt. There are several add-in adapters that do }(hj hhhNhNubj)}(h**not**h]hnot}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhX follow the PCI specification with regards to Parity generation and reporting. The specification says the vendor should tie the parity status bits to 0 if they do not intend to generate parity. Some vendors do not do this, and thus the parity bit can “float” giving false positives.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM hj hhubjq)}(hThere is a PCI device attribute located in sysfs that is checked by the EDAC PCI scanning code. If that attribute is set, PCI parity/error scanning is skipped for that device. The attribute is::h]hThere is a PCI device attribute located in sysfs that is checked by the EDAC PCI scanning code. If that attribute is set, PCI parity/error scanning is skipped for that device. The attribute is:}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj hhubj)}(hbroken_parity_statush]hbroken_parity_status}hj4 sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj hhubjq)}(hUand is located in ``/sys/devices/pci/0000:XX:YY.Z`` directories for PCI devices.h](hand is located in }(hjB hhhNhNubj)}(h&``/sys/devices/pci/0000:XX:YY.Z``h]h"/sys/devices/pci/0000:XX:YY.Z}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB ubh directories for PCI devices.}(hjB hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj hhubeh}(h]pci-bus-scanningah ]h"]pci bus scanningah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h Versioningh]h Versioning}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjj hhhhhMubjq)}(hXFEDAC is composed of a "core" module (``edac_core.ko``) and several Memory Controller (MC) driver modules. On a given system, the CORE is loaded and one MC driver will be loaded. Both the CORE and the MC driver (or ``edac_device`` driver) have individual versions that reflect current release level of their respective modules.h](h)EDAC is composed of a “core” module (}(hj{ hhhNhNubj)}(h``edac_core.ko``h]h edac_core.ko}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubh) and several Memory Controller (MC) driver modules. On a given system, the CORE is loaded and one MC driver will be loaded. Both the CORE and the MC driver (or }(hj{ hhhNhNubj)}(h``edac_device``h]h edac_device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ ubha driver) have individual versions that reflect current release level of their respective modules.}(hj{ hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjj hhubjq)}(htThus, to "report" on what version a system is running, one must report both the CORE's and the MC driver's versions.h]h|Thus, to “report” on what version a system is running, one must report both the CORE’s and the MC driver’s versions.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM$hjj hhubeh}(h] versioningah ]h"] versioningah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(hLoadingh]hLoading}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhM)ubjq)}(hXIf ``edac`` was statically linked with the kernel then no loading is necessary. If ``edac`` was built as modules then simply modprobe the ``edac`` pieces that you need. You should be able to modprobe hardware-specific modules and have the dependencies load the necessary core modules.h](hIf }(hj hhhNhNubj)}(h``edac``h]hedac}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhH was statically linked with the kernel then no loading is necessary. If }(hj hhhNhNubj)}(h``edac``h]hedac}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh/ was built as modules then simply modprobe the }(hj hhhNhNubj)}(h``edac``h]hedac}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh pieces that you need. You should be able to modprobe hardware-specific modules and have the dependencies load the necessary core modules.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM+hj hhubjq)}(h Example::h]hExample:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM1hj hhubj)}(h$ modprobe amd76x_edach]h$ modprobe amd76x_edac}hj&sbah}(h]h ]h"]h$]h&]hhuh1jhhhM3hj hhubjq)}(h^loads both the ``amd76x_edac.ko`` memory controller module and the ``edac_mc.ko`` core module.h](hloads both the }(hj4hhhNhNubj)}(h``amd76x_edac.ko``h]hamd76x_edac.ko}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh" memory controller module and the }(hj4hhhNhNubj)}(h``edac_mc.ko``h]h edac_mc.ko}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh core module.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM5hj hhubeh}(h]loadingah ]h"]loadingah$]h&]uh1j[hj hhhhhM)ubj\)}(hhh](ja)}(hSysfs interfaceh]hSysfs interface}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjnhhhhhM:ubjq)}(h{EDAC presents a ``sysfs`` interface for control and reporting purposes. It lives in the /sys/devices/system/edac directory.h](hEDAC presents a }(hjhhhNhNubj)}(h ``sysfs``h]hsysfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhb interface for control and reporting purposes. It lives in the /sys/devices/system/edac directory.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM<hjnhhubjq)}(h:Within this directory there currently reside 2 components:h]h:Within this directory there currently reside 2 components:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM?hjnhhubh block_quote)}(h======= ============================== mc memory controller(s) system pci PCI control and status system ======= ============================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]jq)}(hmch]hmc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMBhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hmemory controller(s) systemh]hmemory controller(s) system}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMBhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hpcih]hpci}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMChjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hPCI control and status systemh]hPCI control and status system}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMChj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhMAhjnhhubeh}(h]sysfs-interfaceah ]h"]sysfs interfaceah$]h&]uh1j[hj hhhhhM:ubj\)}(hhh](ja)}(hMemory Controller (mc) Modelh]hMemory Controller (mc) Model}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjkhhhhhMIubjq)}(hEach ``mc`` device controls a set of memory modules [#f4]_. These modules are laid out in a Chip-Select Row (``csrowX``) and Channel table (``chX``). There can be multiple csrows and multiple channels.h](hEach }(hj|hhhNhNubj)}(h``mc``h]hmc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh) device controls a set of memory modules }(hj|hhhNhNubj )}(h[#f4]_h]h4}(hjhhhNhNubah}(h]id4ah ]h"]h$]h&]j Kj f4j j uh1j hj|j Kubh3. These modules are laid out in a Chip-Select Row (}(hj|hhhNhNubj)}(h ``csrowX``h]hcsrowX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh) and Channel table (}(hj|hhhNhNubj)}(h``chX``h]hchX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh6). There can be multiple csrows and multiple channels.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMKhjkhhubj )}(hXNowadays, the term DIMM (Dual In-line Memory Module) is widely used to refer to a memory module, although there are other memory packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI specification (Version 2.7) defines a memory module in the Common Platform Error Record (CPER) section to be an SMBIOS Memory Device (Type 17). Along this document, and inside the EDAC subsystem, the term "dimm" is used for all memory modules, even when they use a different kind of packaging. h](j )}(hhh]h4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubjq)}(hXNowadays, the term DIMM (Dual In-line Memory Module) is widely used to refer to a memory module, although there are other memory packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI specification (Version 2.7) defines a memory module in the Common Platform Error Record (CPER) section to be an SMBIOS Memory Device (Type 17). Along this document, and inside the EDAC subsystem, the term "dimm" is used for all memory modules, even when they use a different kind of packaging.h]hXNowadays, the term DIMM (Dual In-line Memory Module) is widely used to refer to a memory module, although there are other memory packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI specification (Version 2.7) defines a memory module in the Common Platform Error Record (CPER) section to be an SMBIOS Memory Device (Type 17). Along this document, and inside the EDAC subsystem, the term “dimm” is used for all memory modules, even when they use a different kind of packaging.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMOhjubeh}(h]jah ]h"]f4ah$]h&]jaj Kj j uh1j hhhMOhjkhhubjq)}(hMemory controllers allow for several csrows, with 8 csrows being a typical value. Yet, the actual number of csrows depends on the layout of a given motherboard, memory controller and memory module characteristics.h]hMemory controllers allow for several csrows, with 8 csrows being a typical value. Yet, the actual number of csrows depends on the layout of a given motherboard, memory controller and memory module characteristics.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMXhjkhhubjq)}(hXDual channels allow for dual data length (e. g. 128 bits, on 64 bit systems) data transfers to/from the CPU from/to memory. Some newer chipsets allow for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory controllers. The following example will assume 2 channels:h]hXDual channels allow for dual data length (e. g. 128 bits, on 64 bit systems) data transfers to/from the CPU from/to memory. Some newer chipsets allow for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory controllers. The following example will assume 2 channels:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM\hjkhhubj)}(hX+------------+-----------------------+ | CS Rows | Channels | +------------+-----------+-----------+ | | ``ch0`` | ``ch1`` | +============+===========+===========+ | |**DIMM_A0**|**DIMM_B0**| +------------+-----------+-----------+ | ``csrow0`` | rank0 | rank0 | +------------+-----------+-----------+ | ``csrow1`` | rank1 | rank1 | +------------+-----------+-----------+ | |**DIMM_A1**|**DIMM_B1**| +------------+-----------+-----------+ | ``csrow2`` | rank0 | rank0 | +------------+-----------+-----------+ | ``csrow3`` | rank1 | rank1 | +------------+-----------+-----------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubhthead)}(hhh](j)}(hhh](j)}(hhh]jq)}(hCS Rowsh]hCS Rows}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMbhjFubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]jq)}(hChannelsh]hChannels}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMbhj]ubah}(h]h ]h"]h$]h&]morecolsKuh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhj@ubj)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]jq)}(h``ch0``h]j)}(hjh]hch0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMdhjubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]jq)}(h``ch1``h]j)}(hjh]hch1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMdhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1j>hjubj)}(hhh](j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(h **DIMM_A0**h]j)}(hjh]hDIMM_A0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMfhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(h **DIMM_B0**h]j)}(hjh]hDIMM_B0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h ``csrow0``h]j)}(hj0h]hcsrow0}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jphhhMhhj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]jq)}(hrank0h]hrank0}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhhjKubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]jq)}(hrank0h]hrank0}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhhjbubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h ``csrow1``h]j)}(hjh]hcsrow1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMjhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hrank1h]hrank1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMjhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hrank1h]hrank1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(h **DIMM_A1**h]j)}(hjh]hDIMM_A1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMlhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(h **DIMM_B1**h]j)}(hjh]hDIMM_B1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h ``csrow2``h]j)}(hj0h]hcsrow2}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jphhhMnhj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]jq)}(hrank0h]hrank0}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMnhjKubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]jq)}(hrank0h]hrank0}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMnhjbubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h ``csrow3``h]j)}(hjh]hcsrow3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphhhMphjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hrank1h]hrank1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMphjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hrank1h]hrank1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMphjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhMahjkhhubjq)}(hUIn the above example, there are 4 physical slots on the motherboard for memory DIMMs:h]hUIn the above example, there are 4 physical slots on the motherboard for memory DIMMs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMshjkhhubj)}(hn+---------+---------+ | DIMM_A0 | DIMM_B0 | +---------+---------+ | DIMM_A1 | DIMM_B1 | +---------+---------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]jq)}(hDIMM_A0h]hDIMM_A0}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMwhj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hDIMM_B0h]hDIMM_B0}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMwhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hDIMM_A1h]hDIMM_A1}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMyhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]jq)}(hDIMM_B1h]hDIMM_B1}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMyhjoubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhMvhjkhhubjq)}(hXLabels for these slots are usually silk-screened on the motherboard. Slots labeled ``A`` are channel 0 in this example. Slots labeled ``B`` are channel 1. Notice that there are two csrows possible on a physical DIMM. These csrows are allocated their csrow assignment based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM is placed in each Channel, the csrows cross both DIMMs.h](hSLabels for these slots are usually silk-screened on the motherboard. Slots labeled }(hjhhhNhNubj)}(h``A``h]hA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. are channel 0 in this example. Slots labeled }(hjhhhNhNubj)}(h``B``h]hB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX are channel 1. Notice that there are two csrows possible on a physical DIMM. These csrows are allocated their csrow assignment based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM is placed in each Channel, the csrows cross both DIMMs.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM|hjkhhubjq)}(hXMemory DIMMs come single or dual "ranked". A rank is a populated csrow. In the example above 2 dual ranked DIMMs are similarly placed. Thus, both csrow0 and csrow1 are populated. On the other hand, when 2 single ranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they will have just one csrow (csrow0) and csrow1 will be empty. The pattern repeats itself for csrow2 and csrow3. Also note that some memory controllers don't have any logic to identify the memory module, see ``rankX`` directories below.h](hXMemory DIMMs come single or dual “ranked”. A rank is a populated csrow. In the example above 2 dual ranked DIMMs are similarly placed. Thus, both csrow0 and csrow1 are populated. On the other hand, when 2 single ranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they will have just one csrow (csrow0) and csrow1 will be empty. The pattern repeats itself for csrow2 and csrow3. Also note that some memory controllers don’t have any logic to identify the memory module, see }(hjhhhNhNubj)}(h ``rankX``h]hrankX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh directories below.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjkhhubjq)}(hXThe representation of the above is reflected in the directory tree in EDAC's sysfs interface. Starting in directory ``/sys/devices/system/edac/mc``, each memory controller will be represented by its own ``mcX`` directory, where ``X`` is the index of the MC::h](hvThe representation of the above is reflected in the directory tree in EDAC’s sysfs interface. Starting in directory }(hjhhhNhNubj)}(h``/sys/devices/system/edac/mc``h]h/sys/devices/system/edac/mc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh8, each memory controller will be represented by its own }(hjhhhNhNubj)}(h``mcX``h]hmcX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh directory, where }(hjhhhNhNubj)}(h``X``h]hX}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is the index of the MC:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjkhhubj)}(h`..../edac/mc/ | |->mc0 |->mc1 |->mc2 ....h]h`..../edac/mc/ | |->mc0 |->mc1 |->mc2 ....}hj;sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjkhhubjq)}(hRWithin each of the ``mcX`` directory are several EDAC control and attribute files.h](hWithin each of the }(hjIhhhNhNubj)}(h``mcX``h]hmcX}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubh8 directory are several EDAC control and attribute files.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjkhhubeh}(h]memory-controller-mc-modelah ]h"]memory controller (mc) modelah$]h&]uh1j[hj hhhhhMIubj\)}(hhh](ja)}(h``mcX`` directoriesh](j)}(h``mcX``h]hmcX}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh directories}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1j`hjqhhhhhMubjq)}(hnIn ``mcX`` directories are EDAC control and attribute files for this ``X`` instance of the memory controllers.h](hIn }(hjhhhNhNubj)}(h``mcX``h]hmcX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh; directories are EDAC control and attribute files for this }(hjhhhNhNubj)}(h``X``h]hX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh$ instance of the memory controllers.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjqhhubjq)}(h/For a description of the sysfs API, please see:h]h/For a description of the sysfs API, please see:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjqhhubj)}(h.Documentation/ABI/testing/sysfs-devices-edac h]jq)}(h,Documentation/ABI/testing/sysfs-devices-edach]h,Documentation/ABI/testing/sysfs-devices-edac}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjqhhubeh}(h]mcx-directoriesah ]h"]mcx directoriesah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h"``dimmX`` or ``rankX`` directoriesh](j)}(h ``dimmX``h]hdimmX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh or }(hjhhhNhNubj)}(h ``rankX``h]hrankX}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh directories}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j`hjhhhhhMubjq)}(hThe recommended way to use the EDAC subsystem is to look at the information provided by the ``dimmX`` or ``rankX`` directories [#f5]_.h](h\The recommended way to use the EDAC subsystem is to look at the information provided by the }(hj!hhhNhNubj)}(h ``dimmX``h]hdimmX}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh or }(hj!hhhNhNubj)}(h ``rankX``h]hrankX}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh directories }(hj!hhhNhNubj )}(h[#f5]_h]h5}(hjMhhhNhNubah}(h]id5ah ]h"]h$]h&]j Kj f5j j uh1j hj!j Kubh.}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjhhubjq)}(h_A typical EDAC system has the following structure under ``/sys/devices/system/edac/``\ [#f6]_::h](h8A typical EDAC system has the following structure under }(hjghhhNhNubj)}(h``/sys/devices/system/edac/``h]h/sys/devices/system/edac/}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubh }(hjghhhNhNubj )}(h[#f6]_h]h6}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]j Kj f6j j uh1j hjgj Kubh:}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjhhubj)}(hX/sys/devices/system/edac/ ├── mc │   ├── mc0 │   │   ├── ce_count │   │   ├── ce_noinfo_count │   │   ├── dimm0 │   │   │   ├── dimm_ce_count │   │   │   ├── dimm_dev_type │   │   │   ├── dimm_edac_mode │   │   │   ├── dimm_label │   │   │   ├── dimm_location │   │   │   ├── dimm_mem_type │   │   │   ├── dimm_ue_count │   │   │   ├── size │   │   │   └── uevent │   │   ├── max_location │   │   ├── mc_name │   │   ├── reset_counters │   │   ├── seconds_since_reset │   │   ├── size_mb │   │   ├── ue_count │   │   ├── ue_noinfo_count │   │   └── uevent │   ├── mc1 │   │   ├── ce_count │   │   ├── ce_noinfo_count │   │   ├── dimm0 │   │   │   ├── dimm_ce_count │   │   │   ├── dimm_dev_type │   │   │   ├── dimm_edac_mode │   │   │   ├── dimm_label │   │   │   ├── dimm_location │   │   │   ├── dimm_mem_type │   │   │   ├── dimm_ue_count │   │   │   ├── size │   │   │   └── uevent │   │   ├── max_location │   │   ├── mc_name │   │   ├── reset_counters │   │   ├── seconds_since_reset │   │   ├── size_mb │   │   ├── ue_count │   │   ├── ue_noinfo_count │   │   └── uevent │   └── uevent └── ueventh]hX/sys/devices/system/edac/ ├── mc │   ├── mc0 │   │   ├── ce_count │   │   ├── ce_noinfo_count │   │   ├── dimm0 │   │   │   ├── dimm_ce_count │   │   │   ├── dimm_dev_type │   │   │   ├── dimm_edac_mode │   │   │   ├── dimm_label │   │   │   ├── dimm_location │   │   │   ├── dimm_mem_type │   │   │   ├── dimm_ue_count │   │   │   ├── size │   │   │   └── uevent │   │   ├── max_location │   │   ├── mc_name │   │   ├── reset_counters │   │   ├── seconds_since_reset │   │   ├── size_mb │   │   ├── ue_count │   │   ├── ue_noinfo_count │   │   └── uevent │   ├── mc1 │   │   ├── ce_count │   │   ├── ce_noinfo_count │   │   ├── dimm0 │   │   │   ├── dimm_ce_count │   │   │   ├── dimm_dev_type │   │   │   ├── dimm_edac_mode │   │   │   ├── dimm_label │   │   │   ├── dimm_location │   │   │   ├── dimm_mem_type │   │   │   ├── dimm_ue_count │   │   │   ├── size │   │   │   └── uevent │   │   ├── max_location │   │   ├── mc_name │   │   ├── reset_counters │   │   ├── seconds_since_reset │   │   ├── size_mb │   │   ├── ue_count │   │   ├── ue_noinfo_count │   │   └── uevent │   └── uevent └── uevent}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjhhubjq)}(h_In the ``dimmX`` directories are EDAC control and attribute files for this ``X`` memory module:h](hIn the }(hjhhhNhNubj)}(h ``dimmX``h]hdimmX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh; directories are EDAC control and attribute files for this }(hjhhhNhNubj)}(h``X``h]hX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh memory module:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjhhubj)}(hhh](j)}(h``size`` - Total memory managed by this csrow attribute file This attribute file displays, in count of megabytes, the memory that this csrow contains. h](jq)}(h<``size`` - Total memory managed by this csrow attribute fileh](j)}(h``size``h]hsize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh4 - Total memory managed by this csrow attribute file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hZThis attribute file displays, in count of megabytes, the memory that this csrow contains. h]jq)}(hYThis attribute file displays, in count of megabytes, the memory that this csrow contains.h]hYThis attribute file displays, in count of megabytes, the memory that this csrow contains.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX'``dimm_ue_count`` - Uncorrectable Errors count attribute file This attribute file displays the total count of uncorrectable errors that have occurred on this DIMM. If panic_on_ue is set this counter will not have a chance to increment, since EDAC will panic the system. h](jq)}(h=``dimm_ue_count`` - Uncorrectable Errors count attribute fileh](j)}(h``dimm_ue_count``h]h dimm_ue_count}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh, - Uncorrectable Errors count attribute file}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hThis attribute file displays the total count of uncorrectable errors that have occurred on this DIMM. If panic_on_ue is set this counter will not have a chance to increment, since EDAC will panic the system. h]jq)}(hThis attribute file displays the total count of uncorrectable errors that have occurred on this DIMM. If panic_on_ue is set this counter will not have a chance to increment, since EDAC will panic the system.h]hThis attribute file displays the total count of uncorrectable errors that have occurred on this DIMM. If panic_on_ue is set this counter will not have a chance to increment, since EDAC will panic the system.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX``dimm_ce_count`` - Correctable Errors count attribute file This attribute file displays the total count of correctable errors that have occurred on this DIMM. This count is very important to examine. CEs provide early indications that a DIMM is beginning to fail. This count field should be monitored for non-zero values and report such information to the system administrator. h](jq)}(h;``dimm_ce_count`` - Correctable Errors count attribute fileh](j)}(h``dimm_ce_count``h]h dimm_ce_count}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubh* - Correctable Errors count attribute file}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjZubj)}(hX?This attribute file displays the total count of correctable errors that have occurred on this DIMM. This count is very important to examine. CEs provide early indications that a DIMM is beginning to fail. This count field should be monitored for non-zero values and report such information to the system administrator. h]jq)}(hX>This attribute file displays the total count of correctable errors that have occurred on this DIMM. This count is very important to examine. CEs provide early indications that a DIMM is beginning to fail. This count field should be monitored for non-zero values and report such information to the system administrator.h]hX>This attribute file displays the total count of correctable errors that have occurred on this DIMM. This count is very important to examine. CEs provide early indications that a DIMM is beginning to fail. This count field should be monitored for non-zero values and report such information to the system administrator.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjzubah}(h]h ]h"]h$]h&]uh1jhhhMhjZubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h``dimm_dev_type`` - Device type attribute file This attribute file will display what type of DRAM device is being utilized on this DIMM. Examples: - x1 - x2 - x4 - x8 h](jq)}(h/``dimm_dev_type`` - Device type attribute fileh](j)}(h``dimm_dev_type``h]h dimm_dev_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Device type attribute file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hThis attribute file will display what type of DRAM device is being utilized on this DIMM. Examples: - x1 - x2 - x4 - x8 h](jq)}(hcThis attribute file will display what type of DRAM device is being utilized on this DIMM. Examples:h]hcThis attribute file will display what type of DRAM device is being utilized on this DIMM. Examples:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(h- x1 - x2 - x4 - x8 h]j)}(hhh](j)}(hx1h]jq)}(hjh]hx1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hx2h]jq)}(hjh]hx2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hx4h]jq)}(hjh]hx4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hx8 h]jq)}(hx8h]hx8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j -uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h``dimm_edac_mode`` - EDAC Mode of operation attribute file This attribute file will display what type of Error detection and correction is being utilized. h](jq)}(h:``dimm_edac_mode`` - EDAC Mode of operation attribute fileh](j)}(h``dimm_edac_mode``h]hdimm_edac_mode}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubh( - EDAC Mode of operation attribute file}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjGubj)}(h`This attribute file will display what type of Error detection and correction is being utilized. h]jq)}(h_This attribute file will display what type of Error detection and correction is being utilized.h]h_This attribute file will display what type of Error detection and correction is being utilized.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjgubah}(h]h ]h"]h$]h&]uh1jhhhMhjGubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXo``dimm_label`` - memory module label control file This control file allows this DIMM to have a label assigned to it. With this label in the module, when errors occur the output can provide the DIMM label in the system log. This becomes vital for panic events to isolate the cause of the UE event. DIMM Labels must be assigned after booting, with information that correctly identifies the physical slot with its silk screen label. This information is currently very motherboard specific and determination of this information must occur in userland at this time. h](jq)}(h1``dimm_label`` - memory module label control fileh](j)}(h``dimm_label``h]h dimm_label}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# - memory module label control file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hXThis control file allows this DIMM to have a label assigned to it. With this label in the module, when errors occur the output can provide the DIMM label in the system log. This becomes vital for panic events to isolate the cause of the UE event. DIMM Labels must be assigned after booting, with information that correctly identifies the physical slot with its silk screen label. This information is currently very motherboard specific and determination of this information must occur in userland at this time. h](jq)}(hThis control file allows this DIMM to have a label assigned to it. With this label in the module, when errors occur the output can provide the DIMM label in the system log. This becomes vital for panic events to isolate the cause of the UE event.h]hThis control file allows this DIMM to have a label assigned to it. With this label in the module, when errors occur the output can provide the DIMM label in the system log. This becomes vital for panic events to isolate the cause of the UE event.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM hjubjq)}(hXDIMM Labels must be assigned after booting, with information that correctly identifies the physical slot with its silk screen label. This information is currently very motherboard specific and determination of this information must occur in userland at this time.h]hXDIMM Labels must be assigned after booting, with information that correctly identifies the physical slot with its silk screen label. This information is currently very motherboard specific and determination of this information must occur in userland at this time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXQ``dimm_location`` - location of the memory module The location can have up to 3 levels, and describe how the memory controller identifies the location of a memory module. Depending on the type of memory and memory controller, it can be: - *csrow* and *channel* - used when the memory controller doesn't identify a single DIMM - e. g. in ``rankX`` dir; - *branch*, *channel*, *slot* - typically used on FB-DIMM memory controllers; - *channel*, *slot* - used on Nehalem and newer Intel drivers. h](jq)}(h1``dimm_location`` - location of the memory moduleh](j)}(h``dimm_location``h]h dimm_location}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - location of the memory module}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hXThe location can have up to 3 levels, and describe how the memory controller identifies the location of a memory module. Depending on the type of memory and memory controller, it can be: - *csrow* and *channel* - used when the memory controller doesn't identify a single DIMM - e. g. in ``rankX`` dir; - *branch*, *channel*, *slot* - typically used on FB-DIMM memory controllers; - *channel*, *slot* - used on Nehalem and newer Intel drivers. h](jq)}(hThe location can have up to 3 levels, and describe how the memory controller identifies the location of a memory module. Depending on the type of memory and memory controller, it can be:h]hThe location can have up to 3 levels, and describe how the memory controller identifies the location of a memory module. Depending on the type of memory and memory controller, it can be:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hX- *csrow* and *channel* - used when the memory controller doesn't identify a single DIMM - e. g. in ``rankX`` dir; - *branch*, *channel*, *slot* - typically used on FB-DIMM memory controllers; - *channel*, *slot* - used on Nehalem and newer Intel drivers. h]j)}(hhh](j)}(hp*csrow* and *channel* - used when the memory controller doesn't identify a single DIMM - e. g. in ``rankX`` dir;h]jq)}(hp*csrow* and *channel* - used when the memory controller doesn't identify a single DIMM - e. g. in ``rankX`` dir;h](j)}(h*csrow*h]hcsrow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h *channel*h]hchannel}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhO - used when the memory controller doesn’t identify a single DIMM - e. g. in }(hjhhhNhNubj)}(h ``rankX``h]hrankX}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh dir;}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hK*branch*, *channel*, *slot* - typically used on FB-DIMM memory controllers;h]jq)}(hK*branch*, *channel*, *slot* - typically used on FB-DIMM memory controllers;h](j)}(h*branch*h]hbranch}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh, }(hjXhhhNhNubj)}(h *channel*h]hchannel}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh, }hjXsbj)}(h*slot*h]hslot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh0 - typically used on FB-DIMM memory controllers;}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjTubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h=*channel*, *slot* - used on Nehalem and newer Intel drivers. h]jq)}(h<*channel*, *slot* - used on Nehalem and newer Intel drivers.h](j)}(h *channel*h]hchannel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, }(hjhhhNhNubj)}(h*slot*h]hslot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh+ - used on Nehalem and newer Intel drivers.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j j4uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX ``dimm_mem_type`` - Memory Type attribute file This attribute file will display what type of memory is currently on this csrow. Normally, either buffered or unbuffered memory. Examples: - Registered-DDR - Unbuffered-DDR h](jq)}(h.``dimm_mem_type`` - Memory Type attribute fileh](j)}(h``dimm_mem_type``h]h dimm_mem_type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Memory Type attribute file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM"hjubj)}(hThis attribute file will display what type of memory is currently on this csrow. Normally, either buffered or unbuffered memory. Examples: - Registered-DDR - Unbuffered-DDR h](jq)}(hThis attribute file will display what type of memory is currently on this csrow. Normally, either buffered or unbuffered memory. Examples:h]hThis attribute file will display what type of memory is currently on this csrow. Normally, either buffered or unbuffered memory. Examples:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM$hjubj)}(h"- Registered-DDR - Unbuffered-DDR h]j)}(hhh](j)}(hRegistered-DDRh]jq)}(hj)h]hRegistered-DDR}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM(hj'ubah}(h]h ]h"]h$]h&]uh1jhj$ubj)}(hUnbuffered-DDR h]jq)}(hUnbuffered-DDRh]hUnbuffered-DDR}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM)hj>ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]j j4uh1jhhhM(hj ubah}(h]h ]h"]h$]h&]uh1jhhhM(hjubeh}(h]h ]h"]h$]h&]uh1jhhhM$hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j j4uh1jhhhMhjhhubj )}(hX'On some systems, the memory controller doesn't have any logic to identify the memory module. On such systems, the directory is called ``rankX``. On modern Intel memory controllers, the memory controller identifies the memory modules directly. On such systems, the directory is called ``dimmX``. h](j )}(hhh]h5}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjthhhNhNubjq)}(hX&On some systems, the memory controller doesn't have any logic to identify the memory module. On such systems, the directory is called ``rankX``. On modern Intel memory controllers, the memory controller identifies the memory modules directly. On such systems, the directory is called ``dimmX``.h](hOn some systems, the memory controller doesn’t have any logic to identify the memory module. On such systems, the directory is called }(hjhhhNhNubj)}(h ``rankX``h]hrankX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. On modern Intel memory controllers, the memory controller identifies the memory modules directly. On such systems, the directory is called }(hjhhhNhNubj)}(h ``dimmX``h]hdimmX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM+hjtubeh}(h]j\ah ]h"]f5ah$]h&]jWaj Kj j uh1j hhhM+hjhhubj )}(hThere are also some ``power`` directories and ``subsystem`` symlinks inside the sysfs mapping that are automatically created by the sysfs subsystem. Currently, they serve no purpose. h](j )}(hhh]h6}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubjq)}(hThere are also some ``power`` directories and ``subsystem`` symlinks inside the sysfs mapping that are automatically created by the sysfs subsystem. Currently, they serve no purpose.h](hThere are also some }(hjhhhNhNubj)}(h ``power``h]hpower}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh directories and }(hjhhhNhNubj)}(h ``subsystem``h]h subsystem}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh{ symlinks inside the sysfs mapping that are automatically created by the sysfs subsystem. Currently, they serve no purpose.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM0hjubeh}(h]jah ]h"]f6ah$]h&]jaj Kj j uh1j hhhM0hjhhubeh}(h]dimmx-or-rankx-directoriesah ]h"]dimmx or rankx directoriesah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(hSystem Loggingh]hSystem Logging}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhM6ubjq)}(h|If logging for UEs and CEs is enabled, then system logs will contain information indicating that errors have been detected::h]h{If logging for UEs and CEs is enabled, then system logs will contain information indicating that errors have been detected:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM8hjhhubj)}(hEDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edach]hEDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac}hj/sbah}(h]h ]h"]h$]h&]hhuh1jhhhM;hjhhubjq)}(h The structure of the message is:h]h The structure of the message is:}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM?hjhhubj)}(hX+---------------------------------------+-------------+ | Content | Example | +=======================================+=============+ | The memory controller | MC0 | +---------------------------------------+-------------+ | Error type | CE | +---------------------------------------+-------------+ | Memory page | 0x283 | +---------------------------------------+-------------+ | Offset in the page | 0xce0 | +---------------------------------------+-------------+ | The byte granularity | grain 8 | | or resolution of the error | | +---------------------------------------+-------------+ | The error syndrome | 0xb741 | +---------------------------------------+-------------+ | Memory row | row 0 | +---------------------------------------+-------------+ | Memory channel | channel 1 | +---------------------------------------+-------------+ | DIMM label, if set prior | DIMM B1 | +---------------------------------------+-------------+ | And then an optional, driver-specific | | | message that may have additional | | | information. | | +---------------------------------------+-------------+ h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK'uh1jhjRubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjRubj?)}(hhh]j)}(hhh](j)}(hhh]jq)}(hContenth]hContent}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMBhjoubah}(h]h ]h"]h$]h&]uh1jhjlubj)}(hhh]jq)}(hExampleh]hExample}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMBhjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1j>hjRubj)}(hhh](j)}(hhh](j)}(hhh]jq)}(hThe memory controllerh]hThe memory controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hMC0h]hMC0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h Error typeh]h Error type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hCEh]hCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h Memory pageh]h Memory page}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMHhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(h0x283h]h0x283}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMHhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hOffset in the pageh]hOffset in the page}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMJhjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]jq)}(h0xce0h]h0xce0}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMJhjkubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h/The byte granularity or resolution of the errorh]h/The byte granularity or resolution of the error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hgrain 8h]hgrain 8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hThe error syndromeh]hThe error syndrome}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMOhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(h0xb741h]h0xb741}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMOhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(h Memory rowh]h Memory row}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMQhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jq)}(hrow 0h]hrow 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hMemory channelh]hMemory channel}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMShj0ubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]jq)}(h channel 1h]h channel 1}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMShjGubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hDIMM label, if set priorh]hDIMM label, if set prior}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMUhjgubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]jq)}(hDIMM B1h]hDIMM B1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMUhj~ubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jq)}(hSAnd then an optional, driver-specific message that may have additional information.h]hSAnd then an optional, driver-specific message that may have additional information.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMWhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]colsKuh1jhjOubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhhhMAhjhhubjq)}(hBoth UEs and CEs with no info will lack all but memory controller, error type, a notice of "no info" and then an optional, driver-specific error message.h]hBoth UEs and CEs with no info will lack all but memory controller, error type, a notice of “no info” and then an optional, driver-specific error message.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM\hjhhubeh}(h]system-loggingah ]h"]system loggingah$]h&]uh1j[hj hhhhhM6ubj\)}(hhh](ja)}(hPCI Bus Parity Detectionh]hPCI Bus Parity Detection}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhMbubjq)}(hXVOn Header Type 00 devices, the primary status is looked at for any parity error regardless of whether parity is enabled on the device or not. (The spec indicates parity is generated in some cases). On Header Type 01 bridges, the secondary status register is also looked at to see if parity occurred on the bus on the other side of the bridge.h]hXVOn Header Type 00 devices, the primary status is looked at for any parity error regardless of whether parity is enabled on the device or not. (The spec indicates parity is generated in some cases). On Header Type 01 bridges, the secondary status register is also looked at to see if parity occurred on the bus on the other side of the bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMdhjhhubeh}(h]pci-bus-parity-detectionah ]h"]pci bus parity detectionah$]h&]uh1j[hj hhhhhMbubj\)}(hhh](ja)}(hSysfs configurationh]hSysfs configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhMlubjq)}(hRUnder ``/sys/devices/system/edac/pci`` are control and attribute files as follows:h](hUnder }(hj+hhhNhNubj)}(h ``/sys/devices/system/edac/pci``h]h/sys/devices/system/edac/pci}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh, are control and attribute files as follows:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMnhjhhubj)}(hhh](j)}(hX``check_pci_parity`` - Enable/Disable PCI Parity checking control file This control file enables or disables the PCI Bus Parity scanning operation. Writing a 1 to this file enables the scanning. Writing a 0 to this file disables the scanning. Enable:: echo "1" >/sys/devices/system/edac/pci/check_pci_parity Disable:: echo "0" >/sys/devices/system/edac/pci/check_pci_parity h](jq)}(hF``check_pci_parity`` - Enable/Disable PCI Parity checking control fileh](j)}(h``check_pci_parity``h]hcheck_pci_parity}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubh2 - Enable/Disable PCI Parity checking control file}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMrhjNubj)}(hXDThis control file enables or disables the PCI Bus Parity scanning operation. Writing a 1 to this file enables the scanning. Writing a 0 to this file disables the scanning. Enable:: echo "1" >/sys/devices/system/edac/pci/check_pci_parity Disable:: echo "0" >/sys/devices/system/edac/pci/check_pci_parity h](jq)}(hThis control file enables or disables the PCI Bus Parity scanning operation. Writing a 1 to this file enables the scanning. Writing a 0 to this file disables the scanning.h]hThis control file enables or disables the PCI Bus Parity scanning operation. Writing a 1 to this file enables the scanning. Writing a 0 to this file disables the scanning.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMthjnubjq)}(hEnable::h]hEnable:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMxhjnubj)}(h7echo "1" >/sys/devices/system/edac/pci/check_pci_parityh]h7echo "1" >/sys/devices/system/edac/pci/check_pci_parity}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMzhjnubjq)}(h Disable::h]hDisable:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM|hjnubj)}(h7echo "0" >/sys/devices/system/edac/pci/check_pci_parityh]h7echo "0" >/sys/devices/system/edac/pci/check_pci_parity}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhM~hjnubeh}(h]h ]h"]h$]h&]uh1jhhhMthjNubeh}(h]h ]h"]h$]h&]uh1jhjKhhhhhNubj)}(h``pci_parity_count`` - Parity Count This attribute file will display the number of parity errors that have been detected. h](jq)}(h#``pci_parity_count`` - Parity Counth](j)}(h``pci_parity_count``h]hpci_parity_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Parity Count}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hWThis attribute file will display the number of parity errors that have been detected. h]jq)}(hUThis attribute file will display the number of parity errors that have been detected.h]hUThis attribute file will display the number of parity errors that have been detected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjKhhhhhNubeh}(h]h ]h"]h$]h&]j j4uh1jhhhMrhjhhubeh}(h]sysfs-configurationah ]h"]sysfs configurationah$]h&]uh1j[hj hhhhhMlubj\)}(hhh](ja)}(hModule parametersh]hModule parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhMubj)}(hhh](j)}(hXv``edac_mc_panic_on_ue`` - Panic on UE control file An uncorrectable error will cause a machine panic. This is usually desirable. It is a bad idea to continue when an uncorrectable error occurs - it is indeterminate what was uncorrected and the operating system context might be so mangled that continuing will lead to further corruption. If the kernel has MCE configured, then EDAC will never notice the UE. LOAD TIME:: module/kernel parameter: edac_mc_panic_on_ue=[0|1] RUN TIME:: echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue h](jq)}(h2``edac_mc_panic_on_ue`` - Panic on UE control fileh](j)}(h``edac_mc_panic_on_ue``h]hedac_mc_panic_on_ue}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubh - Panic on UE control file}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj$ubj)}(hXAn uncorrectable error will cause a machine panic. This is usually desirable. It is a bad idea to continue when an uncorrectable error occurs - it is indeterminate what was uncorrected and the operating system context might be so mangled that continuing will lead to further corruption. If the kernel has MCE configured, then EDAC will never notice the UE. LOAD TIME:: module/kernel parameter: edac_mc_panic_on_ue=[0|1] RUN TIME:: echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue h](jq)}(hXfAn uncorrectable error will cause a machine panic. This is usually desirable. It is a bad idea to continue when an uncorrectable error occurs - it is indeterminate what was uncorrected and the operating system context might be so mangled that continuing will lead to further corruption. If the kernel has MCE configured, then EDAC will never notice the UE.h]hXfAn uncorrectable error will cause a machine panic. This is usually desirable. It is a bad idea to continue when an uncorrectable error occurs - it is indeterminate what was uncorrected and the operating system context might be so mangled that continuing will lead to further corruption. If the kernel has MCE configured, then EDAC will never notice the UE.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjDubjq)}(h LOAD TIME::h]h LOAD TIME:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjDubj)}(h2module/kernel parameter: edac_mc_panic_on_ue=[0|1]h]h2module/kernel parameter: edac_mc_panic_on_ue=[0|1]}hjdsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjDubjq)}(h RUN TIME::h]h RUN TIME:}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjDubj)}(h?echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ueh]h?echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjDubeh}(h]h ]h"]h$]h&]uh1jhhhMhj$ubeh}(h]h ]h"]h$]h&]uh1jhj!hhhhhNubj)}(hX``edac_mc_log_ue`` - Log UE control file Generate kernel messages describing uncorrectable errors. These errors are reported through the system message log system. UE statistics will be accumulated even when UE logging is disabled. LOAD TIME:: module/kernel parameter: edac_mc_log_ue=[0|1] RUN TIME:: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue h](jq)}(h(``edac_mc_log_ue`` - Log UE control fileh](j)}(h``edac_mc_log_ue``h]hedac_mc_log_ue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Log UE control file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hXVGenerate kernel messages describing uncorrectable errors. These errors are reported through the system message log system. UE statistics will be accumulated even when UE logging is disabled. LOAD TIME:: module/kernel parameter: edac_mc_log_ue=[0|1] RUN TIME:: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue h](jq)}(hGenerate kernel messages describing uncorrectable errors. These errors are reported through the system message log system. UE statistics will be accumulated even when UE logging is disabled.h]hGenerate kernel messages describing uncorrectable errors. These errors are reported through the system message log system. UE statistics will be accumulated even when UE logging is disabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubjq)}(h LOAD TIME::h]h LOAD TIME:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(h-module/kernel parameter: edac_mc_log_ue=[0|1]h]h-module/kernel parameter: edac_mc_log_ue=[0|1]}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubjq)}(h RUN TIME::h]h RUN TIME:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(h:echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ueh]h:echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhj!hhhhhNubj)}(hX``edac_mc_log_ce`` - Log CE control file Generate kernel messages describing correctable errors. These errors are reported through the system message log system. CE statistics will be accumulated even when CE logging is disabled. LOAD TIME:: module/kernel parameter: edac_mc_log_ce=[0|1] RUN TIME:: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce h](jq)}(h(``edac_mc_log_ce`` - Log CE control fileh](j)}(h``edac_mc_log_ce``h]hedac_mc_log_ce}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Log CE control file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hXSGenerate kernel messages describing correctable errors. These errors are reported through the system message log system. CE statistics will be accumulated even when CE logging is disabled. LOAD TIME:: module/kernel parameter: edac_mc_log_ce=[0|1] RUN TIME:: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce h](jq)}(hGenerate kernel messages describing correctable errors. These errors are reported through the system message log system. CE statistics will be accumulated even when CE logging is disabled.h]hGenerate kernel messages describing correctable errors. These errors are reported through the system message log system. CE statistics will be accumulated even when CE logging is disabled.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj0ubjq)}(h LOAD TIME::h]h LOAD TIME:}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj0ubj)}(h-module/kernel parameter: edac_mc_log_ce=[0|1]h]h-module/kernel parameter: edac_mc_log_ce=[0|1]}hjPsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj0ubjq)}(h RUN TIME::h]h RUN TIME:}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj0ubj)}(h:echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ceh]h:echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce}hjlsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj0ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhj!hhhhhNubj)}(hXy``edac_mc_poll_msec`` - Polling period control file The time period, in milliseconds, for polling for error information. Too small a value wastes resources. Too large a value might delay necessary handling of errors and might loose valuable information for locating the error. 1000 milliseconds (once each second) is the current default. Systems which require all the bandwidth they can get, may increase this. LOAD TIME:: module/kernel parameter: edac_mc_poll_msec=[0|1] RUN TIME:: echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec h](jq)}(h3``edac_mc_poll_msec`` - Polling period control fileh](j)}(h``edac_mc_poll_msec``h]hedac_mc_poll_msec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Polling period control file}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hXThe time period, in milliseconds, for polling for error information. Too small a value wastes resources. Too large a value might delay necessary handling of errors and might loose valuable information for locating the error. 1000 milliseconds (once each second) is the current default. Systems which require all the bandwidth they can get, may increase this. LOAD TIME:: module/kernel parameter: edac_mc_poll_msec=[0|1] RUN TIME:: echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec h](jq)}(hXhThe time period, in milliseconds, for polling for error information. Too small a value wastes resources. Too large a value might delay necessary handling of errors and might loose valuable information for locating the error. 1000 milliseconds (once each second) is the current default. Systems which require all the bandwidth they can get, may increase this.h]hXhThe time period, in milliseconds, for polling for error information. Too small a value wastes resources. Too large a value might delay necessary handling of errors and might loose valuable information for locating the error. 1000 milliseconds (once each second) is the current default. Systems which require all the bandwidth they can get, may increase this.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubjq)}(h LOAD TIME::h]h LOAD TIME:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(h0module/kernel parameter: edac_mc_poll_msec=[0|1]h]h0module/kernel parameter: edac_mc_poll_msec=[0|1]}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubjq)}(h RUN TIME::h]h RUN TIME:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(h@echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msech]h@echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhj!hhhhhNubj)}(hX``panic_on_pci_parity`` - Panic on PCI PARITY Error This control file enables or disables panicking when a parity error has been detected. module/kernel parameter:: edac_panic_on_pci_pe=[0|1] Enable:: echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe Disable:: echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe h](jq)}(h3``panic_on_pci_parity`` - Panic on PCI PARITY Errorh](j)}(h``panic_on_pci_parity``h]hpanic_on_pci_parity}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh - Panic on PCI PARITY Error}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjubj)}(hXJThis control file enables or disables panicking when a parity error has been detected. module/kernel parameter:: edac_panic_on_pci_pe=[0|1] Enable:: echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe Disable:: echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe h](jq)}(hVThis control file enables or disables panicking when a parity error has been detected.h]hVThis control file enables or disables panicking when a parity error has been detected.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj ubjq)}(hmodule/kernel parameter::h]hmodule/kernel parameter:}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj ubj)}(hedac_panic_on_pci_pe=[0|1]h]hedac_panic_on_pci_pe=[0|1]}hj< sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj ubjq)}(hEnable::h]hEnable:}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj ubj)}(h@echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_peh]h@echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe}hjX sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj ubjq)}(h Disable::h]hDisable:}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj ubj)}(h@echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_peh]h@echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe}hjt sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhj!hhhhhNubeh}(h]h ]h"]h$]h&]j j4uh1jhhhMhjhhubeh}(h]module-parametersah ]h"]module parametersah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(hEDAC device typeh]hEDAC device type}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhMubjq)}(hiIn the header file, edac_pci.h, there is a series of edac_device structures and APIs for the EDAC_DEVICE.h]hiIn the header file, edac_pci.h, there is a series of edac_device structures and APIs for the EDAC_DEVICE.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj hhubjq)}(hCUser space access to an edac_device is through the sysfs interface.h]hCUser space access to an edac_device is through the sysfs interface.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj hhubjq)}(hYAt the location ``/sys/devices/system/edac`` (sysfs) new edac_device devices will appear.h](hAt the location }(hj hhhNhNubj)}(h``/sys/devices/system/edac``h]h/sys/devices/system/edac}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh- (sysfs) new edac_device devices will appear.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj hhubjq)}(hThere is a three level tree beneath the above ``edac`` directory. For example, the ``test_device_edac`` device (found at the http://bluesmoke.sourceforget.net website) installs itself as::h](h.There is a three level tree beneath the above }(hj hhhNhNubj)}(h``edac``h]hedac}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh directory. For example, the }(hj hhhNhNubj)}(h``test_device_edac``h]htest_device_edac}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh device (found at the }(hj hhhNhNubj )}(h!http://bluesmoke.sourceforget.neth]h!http://bluesmoke.sourceforget.net}(hj!hhhNhNubah}(h]h ]h"]h$]h&]refurij!uh1j hj ubh website) installs itself as:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj hhubj)}(h&/sys/devices/system/edac/test-instanceh]h&/sys/devices/system/edac/test-instance}hj.!sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj hhubjq)}(h[in this directory are various controls, a symlink and one or more ``instance`` directories.h](hBin this directory are various controls, a symlink and one or more }(hjhjs&ubah}(h]h ]h"]h$]h&]uh1jhjp&ubj)}(hhh]jq)}(hPevery 100 cycles, this counter is bumped once, and test-block-bits-1 is set to 0h]hPevery 100 cycles, this counter is bumped once, and test-block-bits-1 is set to 0}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM>hj&ubah}(h]h ]h"]h$]h&]uh1jhjp&ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]jq)}(htest-block-bits-3h]htest-block-bits-3}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM@hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubj)}(hhh]jq)}(hQevery 1000 cycles, this counter is bumped once, and test-block-bits-2 is set to 0h]hQevery 1000 cycles, this counter is bumped once, and test-block-bits-2 is set to 0}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM@hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]colsKuh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj&ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK4uh1jhj&ubj)}(hhh]j)}(hhh](j)}(hhh]jq)}(hreset-countersh]hreset-counters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMFhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(hhh]jq)}(hDwriting ANY thing to this control will reset all the above counters.h]hDwriting ANY thing to this control will reset all the above counters.}(hj+'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMFhj('ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj 'ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]colsKuh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhhhM9hjf$hhubjq)}(h~Use of the ``test_device_edac`` driver should enable any others to create their own unique drivers for their hardware systems.h](h Use of the }(hj^'hhhNhNubj)}(h``test_device_edac``h]htest_device_edac}(hjf'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^'ubh_ driver should enable any others to create their own unique drivers for their hardware systems.}(hj^'hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMKhjf$hhubjq)}(hpThe ``test_device_edac`` sample driver is located at the http://bluesmoke.sourceforge.net project site for EDAC.h](hThe }(hj~'hhhNhNubj)}(h``test_device_edac``h]htest_device_edac}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~'ubh! sample driver is located at the }(hj~'hhhNhNubj )}(h http://bluesmoke.sourceforge.neth]h http://bluesmoke.sourceforge.net}(hj'hhhNhNubah}(h]h ]h"]h$]h&]refurij'uh1j hj~'ubh project site for EDAC.}(hj~'hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMNhjf$hhubeh}(h]blocksah ]h"]blocksah$]h&]uh1j[hj hhhhhM$ubj\)}(hhh](ja)}(h2Usage of EDAC APIs on Nehalem and newer Intel CPUsh]h2Usage of EDAC APIs on Nehalem and newer Intel CPUs}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj'hhhhhMSubjq)}(hOn older Intel architectures, the memory controller was part of the North Bridge chipset. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Sky Lake and newer Intel architectures integrated an enhanced version of the memory controller (MC) inside the CPUs.h]hOn older Intel architectures, the memory controller was part of the North Bridge chipset. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Sky Lake and newer Intel architectures integrated an enhanced version of the memory controller (MC) inside the CPUs.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMUhj'hhubjq)}(hThis chapter will cover the differences of the enhanced memory controllers found on newer Intel CPUs, such as ``i7core_edac``, ``sb_edac`` and ``sbx_edac`` drivers.h](hnThis chapter will cover the differences of the enhanced memory controllers found on newer Intel CPUs, such as }(hj'hhhNhNubj)}(h``i7core_edac``h]h i7core_edac}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubh, }(hj'hhhNhNubj)}(h ``sb_edac``h]hsb_edac}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubh and }(hj'hhhNhNubj)}(h ``sbx_edac``h]hsbx_edac}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubh drivers.}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMZhj'hhubj )}(hThe Xeon E7 processor families use a separate chip for the memory controller, called Intel Scalable Memory Buffer. This section doesn't apply for such families.h]jq)}(hThe Xeon E7 processor families use a separate chip for the memory controller, called Intel Scalable Memory Buffer. This section doesn't apply for such families.h]hThe Xeon E7 processor families use a separate chip for the memory controller, called Intel Scalable Memory Buffer. This section doesn’t apply for such families.}(hj (hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM`hj(ubah}(h]h ]h"]h$]h&]uh1j hj'hhhhhNubhenumerated_list)}(hhh](j)}(hXThere is one Memory Controller per Quick Patch Interconnect (QPI). At the driver, the term "socket" means one QPI. This is associated with a physical CPU socket. Each MC have 3 physical read channels, 3 physical write channels and 3 logic channels. The driver currently sees it as just 3 channels. Each channel can have up to 3 DIMMs. The minimum known unity is DIMMs. There are no information about csrows. As EDAC API maps the minimum unity is csrows, the driver sequentially maps channel/DIMM into different csrows. For example, supposing the following layout:: Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400 Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 The driver will map it as:: csrow0: channel 0, dimm0 csrow1: channel 0, dimm1 csrow2: channel 1, dimm0 csrow3: channel 2, dimm0 exports one DIMM per csrow. Each QPI is exported as a different memory controller. h](jq)}(hThere is one Memory Controller per Quick Patch Interconnect (QPI). At the driver, the term "socket" means one QPI. This is associated with a physical CPU socket.h]hThere is one Memory Controller per Quick Patch Interconnect (QPI). At the driver, the term “socket” means one QPI. This is associated with a physical CPU socket.}(hj=(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMdhj9(ubjq)}(hEach MC have 3 physical read channels, 3 physical write channels and 3 logic channels. The driver currently sees it as just 3 channels. Each channel can have up to 3 DIMMs.h]hEach MC have 3 physical read channels, 3 physical write channels and 3 logic channels. The driver currently sees it as just 3 channels. Each channel can have up to 3 DIMMs.}(hjK(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhhj9(ubjq)}(hThe minimum known unity is DIMMs. There are no information about csrows. As EDAC API maps the minimum unity is csrows, the driver sequentially maps channel/DIMM into different csrows.h]hThe minimum known unity is DIMMs. There are no information about csrows. As EDAC API maps the minimum unity is csrows, the driver sequentially maps channel/DIMM into different csrows.}(hjY(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMlhj9(ubjq)}(h-For example, supposing the following layout::h]h,For example, supposing the following layout:}(hjg(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMphj9(ubj)}(hXCh0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400 Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400h]hXCh0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400 Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400}hju(sbah}(h]h ]h"]h$]h&]hhuh1jhhhMrhj9(ubjq)}(hThe driver will map it as::h]hThe driver will map it as:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMzhj9(ubj)}(hccsrow0: channel 0, dimm0 csrow1: channel 0, dimm1 csrow2: channel 1, dimm0 csrow3: channel 2, dimm0h]hccsrow0: channel 0, dimm0 csrow1: channel 0, dimm1 csrow2: channel 1, dimm0 csrow3: channel 2, dimm0}hj(sbah}(h]h ]h"]h$]h&]hhuh1jhhhM|hj9(ubjq)}(hexports one DIMM per csrow.h]hexports one DIMM per csrow.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj9(ubjq)}(h6Each QPI is exported as a different memory controller.h]h6Each QPI is exported as a different memory controller.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj9(ubeh}(h]h ]h"]h$]h&]uh1jhj6(hhhhhNubj)}(hX5 The MC has the ability to inject errors to test drivers. The drivers implement this functionality via some error injection nodes: For injecting a memory error, there are some sysfs nodes, under ``/sys/devices/system/edac/mc/mc?/``: - ``inject_addrmatch/*``: Controls the error injection mask register. It is possible to specify several characteristics of the address to match an error code:: dimm = the affected dimm. Numbers are relative to a channel; rank = the memory rank; channel = the channel that will generate an error; bank = the affected bank; page = the page address; column (or col) = the address column. each of the above values can be set to "any" to match any valid value. At driver init, all values are set to any. For example, to generate an error at rank 1 of dimm 2, for any channel, any bank, any page, any column:: echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank To return to the default behaviour of matching any, you can do:: echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank - ``inject_eccmask``: specifies what bits will have troubles, - ``inject_section``: specifies what ECC cache section will get the error:: 3 for both 2 for the highest 1 for the lowest - ``inject_type``: specifies the type of error, being a combination of the following bits:: bit 0 - repeat bit 1 - ecc bit 2 - parity - ``inject_enable``: starts the error generation when something different than 0 is written. All inject vars can be read. root permission is needed for write. Datasheet states that the error will only be generated after a write on an address that matches inject_addrmatch. It seems, however, that reading will also produce an error. For example, the following code will generate an error for any write access at socket 0, on any DIMM/address on channel 2:: echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel echo 2 >/sys/devices/system/edac/mc/mc0/inject_type echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask echo 3 >/sys/devices/system/edac/mc/mc0/inject_section echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null For socket 1, it is needed to replace "mc0" by "mc1" at the above commands. The generated error message will look like:: EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error)) h](jq)}(hThe MC has the ability to inject errors to test drivers. The drivers implement this functionality via some error injection nodes:h]hThe MC has the ability to inject errors to test drivers. The drivers implement this functionality via some error injection nodes:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj(ubjq)}(heFor injecting a memory error, there are some sysfs nodes, under ``/sys/devices/system/edac/mc/mc?/``:h](h@For injecting a memory error, there are some sysfs nodes, under }(hj(hhhNhNubj)}(h$``/sys/devices/system/edac/mc/mc?/``h]h /sys/devices/system/edac/mc/mc?/}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubh:}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj(ubj)}(hhh](j)}(hX``inject_addrmatch/*``: Controls the error injection mask register. It is possible to specify several characteristics of the address to match an error code:: dimm = the affected dimm. Numbers are relative to a channel; rank = the memory rank; channel = the channel that will generate an error; bank = the affected bank; page = the page address; column (or col) = the address column. each of the above values can be set to "any" to match any valid value. At driver init, all values are set to any. For example, to generate an error at rank 1 of dimm 2, for any channel, any bank, any page, any column:: echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank To return to the default behaviour of matching any, you can do:: echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank h]j)}(hhh]j)}(hX``inject_addrmatch/*``: Controls the error injection mask register. It is possible to specify several characteristics of the address to match an error code:: dimm = the affected dimm. Numbers are relative to a channel; rank = the memory rank; channel = the channel that will generate an error; bank = the affected bank; page = the page address; column (or col) = the address column. each of the above values can be set to "any" to match any valid value. At driver init, all values are set to any. For example, to generate an error at rank 1 of dimm 2, for any channel, any bank, any page, any column:: echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank To return to the default behaviour of matching any, you can do:: echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank h](j)}(h``inject_addrmatch/*``:h](j)}(h``inject_addrmatch/*``h]hinject_addrmatch/*}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh:}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj(ubj)}(hhh](jq)}(hControls the error injection mask register. It is possible to specify several characteristics of the address to match an error code::h]hControls the error injection mask register. It is possible to specify several characteristics of the address to match an error code:}(hj )hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj)ubj)}(hdimm = the affected dimm. Numbers are relative to a channel; rank = the memory rank; channel = the channel that will generate an error; bank = the affected bank; page = the page address; column (or col) = the address column.h]hdimm = the affected dimm. Numbers are relative to a channel; rank = the memory rank; channel = the channel that will generate an error; bank = the affected bank; page = the page address; column (or col) = the address column.}hj.)sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj)ubjq)}(hFeach of the above values can be set to "any" to match any valid value.h]hJeach of the above values can be set to “any” to match any valid value.}(hj<)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj)ubjq)}(h*At driver init, all values are set to any.h]h*At driver init, all values are set to any.}(hjJ)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj)ubjq)}(hhFor example, to generate an error at rank 1 of dimm 2, for any channel, any bank, any page, any column::h]hgFor example, to generate an error at rank 1 of dimm 2, for any channel, any bank, any page, any column:}(hjX)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj)ubj)}(hX^ echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank To return to the default behaviour of matching any, you can do:: echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rankh]hX^ echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank To return to the default behaviour of matching any, you can do:: echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank}hjf)sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj)ubeh}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hA``inject_eccmask``: specifies what bits will have troubles, h]j)}(hhh]j)}(h<``inject_eccmask``: specifies what bits will have troubles, h](j)}(h``inject_eccmask``:h](j)}(h``inject_eccmask``h]hinject_eccmask}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh:}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj)ubj)}(hhh]jq)}(h'specifies what bits will have troubles,h]h'specifies what bits will have troubles,}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(h``inject_section``: specifies what ECC cache section will get the error:: 3 for both 2 for the highest 1 for the lowest h]j)}(hhh]j)}(h``inject_section``: specifies what ECC cache section will get the error:: 3 for both 2 for the highest 1 for the lowest h](j)}(h``inject_section``:h](j)}(h``inject_section``h]hinject_section}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh:}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj)ubj)}(hhh](jq)}(h5specifies what ECC cache section will get the error::h]h4specifies what ECC cache section will get the error:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj*ubj)}(h-3 for both 2 for the highest 1 for the lowesth]h-3 for both 2 for the highest 1 for the lowest}hj*sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj*ubeh}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(h``inject_type``: specifies the type of error, being a combination of the following bits:: bit 0 - repeat bit 1 - ecc bit 2 - parity h]j)}(hhh]j)}(h``inject_type``: specifies the type of error, being a combination of the following bits:: bit 0 - repeat bit 1 - ecc bit 2 - parity h](j)}(h``inject_type``:h](j)}(h``inject_type``h]h inject_type}(hjI*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE*ubh:}(hjE*hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjA*ubj)}(hhh](jq)}(hHspecifies the type of error, being a combination of the following bits::h]hGspecifies the type of error, being a combination of the following bits:}(hjd*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhja*ubj)}(h)bit 0 - repeat bit 1 - ecc bit 2 - parityh]h)bit 0 - repeat bit 1 - ecc bit 2 - parity}hjr*sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhja*ubeh}(h]h ]h"]h$]h&]uh1jhjA*ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj>*ubah}(h]h ]h"]h$]h&]uh1jhj:*ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(h]``inject_enable``: starts the error generation when something different than 0 is written. h]j)}(hhh]j)}(h[``inject_enable``: starts the error generation when something different than 0 is written. h](j)}(h``inject_enable``:h](j)}(h``inject_enable``h]h inject_enable}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh:}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj*ubj)}(hhh]jq)}(hGstarts the error generation when something different than 0 is written.h]hGstarts the error generation when something different than 0 is written.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]j j4uh1jhhhMhj(ubjq)}(hAAll inject vars can be read. root permission is needed for write.h]hAAll inject vars can be read. root permission is needed for write.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj(ubjq)}(hDatasheet states that the error will only be generated after a write on an address that matches inject_addrmatch. It seems, however, that reading will also produce an error.h]hDatasheet states that the error will only be generated after a write on an address that matches inject_addrmatch. It seems, however, that reading will also produce an error.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj(ubjq)}(h{For example, the following code will generate an error for any write access at socket 0, on any DIMM/address on channel 2::h]hzFor example, the following code will generate an error for any write access at socket 0, on any DIMM/address on channel 2:}(hj +hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj(ubj)}(hXYecho 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel echo 2 >/sys/devices/system/edac/mc/mc0/inject_type echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask echo 3 >/sys/devices/system/edac/mc/mc0/inject_section echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/nullh]hXYecho 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel echo 2 >/sys/devices/system/edac/mc/mc0/inject_type echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask echo 3 >/sys/devices/system/edac/mc/mc0/inject_section echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null}hj+sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj(ubjq)}(hKFor socket 1, it is needed to replace "mc0" by "mc1" at the above commands.h]hSFor socket 1, it is needed to replace “mc0” by “mc1” at the above commands.}(hj&+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj(ubjq)}(h,The generated error message will look like::h]h+The generated error message will look like:}(hj4+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj(ubj)}(hEDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))h]hEDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))}hjB+sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj(ubeh}(h]h ]h"]h$]h&]uh1jhj6(hhhhhNubj)}(hXpCorrected Error memory register counters Those newer MCs have some registers to count memory errors. The driver uses those registers to report Corrected Errors on devices with Registered DIMMs. However, those counters don't work with Unregistered DIMM. As the chipset offers some counters that also work with UDIMMs (but with a worse level of granularity than the default ones), the driver exposes those registers for UDIMM memories. They can be read by looking at the contents of ``all_channel_counts/``:: $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0 0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1 0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2 0 What happens here is that errors on different csrows, but at the same dimm number will increment the same counter. So, in this memory mapping:: csrow0: channel 0, dimm0 csrow1: channel 0, dimm1 csrow2: channel 1, dimm0 csrow3: channel 2, dimm0 The hardware will increment udimm0 for an error at the first dimm at either csrow0, csrow2 or csrow3; The hardware will increment udimm1 for an error at the second dimm at either csrow0, csrow2 or csrow3; The hardware will increment udimm2 for an error at the third dimm at either csrow0, csrow2 or csrow3; h](jq)}(h(Corrected Error memory register countersh]h(Corrected Error memory register counters}(hjZ+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubjq)}(hThose newer MCs have some registers to count memory errors. The driver uses those registers to report Corrected Errors on devices with Registered DIMMs.h]hThose newer MCs have some registers to count memory errors. The driver uses those registers to report Corrected Errors on devices with Registered DIMMs.}(hjh+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubjq)}(hHowever, those counters don't work with Unregistered DIMM. As the chipset offers some counters that also work with UDIMMs (but with a worse level of granularity than the default ones), the driver exposes those registers for UDIMM memories.h]hHowever, those counters don’t work with Unregistered DIMM. As the chipset offers some counters that also work with UDIMMs (but with a worse level of granularity than the default ones), the driver exposes those registers for UDIMM memories.}(hjv+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubjq)}(hHThey can be read by looking at the contents of ``all_channel_counts/``::h](h/They can be read by looking at the contents of }(hj+hhhNhNubj)}(h``all_channel_counts/``h]hall_channel_counts/}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubj)}(hX$ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0 0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1 0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2 0h]hX$ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0 0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1 0 /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2 0}hj+sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjV+ubjq)}(hWhat happens here is that errors on different csrows, but at the same dimm number will increment the same counter. So, in this memory mapping::h]hWhat happens here is that errors on different csrows, but at the same dimm number will increment the same counter. So, in this memory mapping:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubj)}(hccsrow0: channel 0, dimm0 csrow1: channel 0, dimm1 csrow2: channel 1, dimm0 csrow3: channel 2, dimm0h]hccsrow0: channel 0, dimm0 csrow1: channel 0, dimm1 csrow2: channel 1, dimm0 csrow3: channel 2, dimm0}hj+sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjV+ubjq)}(hfThe hardware will increment udimm0 for an error at the first dimm at either csrow0, csrow2 or csrow3;h]hfThe hardware will increment udimm0 for an error at the first dimm at either csrow0, csrow2 or csrow3;}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubjq)}(hgThe hardware will increment udimm1 for an error at the second dimm at either csrow0, csrow2 or csrow3;h]hgThe hardware will increment udimm1 for an error at the second dimm at either csrow0, csrow2 or csrow3;}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubjq)}(hfThe hardware will increment udimm2 for an error at the third dimm at either csrow0, csrow2 or csrow3;h]hfThe hardware will increment udimm2 for an error at the third dimm at either csrow0, csrow2 or csrow3;}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjV+ubeh}(h]h ]h"]h$]h&]uh1jhj6(hhhhhNubj)}(hX Standard error counters The standard error counters are generated when an mcelog error is received by the driver. Since, with UDIMM, this is counted by software, it is possible that some errors could be lost. With RDIMM's, they display the contents of the registers h](jq)}(hStandard error countersh]hStandard error counters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj+ubjq)}(hThe standard error counters are generated when an mcelog error is received by the driver. Since, with UDIMM, this is counted by software, it is possible that some errors could be lost. With RDIMM's, they display the contents of the registersh]hThe standard error counters are generated when an mcelog error is received by the driver. Since, with UDIMM, this is counted by software, it is possible that some errors could be lost. With RDIMM’s, they display the contents of the registers}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj+ubeh}(h]h ]h"]h$]h&]uh1jhj6(hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1j4(hj'hhhhhMdubeh}(h]2usage-of-edac-apis-on-nehalem-and-newer-intel-cpusah ]h"]2usage of edac apis on nehalem and newer intel cpusah$]h&]uh1j[hj hhhhhMSubj\)}(hhh](ja)}(h*Reference documents used on ``amd64_edac``h](hReference documents used on }(hj:,hhhNhNubj)}(h``amd64_edac``h]h amd64_edac}(hjB,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:,ubeh}(h]h ]h"]h$]h&]uh1j`hj7,hhhhhMubjq)}(hy``amd64_edac`` module is based on the following documents (available from http://support.amd.com/en-us/search/tech-docs):h](j)}(h``amd64_edac``h]h amd64_edac}(hjZ,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjV,ubh< module is based on the following documents (available from }(hjV,hhhNhNubj )}(h-http://support.amd.com/en-us/search/tech-docsh]h-http://support.amd.com/en-us/search/tech-docs}(hjl,hhhNhNubah}(h]h ]h"]h$]h&]refurijn,uh1j hjV,ubh):}(hjV,hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhMhj7,hhubj5()}(hhh](j)}(h:Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors :AMD publication #: 26094 :Revision: 3.26 :Link: http://support.amd.com/TechDocs/26094.PDF h]h field_list)}(hhh](hfield)}(hhh](h field_name)}(hTitleh]hTitle}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj,hhhKubh field_body)}(hNBIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processorsh]jq)}(hNBIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processorsh]hPBIOS and Kernel Developer’s Guide for AMD Athlon 64 and AMD Opteron Processors}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj,ubah}(h]h ]h"]h$]h&]uh1j,hj,ubeh}(h]h ]h"]h$]h&]uh1j,hhhMhj,ubj,)}(hhh](j,)}(hAMD publication #h]hAMD publication #}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj,hhhKubj,)}(h26094h]jq)}(hj,h]h26094}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhj,ubah}(h]h ]h"]h$]h&]uh1j,hj,ubeh}(h]h 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]h"]h$]h&]uh1j,hhhM&hj1ubj,)}(hhh](j,)}(hAMD publication #h]hAMD publication #}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj1hhhKubj,)}(h48751h]jq)}(hj1h]h48751}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM(hj1ubah}(h]h ]h"]h$]h&]uh1j,hj1ubeh}(h]h ]h"]h$]h&]uh1j,hhhM(hj1ubj,)}(hhh](j,)}(hRevisionh]hRevision}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj1hhhKubj,)}(h3.03h]jq)}(hj1h]h3.03}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM)hj1ubah}(h]h ]h"]h$]h&]uh1j,hj1ubeh}(h]h ]h"]h$]h&]uh1j,hhhM)hj1ubj,)}(hhh](j,)}(h Issue Dateh]h Issue Date}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj 2hhhKubj,)}(h2/23/2015 (latest release)h]jq)}(hj 2h]h2/23/2015 (latest release)}(hj"2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM*hj2ubah}(h]h ]h"]h$]h&]uh1j,hj 2ubeh}(h]h ]h"]h$]h&]uh1j,hhhM*hj1ubj,)}(hhh](j,)}(hLinkh]hLink}(hj>2hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj;2hhhKubj,)}(h3http://support.amd.com/TechDocs/48751_16h_bkdg.pdf h]jq)}(h2http://support.amd.com/TechDocs/48751_16h_bkdg.pdfh]j )}(hjR2h]h2http://support.amd.com/TechDocs/48751_16h_bkdg.pdf}(hjT2hhhNhNubah}(h]h ]h"]h$]h&]refurijR2uh1j hjP2ubah}(h]h ]h"]h$]h&]uh1jphhhM+hjL2ubah}(h]h ]h"]h$]h&]uh1j,hj;2ubeh}(h]h ]h"]h$]h&]uh1j,hhhM+hj1ubeh}(h]h ]h"]h$]h&]uh1j,hj{1ubah}(h]h ]h"]h$]h&]uh1jhj,hhhNhNubeh}(h]h ]h"]h$]h&]j*,j+,j,,hj-,.uh1j4(hj7,hhhhhMubj\)}(hhh](ja)}(hCreditsh]hCredits}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj2hhhhhM.ubj)}(hhh](j)}(hYWritten by Doug Thompson - 7 Dec 2005 - 17 Jul 2007 Updated h](jq)}(h4Written by Doug Thompson h](hWritten by Doug Thompson <}(hj2hhhNhNubj )}(hdougthompson@xmission.comh]hdougthompson@xmission.com}(hj2hhhNhNubah}(h]h ]h"]h$]h&]refuri mailto:dougthompson@xmission.comuh1j hj2ubh>}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhM0hj2ubj)}(hhh](j)}(h 7 Dec 2005h]jq)}(hj2h]h 7 Dec 2005}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM2hj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(h17 Jul 2007 Updated h]jq)}(h17 Jul 2007 Updatedh]h17 Jul 2007 Updated}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM3hj2ubah}(h]h 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