sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget%/translations/zh_CN/accel/qaic/aic100modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget%/translations/zh_TW/accel/qaic/aic100modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget%/translations/it_IT/accel/qaic/aic100modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget%/translations/ja_JP/accel/qaic/aic100modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget%/translations/ko_KR/accel/qaic/aic100modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget%/translations/sp_SP/accel/qaic/aic100modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h%SPDX-License-Identifier: GPL-2.0-onlyh]h%SPDX-License-Identifier: GPL-2.0-only}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh?/var/lib/git/docbuild/linux/Documentation/accel/qaic/aic100.rsthKubhsection)}(hhh](htitle)}(hQualcomm Cloud AI 100 (AIC100)h]hQualcomm Cloud AI 100 (AIC100)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThe Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of Snapdragon Ride) are PCIe adapter cards which contain a dedicated SoC ASIC for the purpose of efficiently running Artificial Intelligence (AI) Deep Learning inference workloads. They are AI accelerators.h]hXThe Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of Snapdragon Ride) are PCIe adapter cards which contain a dedicated SoC ASIC for the purpose of efficiently running Artificial Intelligence (AI) Deep Learning inference workloads. They are AI accelerators.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hThe PCIe interface of AIC100 is capable of PCIe Gen4 speeds over eight lanes (x8). An individual SoC on a card can have up to 16 NSPs for running workloads. Each SoC has an A53 management CPU. On card, there can be up to 32 GB of DDR.h]hThe PCIe interface of AIC100 is capable of PCIe Gen4 speeds over eight lanes (x8). An individual SoC on a card can have up to 16 NSPs for running workloads. Each SoC has an A53 management CPU. On card, there can be up to 32 GB of DDR.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hMultiple AIC100 cards can be hosted in a single system to scale overall performance. AIC100 cards are multi-user capable and able to execute workloads from multiple users in a concurrent manner.h]hMultiple AIC100 cards can be hosted in a single system to scale overall performance. AIC100 cards are multi-user capable and able to execute workloads from multiple users in a concurrent manner.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]overviewah ]h"]h$]overviewah&]uh1hhhhhhhhK referencedKubh)}(hhh](h)}(hHardware Descriptionh]hHardware Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hbAn AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc peripherals (PMICs, etc).h]hbAn AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc peripherals (PMICs, etc).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hAn AIC100 card can either be a PCIe HHHL form factor (a traditional PCIe card), or a Dual M.2 card. Both use PCIe to connect to the host system.h]hAn AIC100 card can either be a PCIe HHHL form factor (a traditional PCIe card), or a Dual M.2 card. Both use PCIe to connect to the host system.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hAs a PCIe endpoint/adapter, AIC100 uses the standard VendorID(VID)/ DeviceID(DID) combination to uniquely identify itself to the host. AIC100 uses the standard Qualcomm VID (0x17cb). All AIC100 SKUs use the same AIC100 DID (0xa100).h]hAs a PCIe endpoint/adapter, AIC100 uses the standard VendorID(VID)/ DeviceID(DID) combination to uniquely identify itself to the host. AIC100 uses the standard Qualcomm VID (0x17cb). All AIC100 SKUs use the same AIC100 DID (0xa100).}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjhhubh)}(h5AIC100 does not implement FLR (function level reset).h]h5AIC100 does not implement FLR (function level reset).}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjhhubh)}(hAIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to operate (1 for MHI, 16 for the DMA Bridge). Falling back to 1 MSI is possible in scenarios where reserving 32 MSIs isn't feasible.h]hAIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to operate (1 for MHI, 16 for the DMA Bridge). Falling back to 1 MSI is possible in scenarios where reserving 32 MSIs isn’t feasible.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjhhubh)}(hyAs a PCIe device, AIC100 utilizes BARs to provide host interfaces to the device hardware. AIC100 provides 3, 64-bit BARs.h]hyAs a PCIe device, AIC100 utilizes BARs to provide host interfaces to the device hardware. AIC100 provides 3, 64-bit BARs.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjhhubh bullet_list)}(hhh](h list_item)}(hHThe first BAR is 4K in size, and exposes the MHI interface to the host. h]h)}(hGThe first BAR is 4K in size, and exposes the MHI interface to the host.h]hGThe first BAR is 4K in size, and exposes the MHI interface to the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hj{ubah}(h]h ]h"]h$]h&]uh1jyhjvhhhhhNubjz)}(hPThe second BAR is 2M in size, and exposes the DMA Bridge interface to the host. h]h)}(hOThe second BAR is 2M in size, and exposes the DMA Bridge interface to the host.h]hOThe second BAR is 2M in size, and exposes the DMA Bridge interface to the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jyhjvhhhhhNubjz)}(hThe third BAR is variable in size based on an individual AIC100's configuration, but defaults to 64K. This BAR currently has no purpose. h]h)}(hThe third BAR is variable in size based on an individual AIC100's configuration, but defaults to 64K. This BAR currently has no purpose.h]hThe third BAR is variable in size based on an individual AIC100’s configuration, but defaults to 64K. This BAR currently has no purpose.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1jyhjvhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1jthhhK.hjhhubh)}(hGFrom the host perspective, AIC100 has several key hardware components -h]hGFrom the host perspective, AIC100 has several key hardware components -}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjhhubju)}(hhh](jz)}(hMHI (Modem Host Interface)h]h)}(hjh]hMHI (Modem Host Interface)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubah}(h]h ]h"]h$]h&]uh1jyhjhhhhhNubjz)}(hQSM (QAIC Service Manager)h]h)}(hjh]hQSM (QAIC Service Manager)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jyhjhhhhhNubjz)}(hNSPs (Neural Signal Processor)h]h)}(hj h]hNSPs (Neural Signal Processor)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hj ubah}(h]h ]h"]h$]h&]uh1jyhjhhhhhNubjz)}(h DMA Bridgeh]h)}(hj#h]h DMA Bridge}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj!ubah}(h]h ]h"]h$]h&]uh1jyhjhhhhhNubjz)}(hDDR h]h)}(hDDRh]hDDR}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAIC100 uses a flashless boot flow, derived from Qualcomm MSMs.h]h>AIC100 uses a flashless boot flow, derived from Qualcomm MSMs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWhen AIC100 is first powered on, it begins executing PBL (Primary Bootloader) from ROM. PBL enumerates the PCIe link, and initializes the BHI (Boot Host Interface) component of MHI.h]hWhen AIC100 is first powered on, it begins executing PBL (Primary Bootloader) from ROM. PBL enumerates the PCIe link, and initializes the BHI (Boot Host Interface) component of MHI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hUsing BHI, the host points PBL to the location of the SBL (Secondary Bootloader) image. The PBL pulls the image from the host, validates it, and begins execution of SBL.h]hUsing BHI, the host points PBL to the location of the SBL (Secondary Bootloader) image. The PBL pulls the image from the host, validates it, and begins execution of SBL.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hSBL initializes MHI, and uses MHI to notify the host that the device has entered the SBL stage. SBL performs a number of operations:h]hSBL initializes MHI, and uses MHI to notify the host that the device has entered the SBL stage. SBL performs a number of operations:}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubju)}(hhh](jz)}(hZSBL initializes the majority of hardware (anything PBL left uninitialized), including DDR.h]h)}(hZSBL initializes the majority of hardware (anything PBL left uninitialized), including DDR.h]hZSBL initializes the majority of hardware (anything PBL left uninitialized), including DDR.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj@ubah}(h]h ]h"]h$]h&]uh1jyhj=hhhhhNubjz)}(h%SBL offloads the bootlog to the host.h]h)}(hjZh]h%SBL offloads the bootlog to the host.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjXubah}(h]h ]h"]h$]h&]uh1jyhj=hhhhhNubjz)}(h=SBL synchronizes timestamps with the host for future logging.h]h)}(hjqh]h=SBL synchronizes timestamps with the host for future logging.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjoubah}(h]h ]h"]h$]h&]uh1jyhj=hhhhhNubjz)}(hRSBL uses the Sahara protocol to obtain the runtime firmware images from the host. h]h)}(hQSBL uses the Sahara protocol to obtain the runtime firmware images from the host.h]hQSBL uses the Sahara protocol to obtain the runtime firmware images from the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jyhj=hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jthhhKhjhhubh)}(hrOnce SBL has obtained and validated the runtime firmware, it brings the NSPs out of reset, and jumps into the QSM.h]hrOnce SBL has obtained and validated the runtime firmware, it brings the NSPs out of reset, and jumps into the QSM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThe QSM uses MHI to notify the host that the device has entered the QSM stage (AMSS in MHI terms). At this point, the AIC100 device is fully functional, and ready to process workloads.h]hThe QSM uses MHI to notify the host that the device has entered the QSM stage (AMSS in MHI terms). At this point, the AIC100 device is fully functional, and ready to process workloads.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] boot-flowah ]h"] boot flowah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hUserspace componentsh]hUserspace components}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hCompilerh]hCompiler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hAn open compiler for AIC100 based on upstream LLVM can be found at: https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100-cch](hDAn open compiler for AIC100 based on upstream LLVM can be found at: }(hjhhhNhNubh reference)}(hAhttps://github.com/quic/software-kit-for-qualcomm-cloud-ai-100-cch]hAhttps://github.com/quic/software-kit-for-qualcomm-cloud-ai-100-cc}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]compilerah ]h"]compilerah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hUsermode Driver (UMD)h]hUsermode Driver (UMD)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hAn open UMD that interfaces with the qaic kernel driver can be found at: https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100h](hIAn open UMD that interfaces with the qaic kernel driver can be found at: }(hj"hhhNhNubj)}(h>https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100h]h>https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100}(hj*hhhNhNubah}(h]h ]h"]h$]h&]refurij,uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]usermode-driver-umdah ]h"]usermode driver (umd)ah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h Sahara loaderh]h Sahara loader}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhKubh)}(hpAn open implementation of the Sahara protocol called kickstart can be found at: https://github.com/andersson/qdlh](hPAn open implementation of the Sahara protocol called kickstart can be found at: }(hjXhhhNhNubj)}(h https://github.com/andersson/qdlh]h https://github.com/andersson/qdl}(hj`hhhNhNubah}(h]h ]h"]h$]h&]refurijbuh1jhjXubeh}(h]h ]h"]h$]h&]uh1hhhhKhjGhhubeh}(h] sahara-loaderah ]h"] sahara loaderah$]h&]uh1hhjhhhhhKubeh}(h]userspace-componentsah ]h"]userspace componentsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h MHI Channelsh]h MHI Channels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hwAIC100 defines a number of MHI channels for different purposes. This is a list of the defined channels, and their uses.h]hwAIC100 defines a number of MHI channels for different purposes. This is a list of the defined channels, and their uses.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK(uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(h Channel nameh]h Channel name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hIDsh]hIDs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hEEsh]hEEs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPurposeh]hPurpose}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj)ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(h QAIC_LOOPBACKh]h QAIC_LOOPBACK}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(h0 & 1h]h0 & 1}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(hAMSSh]hAMSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(hEAny data sent to the device on this channel is sent back to the host.h]hEAny data sent to the device on this channel is sent back to the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_SAHARAh]h QAIC_SAHARA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h2 & 3h]h2 & 3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSBLh]hSBL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h9Used by SBL to obtain the runtime firmware from the host.h]h9Used by SBL to obtain the runtime firmware from the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_DIAGh]h QAIC_DIAG}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h4 & 5h]h4 & 5}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAMSSh]hAMSS}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h3Used to communicate with QSM via the DIAG protocol.h]h3Used to communicate with QSM via the DIAG protocol.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(hQAIC_SSRh]hQAIC_SSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h6 & 7h]h6 & 7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAMSSh]hAMSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSUsed to notify the host of subsystem restart events, and to offload SSR crashdumps.h]hSUsed to notify the host of subsystem restart events, and to offload SSR crashdumps.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_QDSSh]h QAIC_QDSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h8 & 9h]h8 & 9}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAMSSh]hAMSS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&Used for the Qualcomm Debug Subsystem.h]h&Used for the Qualcomm Debug Subsystem.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_CONTROLh]h QAIC_CONTROL}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1jhjJubj)}(hhh]h)}(h10 & 11h]h10 & 11}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1jhjJubj)}(hhh]h)}(hAMSSh]hAMSS}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj{ubah}(h]h ]h"]h$]h&]uh1jhjJubj)}(hhh]h)}(h|Used for the Neural Network Control (NNC) protocol. This is the primary channel between host and QSM for managing workloads.h]h|Used for the Neural Network Control (NNC) protocol. This is the primary channel between host and QSM for managing workloads.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_LOGGINGh]h QAIC_LOGGING}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h12 & 13h]h12 & 13}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSBLh]hSBL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h0Used by the SBL to send the bootlog to the host.h]h0Used by the SBL to send the bootlog to the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_STATUSh]h QAIC_STATUS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h14 & 15h]h14 & 15}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj. ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hAMSSh]hAMSS}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjE ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hSUsed to notify the host of Reliability, Accessibility, Serviceability (RAS) events.h]hSUsed to notify the host of Reliability, Accessibility, Serviceability (RAS) events.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(hQAIC_TELEMETRYh]hQAIC_TELEMETRY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj| ubah}(h]h ]h"]h$]h&]uh1jhjy ubj)}(hhh]h)}(h16 & 17h]h16 & 17}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjy ubj)}(hhh]h)}(hAMSSh]hAMSS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjy ubj)}(hhh]h)}(h-Used to get/set power/thermal/etc attributes.h]h-Used to get/set power/thermal/etc attributes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjy ubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_DEBUGh]h QAIC_DEBUG}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h18 & 19h]h18 & 19}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hAMSSh]hAMSS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Not used.h]h Not used.}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj& ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h QAIC_TIMESYNCh]h QAIC_TIMESYNC}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjF ubah}(h]h ]h"]h$]h&]uh1jhjC ubj)}(hhh]h)}(h20 & 21h]h20 & 21}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj] ubah}(h]h ]h"]h$]h&]uh1jhjC ubj)}(hhh]h)}(hSBLh]hSBL}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjt ubah}(h]h ]h"]h$]h&]uh1jhjC ubj)}(hhh]h)}(hQUsed to synchronize timestamps in the device side logs with the host time source.h]hQUsed to synchronize timestamps in the device side logs with the host time source.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjC ubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(hQAIC_TIMESYNC _PERIODICh]hQAIC_TIMESYNC _PERIODIC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h22 & 23h]h22 & 23}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hAMSSh]hAMSS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h^Used to periodically synchronize timestamps in the device side logs with the host time source.h]h^Used to periodically synchronize timestamps in the device side logs with the host time source.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(hIPCRh]hIPCR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h24 & 25h]h24 & 25}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj' ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hAMSSh]hAMSS}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj> ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hAF_QIPCRTR clients and servers.h]hAF_QIPCRTR clients and servers.}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjU ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h] mhi-channelsah ]h"] mhi channelsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h DMA Bridgeh]h DMA Bridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXBThe DMA Bridge is one of the main interfaces to the host from the device (the other being MHI). As part of activating a workload to run on NSPs, the QSM assigns that network a DMA Bridge channel. A workload's DMA Bridge channel (DBC for short) is solely for the use of that workload and is not shared with other workloads.h]hXDThe DMA Bridge is one of the main interfaces to the host from the device (the other being MHI). As part of activating a workload to run on NSPs, the QSM assigns that network a DMA Bridge channel. A workload’s DMA Bridge channel (DBC for short) is solely for the use of that workload and is not shared with other workloads.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hEach DBC is a pair of FIFOs that manage data in and out of the workload. One FIFO is the request FIFO. The other FIFO is the response FIFO.h]hEach DBC is a pair of FIFOs that manage data in and out of the workload. One FIFO is the request FIFO. The other FIFO is the response FIFO.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(h*Each DBC contains 4 registers in hardware:h]h*Each DBC contains 4 registers in hardware:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubju)}(hhh](jz)}(h}Request FIFO head pointer (offset 0x0). Read only by the host. Indicates the latest item in the FIFO the device has consumed.h]h)}(h}Request FIFO head pointer (offset 0x0). Read only by the host. Indicates the latest item in the FIFO the device has consumed.h]h}Request FIFO head pointer (offset 0x0). Read only by the host. Indicates the latest item in the FIFO the device has consumed.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jyhj hhhhhNubjz)}(h{Request FIFO tail pointer (offset 0x4). Read/write by the host. Host increments this register to add new items to the FIFO.h]h)}(h{Request FIFO tail pointer (offset 0x4). Read/write by the host. Host increments this register to add new items to the FIFO.h]h{Request FIFO tail pointer (offset 0x4). Read/write by the host. Host increments this register to add new items to the FIFO.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jyhj hhhhhNubjz)}(h}Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates the latest item in the FIFO the host has consumed.h]h)}(h}Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates the latest item in the FIFO the host has consumed.h]h}Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates the latest item in the FIFO the host has consumed.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jyhj hhhhhNubjz)}(h~Response FIFO tail pointer (offset 0xc). Read only by the host. Device increments this register to add new items to the FIFO. h]h)}(h}Response FIFO tail pointer (offset 0xc). Read only by the host. Device increments this register to add new items to the FIFO.h]h}Response FIFO tail pointer (offset 0xc). Read only by the host. Device increments this register to add new items to the FIFO.}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ ubah}(h]h ]h"]h$]h&]uh1jyhj hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jthhhKhj hhubh)}(hThe values in each register are indexes in the FIFO. To get the location of the FIFO element pointed to by the register: FIFO base address + register * element size.h]hThe values in each register are indexes in the FIFO. To get the location of the FIFO element pointed to by the register: FIFO base address + register * element size.}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hdDBC registers are exposed to the host via the second BAR. Each DBC consumes 4KB of space in the BAR.h]hdDBC registers are exposed to the host via the second BAR. Each DBC consumes 4KB of space in the BAR.}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubh)}(hXThe actual FIFOs are backed by host memory. When sending a request to the QSM to activate a network, the host must donate memory to be used for the FIFOs. Due to internal mapping limitations of the device, a single contiguous chunk of memory must be provided per DBC, which hosts both FIFOs. The request FIFO will consume the beginning of the memory chunk, and the response FIFO will consume the end of the memory chunk.h]hXThe actual FIFOs are backed by host memory. When sending a request to the QSM to activate a network, the host must donate memory to be used for the FIFOs. Due to internal mapping limitations of the device, a single contiguous chunk of memory must be provided per DBC, which hosts both FIFOs. The request FIFO will consume the beginning of the memory chunk, and the response FIFO will consume the end of the memory chunk.}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubeh}(h]id2ah ]h"]h$]j ah&]uh1hhj hhhhhKjKubh)}(hhh](h)}(h Request FIFOh]h Request FIFO}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs hhhhhMubh)}(h3A request FIFO element has the following structure:h]h3A request FIFO element has the following structure:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjs hhubh literal_block)}(hXstruct request_elem { u16 req_id; u8 seq_id; u8 pcie_dma_cmd; u32 reserved; u64 pcie_dma_source_addr; u64 pcie_dma_dest_addr; u32 pcie_dma_len; u32 reserved; u64 doorbell_addr; u8 doorbell_attr; u8 reserved; u16 reserved; u32 doorbell_data; u32 sem_cmd0; u32 sem_cmd1; u32 sem_cmd2; u32 sem_cmd3; };h]hXstruct request_elem { u16 req_id; u8 seq_id; u8 pcie_dma_cmd; u32 reserved; u64 pcie_dma_source_addr; u64 pcie_dma_dest_addr; u32 pcie_dma_len; u32 reserved; u64 doorbell_addr; u8 doorbell_attr; u8 reserved; u16 reserved; u32 doorbell_data; u32 sem_cmd0; u32 sem_cmd1; u32 sem_cmd2; u32 sem_cmd3; };}hj sbah}(h]h ]h"]h$]h&]hhforcelanguagechighlight_args}uh1j hhhMhjs hhubh)}(hRequest field descriptions:h]hRequest field descriptions:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjs hhubhdefinition_list)}(hhh](hdefinition_list_item)}(hzreq_id request ID. A request FIFO element and a response FIFO element with the same request ID refer to the same command. h](hterm)}(hreq_idh]hreq_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhM2hj ubh definition)}(hhh]h)}(hrrequest ID. A request FIFO element and a response FIFO element with the same request ID refer to the same command.h]hrrequest ID. A request FIFO element and a response FIFO element with the same request ID refer to the same command.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhM2hj ubj )}(h@seq_id sequence ID within a request. Ignored by the DMA Bridge. h](j )}(hseq_idh]hseq_id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhM5hj ubj )}(hhh]h)}(h8sequence ID within a request. Ignored by the DMA Bridge.h]h8sequence ID within a request. Ignored by the DMA Bridge.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhM5hj hhubj )}(hXzpcie_dma_cmd describes the DMA element of this request. * Bit(7) is the force msi flag, which overrides the DMA Bridge MSI logic and generates a MSI when this request is complete, and QSM configures the DMA Bridge to look at this bit. * Bits(6:5) are reserved. * Bit(4) is the completion code flag, and indicates that the DMA Bridge shall generate a response FIFO element when this request is complete. * Bit(3) indicates if this request is a linked list transfer(0) or a bulk transfer(1). * Bit(2) is reserved. * Bits(1:0) indicate the type of transfer. No transfer(0), to device(1), from device(2). Value 3 is illegal. h](j )}(h pcie_dma_cmdh]h pcie_dma_cmd}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMEhj ubj )}(hhh](h)}(h*describes the DMA element of this request.h]h*describes the DMA element of this request.}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj0 ubju)}(hhh](jz)}(hBit(7) is the force msi flag, which overrides the DMA Bridge MSI logic and generates a MSI when this request is complete, and QSM configures the DMA Bridge to look at this bit.h]h)}(hBit(7) is the force msi flag, which overrides the DMA Bridge MSI logic and generates a MSI when this request is complete, and QSM configures the DMA Bridge to look at this bit.h]hBit(7) is the force msi flag, which overrides the DMA Bridge MSI logic and generates a MSI when this request is complete, and QSM configures the DMA Bridge to look at this bit.}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjD ubah}(h]h ]h"]h$]h&]uh1jyhjA ubjz)}(hBits(6:5) are reserved.h]h)}(hj^ h]hBits(6:5) are reserved.}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hj\ ubah}(h]h ]h"]h$]h&]uh1jyhjA ubjz)}(hBit(4) is the completion code flag, and indicates that the DMA Bridge shall generate a response FIFO element when this request is complete.h]h)}(hBit(4) is the completion code flag, and indicates that the DMA Bridge shall generate a response FIFO element when this request is complete.h]hBit(4) is the completion code flag, and indicates that the DMA Bridge shall generate a response FIFO element when this request is complete.}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjs ubah}(h]h ]h"]h$]h&]uh1jyhjA ubjz)}(hTBit(3) indicates if this request is a linked list transfer(0) or a bulk transfer(1).h]h)}(hTBit(3) indicates if this request is a linked list transfer(0) or a bulk transfer(1).h]hTBit(3) indicates if this request is a linked list transfer(0) or a bulk transfer(1).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj ubah}(h]h ]h"]h$]h&]uh1jyhjA ubjz)}(hBit(2) is reserved.h]h)}(hj h]hBit(2) is reserved.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChj ubah}(h]h ]h"]h$]h&]uh1jyhjA ubjz)}(hkBits(1:0) indicate the type of transfer. No transfer(0), to device(1), from device(2). Value 3 is illegal. h]h)}(hjBits(1:0) indicate the type of transfer. No transfer(0), to device(1), from device(2). Value 3 is illegal.h]hjBits(1:0) indicate the type of transfer. No transfer(0), to device(1), from device(2). Value 3 is illegal.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhj ubah}(h]h ]h"]h$]h&]uh1jyhjA ubeh}(h]h ]h"]h$]h&]jjuh1jthhhM:hj0 ubeh}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMEhj hhubj )}(h\pcie_dma_source_addr source address for a bulk transfer, or the address of the linked list. h](j )}(hpcie_dma_source_addrh]hpcie_dma_source_addr}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMHhj ubj )}(hhh]h)}(hFsource address for a bulk transfer, or the address of the linked list.h]hFsource address for a bulk transfer, or the address of the linked list.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMHhj hhubj )}(haddress of the doorbell to ring when this request is complete.h]h>address of the doorbell to ring when this request is complete.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhjubah}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ]h"]h$]h&]uh1j hhhMRhj hhubj )}(hX1doorbell_attr doorbell attributes. * Bit(7) indicates if a write to a doorbell is to occur. * Bits(6:2) are reserved. * Bits(1:0) contain the encoding of the doorbell length. 0 is 32-bit, 1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address must be naturally aligned to the specified length. h](j )}(h doorbell_attrh]h doorbell_attr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhM[hjubj )}(hhh](h)}(hdoorbell attributes.h]hdoorbell attributes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjubju)}(hhh](jz)}(h6Bit(7) indicates if a write to a doorbell is to occur.h]h)}(hjh]h6Bit(7) indicates if a write to a doorbell is to occur.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hBits(6:2) are reserved.h]h)}(hjh]hBits(6:2) are reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hBits(1:0) contain the encoding of the doorbell length. 0 is 32-bit, 1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address must be naturally aligned to the specified length. h]h)}(hBits(1:0) contain the encoding of the doorbell length. 0 is 32-bit, 1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address must be naturally aligned to the specified length.h]hBits(1:0) contain the encoding of the doorbell length. 0 is 32-bit, 1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address must be naturally aligned to the specified length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]jjuh1jthhhMWhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hhhM[hj hhubj )}(hkdoorbell_data data to write to the doorbell. Only the bits corresponding to the doorbell length are valid. h](j )}(h doorbell_datah]h doorbell_data}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhM_hjubj )}(hhh]h)}(h\data to write to the doorbell. Only the bits corresponding to the doorbell length are valid.h]h\data to write to the doorbell. Only the bits corresponding to the doorbell length are valid.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj0ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hhhM_hj hhubj )}(hX?sem_cmdN semaphore command. * Bit(31) indicates this semaphore command is enabled. * Bit(30) is the to-device DMA fence. Block this request until all to-device DMA transfers are complete. * Bit(29) is the from-device DMA fence. Block this request until all from-device DMA transfers are complete. * Bits(28:27) are reserved. * Bits(26:24) are the semaphore command. 0 is NOP. 1 is init with the specified value. 2 is increment. 3 is decrement. 4 is wait until the semaphore is equal to the specified value. 5 is wait until the semaphore is greater or equal to the specified value. 6 is "P", wait until semaphore is greater than 0, then decrement by 1. 7 is reserved. * Bit(23) is reserved. * Bit(22) is the semaphore sync. 0 is post sync, which means that the semaphore operation is done after the DMA transfer. 1 is presync, which gates the DMA transfer. Only one presync is allowed per request. * Bit(21) is reserved. * Bits(20:16) is the index of the semaphore to operate on. * Bits(15:12) are reserved. * Bits(11:0) are the semaphore value to use in operations. h](j )}(hsem_cmdNh]hsem_cmdN}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMxhjMubj )}(hhh](h)}(hsemaphore command.h]hsemaphore command.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj_ubju)}(hhh](jz)}(h4Bit(31) indicates this semaphore command is enabled.h]h)}(hjuh]h4Bit(31) indicates this semaphore command is enabled.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjsubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hfBit(30) is the to-device DMA fence. Block this request until all to-device DMA transfers are complete.h]h)}(hfBit(30) is the to-device DMA fence. Block this request until all to-device DMA transfers are complete.h]hfBit(30) is the to-device DMA fence. Block this request until all to-device DMA transfers are complete.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hjBit(29) is the from-device DMA fence. Block this request until all from-device DMA transfers are complete.h]h)}(hjBit(29) is the from-device DMA fence. Block this request until all from-device DMA transfers are complete.h]hjBit(29) is the from-device DMA fence. Block this request until all from-device DMA transfers are complete.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hBits(28:27) are reserved.h]h)}(hjh]hBits(28:27) are reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hXSBits(26:24) are the semaphore command. 0 is NOP. 1 is init with the specified value. 2 is increment. 3 is decrement. 4 is wait until the semaphore is equal to the specified value. 5 is wait until the semaphore is greater or equal to the specified value. 6 is "P", wait until semaphore is greater than 0, then decrement by 1. 7 is reserved.h]h)}(hXSBits(26:24) are the semaphore command. 0 is NOP. 1 is init with the specified value. 2 is increment. 3 is decrement. 4 is wait until the semaphore is equal to the specified value. 5 is wait until the semaphore is greater or equal to the specified value. 6 is "P", wait until semaphore is greater than 0, then decrement by 1. 7 is reserved.h]hXWBits(26:24) are the semaphore command. 0 is NOP. 1 is init with the specified value. 2 is increment. 3 is decrement. 4 is wait until the semaphore is equal to the specified value. 5 is wait until the semaphore is greater or equal to the specified value. 6 is “P”, wait until semaphore is greater than 0, then decrement by 1. 7 is reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hBit(23) is reserved.h]h)}(hjh]hBit(23) is reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hBit(22) is the semaphore sync. 0 is post sync, which means that the semaphore operation is done after the DMA transfer. 1 is presync, which gates the DMA transfer. Only one presync is allowed per request.h]h)}(hBit(22) is the semaphore sync. 0 is post sync, which means that the semaphore operation is done after the DMA transfer. 1 is presync, which gates the DMA transfer. Only one presync is allowed per request.h]hBit(22) is the semaphore sync. 0 is post sync, which means that the semaphore operation is done after the DMA transfer. 1 is presync, which gates the DMA transfer. Only one presync is allowed per request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hBit(21) is reserved.h]h)}(hjh]hBit(21) is reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(h8Bits(20:16) is the index of the semaphore to operate on.h]h)}(hj1h]h8Bits(20:16) is the index of the semaphore to operate on.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhj/ubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(hBits(15:12) are reserved.h]h)}(hjHh]hBits(15:12) are reserved.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjFubah}(h]h ]h"]h$]h&]uh1jyhjpubjz)}(h9Bits(11:0) are the semaphore value to use in operations. h]h)}(h8Bits(11:0) are the semaphore value to use in operations.h]h8Bits(11:0) are the semaphore value to use in operations.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj]ubah}(h]h ]h"]h$]h&]uh1jyhjpubeh}(h]h ]h"]h$]h&]jjuh1jthhhMdhj_ubeh}(h]h ]h"]h$]h&]uh1j hjMubeh}(h]h ]h"]h$]h&]uh1j hhhMxhj hhubeh}(h]h ]h"]h$]h&]uh1j hjs hhhhhNubh)}(h+Overall, a request is processed in 4 steps:h]h+Overall, a request is processed in 4 steps:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhjs hhubjO)}(hhh](jz)}(h:If specified, the presync semaphore condition must be trueh]h)}(hjh]h:If specified, the presync semaphore condition must be true}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjubah}(h]h ]h"]h$]h&]uh1jyhjhhhhhNubjz)}(h#If enabled, the DMA transfer occursh]h)}(hjh]h#If enabled, the DMA transfer occurs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjubah}(h]h ]h"]h$]h&]uh1jyhjhhhhhNubjz)}(hmatches the req_id of the request that generated this element.h]h>matches the req_id of the request that generated this element.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZubah}(h]h ]h"]h$]h&]uh1j hjHubeh}(h]h ]h"]h$]h&]uh1j hhhMhjEubj )}(hLcompletion_code status of this request. 0 is success. Non-zero is an error. h](j )}(hcompletion_codeh]hcompletion_code}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjwubj )}(hhh]h)}(h;status of this request. 0 is success. Non-zero is an error.h]h;status of this request. 0 is success. Non-zero is an error.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjwubeh}(h]h ]h"]h$]h&]uh1j hhhMhjEhhubeh}(h]h ]h"]h$]h&]uh1j hjhhhhhNubh)}(hXThe DMA Bridge will generate a MSI to the host as a reaction to activity in the response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation algorithm, where it will only generate a MSI when the response FIFO transitions from empty to non-empty (unless force MSI is enabled and triggered). In response to this MSI, the host is expected to drain the response FIFO, and must take care to handle any race conditions between draining the FIFO, and the device inserting elements into the FIFO.Eh]hXThe DMA Bridge will generate a MSI to the host as a reaction to activity in the response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation algorithm, where it will only generate a MSI when the response FIFO transitions from empty to non-empty (unless force MSI is enabled and triggered). In response to this MSI, the host is expected to drain the response FIFO, and must take care to handle any race conditions between draining the FIFO, and the device inserting elements into the FIFO.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h] response-fifoah ]h"] response fifoah$]h&]uh1hhj hhhhhMubeh}(h]id1ah ]h"]h$]jah&]uh1hhhhhhhhKjKubh)}(hhh](h)}(h%Neural Network Control (NNC) Protocolh]h%Neural Network Control (NNC) Protocol}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(huThe NNC protocol is how the host makes requests to the QSM to manage workloads. It uses the QAIC_CONTROL MHI channel.h]huThe NNC protocol is how the host makes requests to the QSM to manage workloads. It uses the QAIC_CONTROL MHI channel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hEach NNC request is packaged into a message. Each message is a series of transactions. A passthrough type transaction can contain elements known as commands.h]hEach NNC request is packaged into a message. Each message is a series of transactions. A passthrough type transaction can contain elements known as commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hQSM requires NNC messages be little endian encoded and the fields be naturally aligned. Since there are 64-bit elements in some NNC messages, 64-bit alignment must be maintained.h]hQSM requires NNC messages be little endian encoded and the fields be naturally aligned. Since there are 64-bit elements in some NNC messages, 64-bit alignment must be maintained.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXtA message contains a header and then a series of transactions. A message may be at most 4K in size from QSM to the host. From the host to the QSM, a message can be at most 64K (maximum size of a single MHI packet), but there is a continuation feature where message N+1 can be marked as a continuation of message N. This is used for exceedingly large DMA xfer transactions.h]hXtA message contains a header and then a series of transactions. A message may be at most 4K in size from QSM to the host. From the host to the QSM, a message can be at most 64K (maximum size of a single MHI packet), but there is a continuation feature where message N+1 can be marked as a continuation of message N. This is used for exceedingly large DMA xfer transactions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hTransaction descriptionsh]hTransaction descriptions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj )}(hhh](j )}(hpassthrough Allows userspace to send an opaque payload directly to the QSM. This is used for NNC commands. Userspace is responsible for managing the QSM message requirements in the payload. h](j )}(h passthroughh]h passthrough}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhj&ubj )}(hhh]h)}(hAllows userspace to send an opaque payload directly to the QSM. This is used for NNC commands. Userspace is responsible for managing the QSM message requirements in the payload.h]hAllows userspace to send an opaque payload directly to the QSM. This is used for NNC commands. Userspace is responsible for managing the QSM message requirements in the payload.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1j hj&ubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#ubj )}(hpdma_xfer DMA transfer. Describes an object that the QSM should DMA into the device via address and size tuples. h](j )}(hdma_xferh]hdma_xfer}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjUubj )}(hhh]h)}(hfDMA transfer. Describes an object that the QSM should DMA into the device via address and size tuples.h]hfDMA transfer. Describes an object that the QSM should DMA into the device via address and size tuples.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjgubah}(h]h ]h"]h$]h&]uh1j hjUubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubj )}(h\activate Activate a workload onto NSPs. The host must provide memory to be used by the DBC. h](j )}(hactivateh]hactivate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjubj )}(hhh]h)}(hRActivate a workload onto NSPs. The host must provide memory to be used by the DBC.h]hRActivate a workload onto NSPs. The host must provide memory to be used by the DBC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubj )}(hFdeactivate Deactivate an active workload and return the NSPs to idle. h](j )}(h deactivateh]h deactivate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjubj )}(hhh]h)}(h:Deactivate an active workload and return the NSPs to idle.h]h:Deactivate an active workload and return the NSPs to idle.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubj )}(hastatus Query the QSM about it's NNC implementation. Returns the NNC version, and if CRC is used. h](j )}(hstatush]hstatus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjubj )}(hhh]h)}(hYQuery the QSM about it's NNC implementation. Returns the NNC version, and if CRC is used.h]h[Query the QSM about it’s NNC implementation. Returns the NNC version, and if CRC is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubj )}(h&terminate Release a user's resources. h](j )}(h terminateh]h terminate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjubj )}(hhh]h)}(hRelease a user's resources.h]hRelease a user’s resources.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubj )}(hdma_xfer_cont Continuation of a previous DMA transfer. If a DMA transfer cannot be specified in a single message (highly fragmented), this transaction can be used to specify more ranges. h](j )}(h dma_xfer_conth]h dma_xfer_cont}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhj@ubj )}(hhh]h)}(hContinuation of a previous DMA transfer. If a DMA transfer cannot be specified in a single message (highly fragmented), this transaction can be used to specify more ranges.h]hContinuation of a previous DMA transfer. If a DMA transfer cannot be specified in a single message (highly fragmented), this transaction can be used to specify more ranges.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1j hj@ubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubj )}(hQvalidate_partition Query to QSM to determine if a partition identifier is valid. h](j )}(hvalidate_partitionh]hvalidate_partition}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhMhjoubj )}(hhh]h)}(h=Query to QSM to determine if a partition identifier is valid.h]h=Query to QSM to determine if a partition identifier is valid.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjoubeh}(h]h ]h"]h$]h&]uh1j hhhMhj#hhubeh}(h]h ]h"]h$]h&]uh1j hjhhhhhNubh)}(hX Each message is tagged with a user id, and a partition id. The user id allows QSM to track resources, and release them when the user goes away (eg the process crashes). A partition id identifies the resource partition that QSM manages, which this message applies to.h]hX Each message is tagged with a user id, and a partition id. The user id allows QSM to track resources, and release them when the user goes away (eg the process crashes). A partition id identifies the resource partition that QSM manages, which this message applies to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hMessages may have CRCs. Messages should have CRCs applied until the QSM reports via the status transaction that CRCs are not needed. The QSM on the SA9000P requires CRCs for black channel safing.h]hMessages may have CRCs. Messages should have CRCs applied until the QSM reports via the status transaction that CRCs are not needed. The QSM on the SA9000P requires CRCs for black channel safing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]transaction-descriptionsah ]h"]transaction descriptionsah$]h&]uh1hhjhhhhhMubeh}(h]#neural-network-control-nnc-protocolah ]h"]%neural network control (nnc) protocolah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hSubsystem Restart (SSR)h]hSubsystem Restart (SSR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hXSSR is the concept of limiting the impact of an error. An AIC100 device may have multiple users, each with their own workload running. If the workload of one user crashes, the fallout of that should be limited to that workload and not impact other workloads. SSR accomplishes this.h]hXSSR is the concept of limiting the impact of an error. An AIC100 device may have multiple users, each with their own workload running. If the workload of one user crashes, the fallout of that should be limited to that workload and not impact other workloads. SSR accomplishes this.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXIf a particular workload crashes, QSM notifies the host via the QAIC_SSR MHI channel. This notification identifies the workload by it's assigned DBC. A multi-stage recovery process is then used to cleanup both sides, and get the DBC/NSPs into a working state.h]hXIf a particular workload crashes, QSM notifies the host via the QAIC_SSR MHI channel. This notification identifies the workload by it’s assigned DBC. A multi-stage recovery process is then used to cleanup both sides, and get the DBC/NSPs into a working state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXWhen SSR occurs, any state in the workload is lost. Any inputs that were in process, or queued by not yet serviced, are lost. The loaded artifacts will remain in on-card DDR, but the host will need to re-activate the workload if it desires to recover the workload.h]hXWhen SSR occurs, any state in the workload is lost. Any inputs that were in process, or queued by not yet serviced, are lost. The loaded artifacts will remain in on-card DDR, but the host will need to re-activate the workload if it desires to recover the workload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]subsystem-restart-ssrah ]h"]subsystem restart (ssr)ah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h0Reliability, Accessibility, Serviceability (RAS)h]h0Reliability, Accessibility, Serviceability (RAS)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hX4AIC100 is expected to be deployed in server systems where RAS ideology is applied. Simply put, RAS is the concept of detecting, classifying, and reporting errors. While PCIe has AER (Advanced Error Reporting) which factors into RAS, AER does not allow for a device to report details about internal errors. Therefore, AIC100 implements a custom RAS mechanism. When a RAS event occurs, QSM will report the event with appropriate details via the QAIC_STATUS MHI channel. A sysadmin may determine that a particular device needs additional service based on RAS reports.h]hX4AIC100 is expected to be deployed in server systems where RAS ideology is applied. Simply put, RAS is the concept of detecting, classifying, and reporting errors. While PCIe has AER (Advanced Error Reporting) which factors into RAS, AER does not allow for a device to report details about internal errors. Therefore, AIC100 implements a custom RAS mechanism. When a RAS event occurs, QSM will report the event with appropriate details via the QAIC_STATUS MHI channel. A sysadmin may determine that a particular device needs additional service based on RAS reports.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h],reliability-accessibility-serviceability-rasah ]h"]0reliability, accessibility, serviceability (ras)ah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h Telemetryh]h Telemetry}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhhhMubh)}(hXQSM has the ability to report various physical attributes of the device, and in some cases, to allow the host to control them. Examples include thermal limits, thermal readings, and power readings. These items are communicated via the QAIC_TELEMETRY MHI channel.h]hXQSM has the ability to report various physical attributes of the device, and in some cases, to allow the host to control them. Examples include thermal limits, thermal readings, and power readings. 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