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YEN SIGN h]h¥}hjLsbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(hAMD NPUh]hAMD NPU}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj]hhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jzhjwhhhKubh field_body)}(h(|copy| 2024 Advanced Micro Devices, Inc.h]h paragraph)}(hjh](h©}(hjhhhNhNubh" 2024 Advanced Micro Devices, Inc.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1juhhhK hjrhhubjv)}(hhh](j{)}(hAuthorh]hAuthor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jzhjhhhKubj)}(h$Sonal Santan h]j)}(h#Sonal Santan h](hSonal Santan <}(hjhhhNhNubh reference)}(hsonal.santan@amd.comh]hsonal.santan@amd.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:sonal.santan@amd.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1juhhhK hjrhhubeh}(h]h ]h"]h$]h&]uh1jphj]hhhhhK ubj\)}(hhh](ja)}(hOverviewh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK ubj)}(hXAMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator integrated into AMD client APU. NPU enables efficient execution of Machine Learning applications like CNN, LLM, etc. NPU is based on `AMD XDNA Architecture`_. NPU is managed by **amdxdna** driver.h](hAMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator integrated into AMD client APU. NPU enables efficient execution of Machine Learning applications like CNN, LLM, etc. NPU is based on }(hj hhhNhNubj)}(h`AMD XDNA Architecture`_h]hAMD XDNA Architecture}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAMD XDNA Architecturerefuri-https://www.amd.com/en/technologies/xdna.htmluh1jhj resolvedKubh. NPU is managed by }(hj hhhNhNubhstrong)}(h **amdxdna**h]hamdxdna}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j*hj ubh driver.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1j[hj]hhhhhK ubj\)}(hhh](ja)}(hHardware Descriptionh]hHardware Description}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjLhhhhhKubj)}(h6AMD NPU consists of the following hardware components:h]h6AMD NPU consists of the following hardware components:}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjLhhubj\)}(hhh](ja)}(hAMD XDNA Arrayh]hAMD XDNA Array}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjkhhhhhKubj)}(hXAMD XDNA Array comprises of 2D array of compute and memory tiles built with `AMD AI Engine Technology`_. Each column has 4 rows of compute tiles and 1 row of memory tile. Each compute tile contains a VLIW processor with its own dedicated program and data memory. The memory tile acts as L2 memory. The 2D array can be partitioned at a column boundary creating a spatially isolated partition which can be bound to a workload context.h](hLAMD XDNA Array comprises of 2D array of compute and memory tiles built with }(hj|hhhNhNubj)}(h`AMD AI Engine Technology`_h]hAMD AI Engine Technology}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameAMD AI Engine Technologyj#9https://www.xilinx.com/products/technology/ai-engine.htmluh1jhj|j%KubhXI. Each column has 4 rows of compute tiles and 1 row of memory tile. Each compute tile contains a VLIW processor with its own dedicated program and data memory. The memory tile acts as L2 memory. The 2D array can be partitioned at a column boundary creating a spatially isolated partition which can be bound to a workload context.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubj)}(hYEach column also has dedicated DMA engines to move data between host DDR and memory tile.h]hYEach column also has dedicated DMA engines to move data between host DDR and memory tile.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK$hjkhhubj)}(hAMD Phoenix and AMD Hawk Point client NPU have a 4x5 topology, i.e., 4 rows of compute tiles arranged into 5 columns. AMD Strix Point client APU have 4x8 topology, i.e., 4 rows of compute tiles arranged into 8 columns.h]hAMD Phoenix and AMD Hawk Point client NPU have a 4x5 topology, i.e., 4 rows of compute tiles arranged into 5 columns. AMD Strix Point client APU have 4x8 topology, i.e., 4 rows of compute tiles arranged into 8 columns.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK'hjkhhubeh}(h]amd-xdna-arrayah ]h"]amd xdna arrayah$]h&]uh1j[hjLhhhhhKubj\)}(hhh](ja)}(hShared L2 Memoryh]hShared L2 Memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK,ubj)}(hXThe single row of memory tiles create a pool of software managed on chip L2 memory. DMA engines are used to move data between host DDR and memory tiles. AMD Phoenix and AMD Hawk Point NPUs have a total of 2560 KB of L2 memory. AMD Strix Point NPU has a total of 4096 KB of L2 memory.h]hXThe single row of memory tiles create a pool of software managed on chip L2 memory. DMA engines are used to move data between host DDR and memory tiles. AMD Phoenix and AMD Hawk Point NPUs have a total of 2560 KB of L2 memory. AMD Strix Point NPU has a total of 4096 KB of L2 memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK.hjhhubeh}(h]shared-l2-memoryah ]h"]shared l2 memoryah$]h&]uh1j[hjLhhhhhK,ubj\)}(hhh](ja)}(hMicrocontrollerh]hMicrocontroller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhK4ubj)}(hA microcontroller runs NPU Firmware which is responsible for command processing, XDNA Array partition setup, XDNA Array configuration, workload context management and workload orchestration.h]hA microcontroller runs NPU Firmware which is responsible for command processing, XDNA Array partition setup, XDNA Array configuration, workload context management and workload orchestration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK6hjhhubj)}(hNPU Firmware uses a dedicated instance of an isolated non-privileged context called ERT to service each workload context. ERT is also used to execute user provided ``ctrlcode`` associated with the workload context.h](hNPU Firmware uses a dedicated instance of an isolated non-privileged context called ERT to service each workload context. ERT is also used to execute user provided }(hj hhhNhNubhliteral)}(h ``ctrlcode``h]hctrlcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh& associated with the workload context.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK:hjhhubj)}(hzNPU Firmware uses a single isolated privileged context called MERT to service management commands from the amdxdna driver.h]hzNPU Firmware uses a single isolated privileged context called MERT to service management commands from the amdxdna driver.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK>hjhhubeh}(h]microcontrollerah ]h"]microcontrollerah$]h&]uh1j[hjLhhhhhK4ubj\)}(hhh](ja)}(h Mailboxesh]h Mailboxes}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjAhhhhhKBubj)}(hX-The microcontroller and amdxdna driver use a privileged channel for management tasks like setting up of contexts, telemetry, query, error handling, setting up user channel, etc. As mentioned before, privileged channel requests are serviced by MERT. The privileged channel is bound to a single mailbox.h]hX-The microcontroller and amdxdna driver use a privileged channel for management tasks like setting up of contexts, telemetry, query, error handling, setting up user channel, etc. As mentioned before, privileged channel requests are serviced by MERT. The privileged channel is bound to a single mailbox.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKDhjAhhubj)}(hX&The microcontroller and amdxdna driver use a dedicated user channel per workload context. The user channel is primarily used for submitting work to the NPU. As mentioned before, a user channel requests are serviced by an instance of ERT. Each user channel is bound to its own dedicated mailbox.h]hX&The microcontroller and amdxdna driver use a dedicated user channel per workload context. The user channel is primarily used for submitting work to the NPU. As mentioned before, a user channel requests are serviced by an instance of ERT. Each user channel is bound to its own dedicated mailbox.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKIhjAhhubeh}(h] mailboxesah ]h"] mailboxesah$]h&]uh1j[hjLhhhhhKBubj\)}(hhh](ja)}(hPCIe EPh]hPCIe EP}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjvhhhhhKOubj)}(hX3NPU is visible to the x86 host CPU as a PCIe device with multiple BARs and some MSI-X interrupt vectors. NPU uses a dedicated high bandwidth SoC level fabric for reading or writing into host memory. Each instance of ERT gets its own dedicated MSI-X interrupt. MERT gets a single instance of MSI-X interrupt.h]hX3NPU is visible to the x86 host CPU as a PCIe device with multiple BARs and some MSI-X interrupt vectors. NPU uses a dedicated high bandwidth SoC level fabric for reading or writing into host memory. Each instance of ERT gets its own dedicated MSI-X interrupt. MERT gets a single instance of MSI-X interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKQhjvhhubj)}(hThe number of PCIe BARs varies depending on the specific device. Based on their functions, PCIe BARs can generally be categorized into the following types.h]hThe number of PCIe BARs varies depending on the specific device. Based on their functions, PCIe BARs can generally be categorized into the following types.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKVhjvhhubh bullet_list)}(hhh](h list_item)}(hBPSP BAR: Expose the AMD PSP (Platform Security Processor) functionh]j)}(hjh]hBPSP BAR: Expose the AMD PSP (Platform Security Processor) function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h=SMU BAR: Expose the AMD SMU (System Management Unit) functionh]j)}(hjh]h=SMU BAR: Expose the AMD SMU (System Management Unit) function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h-SRAM BAR: Expose ring buffers for the mailboxh]j)}(hjh]h-SRAM BAR: Expose ring buffers for the mailbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK[hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hUMailbox BAR: Expose the mailbox control registers (head, tail and ISR registers etc.)h]j)}(hUMailbox BAR: Expose the mailbox control registers (head, tail and ISR registers etc.)h]hUMailbox BAR: Expose the mailbox control registers (head, tail and ISR registers etc.)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK\hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h-Public Register BAR: Expose public registers h]j)}(h,Public Register BAR: Expose public registersh]h,Public Register BAR: Expose public registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhKYhjvhhubj)}(hOn specific devices, the above-mentioned BAR type might be combined into a single physical PCIe BAR. Or a module might require two physical PCIe BARs to be fully functional. For example,h]hOn specific devices, the above-mentioned BAR type might be combined into a single physical PCIe BAR. Or a module might require two physical PCIe BARs to be fully functional. For example,}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK`hjvhhubj)}(hhh](j)}(hNOn AMD Phoenix device, PSP, SMU, Public Register BARs are on PCIe BAR index 0.h]j)}(hj:h]hNOn AMD Phoenix device, PSP, SMU, Public Register BARs are on PCIe BAR index 0.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKdhj8ubah}(h]h ]h"]h$]h&]uh1jhj5hhhhhNubj)}(hOn AMD Strix Point device, Mailbox and Public Register BARs are on PCIe BAR index 0. The PSP has some registers in PCIe BAR index 0 (Public Register BAR) and PCIe BAR index 4 (PSP BAR). h]j)}(hOn AMD Strix Point device, Mailbox and Public Register BARs are on PCIe BAR index 0. The PSP has some registers in PCIe BAR index 0 (Public Register BAR) and PCIe BAR index 4 (PSP BAR).h]hOn AMD Strix Point device, Mailbox and Public Register BARs are on PCIe BAR index 0. The PSP has some registers in PCIe BAR index 0 (Public Register BAR) and PCIe BAR index 4 (PSP BAR).}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKehjOubah}(h]h ]h"]h$]h&]uh1jhj5hhhhhNubeh}(h]h ]h"]h$]h&]j%j&uh1jhhhKdhjvhhubeh}(h]pcie-epah ]h"]pcie epah$]h&]uh1j[hjLhhhhhKOubj\)}(hhh](ja)}(hProcess Isolation Hardwareh]hProcess Isolation Hardware}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjuhhhhhKjubj)}(hXAs explained before, XDNA Array can be dynamically divided into isolated spatial partitions, each of which may have one or more columns. The spatial partition is setup by programming the column isolation registers by the microcontroller. Each spatial partition is associated with a PASID which is also programmed by the microcontroller. Hence multiple spatial partitions in the NPU can make concurrent host access protected by PASID.h]hXAs explained before, XDNA Array can be dynamically divided into isolated spatial partitions, each of which may have one or more columns. The spatial partition is setup by programming the column isolation registers by the microcontroller. Each spatial partition is associated with a PASID which is also programmed by the microcontroller. Hence multiple spatial partitions in the NPU can make concurrent host access protected by PASID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKlhjuhhubj)}(hyThe NPU FW itself uses microcontroller MMU enforced isolated contexts for servicing user and privileged channel requests.h]hyThe NPU FW itself uses microcontroller MMU enforced isolated contexts for servicing user and privileged channel requests.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKshjuhhubeh}(h]process-isolation-hardwareah ]h"]process isolation hardwareah$]h&]uh1j[hjLhhhhhKjubeh}(h]hardware-descriptionah ]h"]hardware descriptionah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(h%Mixed Spatial and Temporal Schedulingh]h%Mixed Spatial and Temporal Scheduling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhKxubj)}(hXAMD XDNA architecture supports mixed spatial and temporal (time sharing) scheduling of 2D array. This means that spatial partitions may be setup and torn down dynamically to accommodate various workloads. A *spatial* partition may be *exclusively* bound to one workload context while another partition may be *temporarily* bound to more than one workload contexts. The microcontroller updates the PASID for a temporarily shared partition to match the context that has been bound to the partition at any moment.h](hAMD XDNA architecture supports mixed spatial and temporal (time sharing) scheduling of 2D array. This means that spatial partitions may be setup and torn down dynamically to accommodate various workloads. A }(hjhhhNhNubhemphasis)}(h *spatial*h]hspatial}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh partition may be }(hjhhhNhNubj)}(h *exclusively*h]h exclusively}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh> bound to one workload context while another partition may be }(hjhhhNhNubj)}(h *temporarily*h]h temporarily}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh bound to more than one workload contexts. The microcontroller updates the PASID for a temporarily shared partition to match the context that has been bound to the partition at any moment.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKzhjhhubj\)}(hhh](ja)}(hResource Solverh]hResource Solver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hXThe Resource Solver component of the amdxdna driver manages the allocation of 2D array among various workloads. Every workload describes the number of columns required to run the NPU binary in its metadata. The Resource Solver component uses hints passed by the workload and its own heuristics to decide 2D array (re)partition strategy and mapping of workloads for spatial and temporal sharing of columns. The FW enforces the context-to-column(s) resource binding decisions made by the Resource Solver.h]hXThe Resource Solver component of the amdxdna driver manages the allocation of 2D array among various workloads. Every workload describes the number of columns required to run the NPU binary in its metadata. The Resource Solver component uses hints passed by the workload and its own heuristics to decide 2D array (re)partition strategy and mapping of workloads for spatial and temporal sharing of columns. The FW enforces the context-to-column(s) resource binding decisions made by the Resource Solver.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hAMD Phoenix and AMD Hawk Point client NPU can support 6 concurrent workload contexts. AMD Strix Point can support 16 concurrent workload contexts.h]hAMD Phoenix and AMD Hawk Point client NPU can support 6 concurrent workload contexts. AMD Strix Point can support 16 concurrent workload contexts.}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubeh}(h]resource-solverah ]h"]resource solverah$]h&]uh1j[hjhhhhhKubeh}(h]%mixed-spatial-and-temporal-schedulingah ]h"]%mixed spatial and temporal schedulingah$]h&]uh1j[hj]hhhhhKxubj\)}(hhh](ja)}(hApplication Binariesh]hApplication Binaries}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjF hhhhhKubj)}(hiA NPU application workload is comprised of two separate binaries which are generated by the NPU compiler.h]hiA NPU application workload is comprised of two separate binaries which are generated by the NPU compiler.}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjF hhubhenumerated_list)}(hhh](j)}(hXzAMD XDNA Array overlay, which is used to configure a NPU spatial partition. The overlay contains instructions for setting up the stream switch configuration and ELF for the compute tiles. The overlay is loaded on the spatial partition bound to the workload by the associated ERT instance. Refer to the `Versal Adaptive SoC AIE-ML Architecture Manual (AM020)`_ for more details. h]j)}(hXyAMD XDNA Array overlay, which is used to configure a NPU spatial partition. The overlay contains instructions for setting up the stream switch configuration and ELF for the compute tiles. The overlay is loaded on the spatial partition bound to the workload by the associated ERT instance. Refer to the `Versal Adaptive SoC AIE-ML Architecture Manual (AM020)`_ for more details.h](hX.AMD XDNA Array overlay, which is used to configure a NPU spatial partition. The overlay contains instructions for setting up the stream switch configuration and ELF for the compute tiles. The overlay is loaded on the spatial partition bound to the workload by the associated ERT instance. Refer to the }(hjn hhhNhNubj)}(h9`Versal Adaptive SoC AIE-ML Architecture Manual (AM020)`_h]h6Versal Adaptive SoC AIE-ML Architecture Manual (AM020)}(hjv hhhNhNubah}(h]h ]h"]h$]h&]name6Versal Adaptive SoC AIE-ML Architecture Manual (AM020)j#0https://docs.amd.com/r/en-US/am020-versal-aie-mluh1jhjn j%Kubh for more details.}(hjn hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjj ubah}(h]h ]h"]h$]h&]uh1jhjg hhhhhNubj)}(hXH``ctrlcode``, used for orchestrating the overlay loaded on the spatial partition. ``ctrlcode`` is executed by the ERT running in protected mode on the microcontroller in the context of the workload. ``ctrlcode`` is made up of a sequence of opcodes named ``XAie_TxnOpcode``. Refer to the `AI Engine Run Time`_ for more details. h]j)}(hXF``ctrlcode``, used for orchestrating the overlay loaded on the spatial partition. ``ctrlcode`` is executed by the ERT running in protected mode on the microcontroller in the context of the workload. ``ctrlcode`` is made up of a sequence of opcodes named ``XAie_TxnOpcode``. Refer to the `AI Engine Run Time`_ for more details.h](j)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhF, used for orchestrating the overlay loaded on the spatial partition. }(hj hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhi is executed by the ERT running in protected mode on the microcontroller in the context of the workload. }(hj hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh+ is made up of a sequence of opcodes named }(hj hhhNhNubj)}(h``XAie_TxnOpcode``h]hXAie_TxnOpcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh. Refer to the }(hj hhhNhNubj)}(h`AI Engine Run Time`_h]hAI Engine Run Time}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameAI Engine Run Timej#6https://github.com/Xilinx/aie-rt/tree/release/main_aiguh1jhj j%Kubh for more details.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjg hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1je hjF hhhhhKubeh}(h]application-binariesah ]h"]application binariesah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(hSpecial Host Buffersh]hSpecial Host Buffers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj\)}(hhh](ja)}(hPer-context Instruction Bufferh]hPer-context Instruction Buffer}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj, hhhhhKubj)}(hXtEvery workload context uses a host resident 64 MB buffer which is memory mapped into the ERT instance created to service the workload. The ``ctrlcode`` used by the workload is copied into this special memory. This buffer is protected by PASID like all other input/output buffers used by that workload. Instruction buffer is also mapped into the user space of the workload.h](hEvery workload context uses a host resident 64 MB buffer which is memory mapped into the ERT instance created to service the workload. The }(hj= hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj= ubh used by the workload is copied into this special memory. This buffer is protected by PASID like all other input/output buffers used by that workload. Instruction buffer is also mapped into the user space of the workload.}(hj= hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj, hhubeh}(h]per-context-instruction-bufferah ]h"]per-context instruction bufferah$]h&]uh1j[hj hhhhhKubj\)}(hhh](ja)}(hGlobal Privileged Bufferh]hGlobal Privileged Buffer}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hje hhhhhKubj)}(hIn addition, the driver also allocates a single buffer for maintenance tasks like recording errors from MERT. This global buffer uses the global IOMMU domain and is only accessible by MERT.h]hIn addition, the driver also allocates a single buffer for maintenance tasks like recording errors from MERT. This global buffer uses the global IOMMU domain and is only accessible by MERT.}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhje hhubeh}(h]global-privileged-bufferah ]h"]global privileged bufferah$]h&]uh1j[hj hhhhhKubeh}(h]special-host-buffersah ]h"]special host buffersah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(hHigh-level Use Flowh]hHigh-level Use Flow}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(h0Here are the steps to run a workload on AMD NPU:h]h0Here are the steps to run a workload on AMD NPU:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubjf )}(hhh](j)}(h?Compile the workload into an overlay and a ``ctrlcode`` binary.h]j)}(hj h](h+Compile the workload into an overlay and a }(hj hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh binary.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hAUserspace opens a context in the driver and provides the overlay.h]j)}(hj h]hAUserspace opens a context in the driver and provides the overlay.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h^The driver checks with the Resource Solver for provisioning a set of columns for the workload.h]j)}(h^The driver checks with the Resource Solver for provisioning a set of columns for the workload.h]h^The driver checks with the Resource Solver for provisioning a set of columns for the workload.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hUThe driver then asks MERT to create a context on the device with the desired columns.h]j)}(hUThe driver then asks MERT to create a context on the device with the desired columns.h]hUThe driver then asks MERT to create a context on the device with the desired columns.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h\MERT then creates an instance of ERT. MERT also maps the Instruction Buffer into ERT memory.h]j)}(h\MERT then creates an instance of ERT. MERT also maps the Instruction Buffer into ERT memory.h]h\MERT then creates an instance of ERT. MERT also maps the Instruction Buffer into ERT memory.}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj& ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hEThe userspace then copies the ``ctrlcode`` to the Instruction Buffer.h]j)}(hj@ h](hThe userspace then copies the }(hjB hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB ubh to the Instruction Buffer.}(hjB hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj> ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hUserspace then creates a command buffer with pointers to input, output, and instruction buffer; it then submits command buffer with the driver and goes to sleep waiting for completion.h]j)}(hUserspace then creates a command buffer with pointers to input, output, and instruction buffer; it then submits command buffer with the driver and goes to sleep waiting for completion.h]hUserspace then creates a command buffer with pointers to input, output, and instruction buffer; it then submits command buffer with the driver and goes to sleep waiting for completion.}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjg ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h5The driver sends the command over the Mailbox to ERT.h]j)}(hj h]h5The driver sends the command over the Mailbox to ERT.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h:ERT *executes* the ``ctrlcode`` in the instruction buffer.h]j)}(hj h](hERT }(hj hhhNhNubj)}(h *executes*h]hexecutes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh the }(hj hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh in the instruction buffer.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hfExecution of the ``ctrlcode`` kicks off DMAs to and from the host DDR while AMD XDNA Array is running.h]j)}(hfExecution of the ``ctrlcode`` kicks off DMAs to and from the host DDR while AMD XDNA Array is running.h](hExecution of the }(hj hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhI kicks off DMAs to and from the host DDR while AMD XDNA Array is running.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hWhen ERT reaches end of ``ctrlcode``, it raises an MSI-X to send completion signal to the driver which then wakes up the waiting workload. h]j)}(hWhen ERT reaches end of ``ctrlcode``, it raises an MSI-X to send completion signal to the driver which then wakes up the waiting workload.h](hWhen ERT reaches end of }(hj hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubhf, it raises an MSI-X to send completion signal to the driver which then wakes up the waiting workload.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]j j j hj j uh1je hj hhhhhKubeh}(h]high-level-use-flowah ]h"]high-level use flowah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(h Boot Flowh]h Boot Flow}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj3 hhhhhKubj)}(hXAamdxdna driver uses PSP to securely load signed NPU FW and kick off the boot of the NPU microcontroller. amdxdna driver then waits for the alive signal in a special location on BAR 0. The NPU is switched off during SoC suspend and turned on after resume where the NPU FW is reloaded, and the handshake is performed again.h]hXAamdxdna driver uses PSP to securely load signed NPU FW and kick off the boot of the NPU microcontroller. amdxdna driver then waits for the alive signal in a special location on BAR 0. The NPU is switched off during SoC suspend and turned on after resume where the NPU FW is reloaded, and the handshake is performed again.}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj3 hhubeh}(h] boot-flowah ]h"] boot flowah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(hUserspace componentsh]hUserspace components}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjZ hhhhhKubj\)}(hhh](ja)}(hCompilerh]hCompiler}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjk hhhhhKubj)}(hPeano is an LLVM based open-source single core compiler for AMD XDNA Array compute tile. Peano is available at: https://github.com/Xilinx/llvm-aieh](hpPeano is an LLVM based open-source single core compiler for AMD XDNA Array compute tile. Peano is available at: }(hj| hhhNhNubj)}(h"https://github.com/Xilinx/llvm-aieh]h"https://github.com/Xilinx/llvm-aie}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj| ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjk hhubj)}(hIRON is an open-source array compiler for AMD XDNA Array based NPU which uses Peano underneath. IRON is available at: https://github.com/Xilinx/mlir-aieh](hvIRON is an open-source array compiler for AMD XDNA Array based NPU which uses Peano underneath. IRON is available at: }(hj hhhNhNubj)}(h"https://github.com/Xilinx/mlir-aieh]h"https://github.com/Xilinx/mlir-aie}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjk hhubeh}(h]compilerah ]h"]compilerah$]h&]uh1j[hjZ hhhhhKubj\)}(hhh](ja)}(hUsermode Driver (UMD)h]hUsermode Driver (UMD)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(h{The open-source XRT runtime stack interfaces with amdxdna kernel driver. XRT can be found at: https://github.com/Xilinx/XRTh](h^The open-source XRT runtime stack interfaces with amdxdna kernel driver. XRT can be found at: }(hj hhhNhNubj)}(hhttps://github.com/Xilinx/XRTh]hhttps://github.com/Xilinx/XRT}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hWThe open-source XRT shim for NPU is can be found at: https://github.com/amd/xdna-driverh](h5The open-source XRT shim for NPU is can be found at: }(hj hhhNhNubj)}(h"https://github.com/amd/xdna-driverh]h"https://github.com/amd/xdna-driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubeh}(h]usermode-driver-umdah ]h"]usermode driver (umd)ah$]h&]uh1j[hjZ hhhhhKubeh}(h]userspace-componentsah ]h"]userspace componentsah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(h DMA Operationh]h DMA Operation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hDMA operation instructions are encoded in the ``ctrlcode`` as ``XAIE_IO_BLOCKWRITE`` opcode. When ERT executes ``XAIE_IO_BLOCKWRITE``, DMA operations between host DDR and L2 memory are effected.h](h.DMA operation instructions are encoded in the }(hj* hhhNhNubj)}(h ``ctrlcode``h]hctrlcode}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj* ubh as }(hj* hhhNhNubj)}(h``XAIE_IO_BLOCKWRITE``h]hXAIE_IO_BLOCKWRITE}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj* ubh opcode. When ERT executes }(hj* hhhNhNubj)}(h``XAIE_IO_BLOCKWRITE``h]hXAIE_IO_BLOCKWRITE}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj* ubh=, DMA operations between host DDR and L2 memory are effected.}(hj* hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubeh}(h] dma-operationah ]h"] dma operationah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(hError Handlingh]hError Handling}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjv hhhhhKubj)}(hX}When MERT detects an error in AMD XDNA Array, it pauses execution for that workload context and sends an asynchronous message to the driver over the privileged channel. The driver then sends a buffer pointer to MERT to capture the register states for the partition bound to faulting workload context. The driver then decodes the error by reading the contents of the buffer pointer.h]hX}When MERT detects an error in AMD XDNA Array, it pauses execution for that workload context and sends an asynchronous message to the driver over the privileged channel. The driver then sends a buffer pointer to MERT to capture the register states for the partition bound to faulting workload context. The driver then decodes the error by reading the contents of the buffer pointer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjv hhubeh}(h]error-handlingah ]h"]error handlingah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(h Telemetryh]h Telemetry}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhMubj)}(hJMERT can report various kinds of telemetry information like the following:h]hJMERT can report various kinds of telemetry information like the following:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj hhubj)}(hhh](j)}(hL1 interrupt counterh]j)}(hj h]hL1 interrupt counter}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h DMA counterh]j)}(hj h]h DMA counter}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hDeep Sleep counterh]j)}(hj h]hDeep Sleep counter}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hetc. h]j)}(hetc.h]hetc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]j%j&uh1jhhhM hj hhubhtarget)}(h.. _amdxdna-usage-stats:h]h}(h]h ]h"]h$]h&]refidamdxdna-usage-statsuh1j"hMghj hhhhubeh}(h] telemetryah ]h"] telemetryah$]h&]uh1j[hj]hhhhhMubj\)}(hhh](ja)}(h-Amdxdna DRM client usage stats implementationh]h-Amdxdna DRM client usage stats implementation}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj8hhhhhMubj)}(hvThe amdxdna driver implements the DRM client usage stats specification as documented in :ref:`drm-client-usage-stats`.h](hXThe amdxdna driver implements the DRM client usage stats specification as documented in }(hjIhhhNhNubh)}(h:ref:`drm-client-usage-stats`h]hinline)}(hjSh]hdrm-client-usage-stats}(hjWhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jUhjQubah}(h]h ]h"]h$]h&]refdocaccel/amdxdna/amdnpu refdomainjbreftyperef refexplicitrefwarn reftargetdrm-client-usage-statsuh1hhhhMhjIubh.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj8hhubj)}(h>Example of the output showing the implemented key value pairs:h]h>Example of the output showing the implemented key value pairs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj8hhubh literal_block)}(hXNpos: 0 flags: 0100002 mnt_id: 29 ino: 939 drm-driver: amdxdna_accel_driver drm-client-id: 3219 drm-pdev: 0000:c5:00.1 amdxdna_accel_driver-heap-alloc: 60 KiB amdxdna_accel_driver-internal-alloc: 67588 KiB amdxdna_accel_driver-external-alloc: 0 drm-total-memory: 67632 KiB drm-shared-memory: 0h]hXNpos: 0 flags: 0100002 mnt_id: 29 ino: 939 drm-driver: amdxdna_accel_driver drm-client-id: 3219 drm-pdev: 0000:c5:00.1 amdxdna_accel_driver-heap-alloc: 60 KiB amdxdna_accel_driver-internal-alloc: 67588 KiB amdxdna_accel_driver-external-alloc: 0 drm-total-memory: 67632 KiB drm-shared-memory: 0}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj8hhubeh}(h](-amdxdna-drm-client-usage-stats-implementationj/eh ]h"](-amdxdna drm client usage stats implementationamdxdna-usage-statseh$]h&]uh1j[hj]hhhhhMexpect_referenced_by_name}jj$sexpect_referenced_by_id}j/j$subj\)}(hhh](ja)}(h Referencesh]h References}(hjhhhNhNubah}(h]h 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