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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h+The PCI Express Port Bus Driver Guide HOWTOh]h+The PCI Express Port Bus Driver Guide HOWTO}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjchhhKubh field_body)}(h.Tom L Nguyen tom.l.nguyen@intel.com 11/03/2004h]h paragraph)}(hjzh](h Tom L Nguyen }(hj~hhhNhNubh reference)}(htom.l.nguyen@intel.comh]htom.l.nguyen@intel.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:tom.l.nguyen@intel.comuh1jhj~ubh 11/03/2004}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1j|hhhKhjxubah}(h]h ]h"]h$]h&]uh1jvhjcubeh}(h]h ]h"]h$]h&]uh1jahhhKhj^hhubjb)}(hhh](jg)}(h Copyrighth]h Copyright}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjhhhKubjw)}(h|copy| 2004 Intel Corporation h]j})}(h|copy| 2004 Intel Corporationh](h©}(hjhhhNhNubh 2004 Intel Corporation}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j|hhhK hjubah}(h]h ]h"]h$]h&]uh1jvhjubeh}(h]h ]h"]h$]h&]uh1jahhhK hj^hhubeh}(h]h ]h"]h$]h&]uh1j\hjIhhhhhKubjH)}(hhh](jM)}(hAbout this guideh]hAbout this guide}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhK ubj})}(hThis guide describes the basics of the PCI Express Port Bus driver and provides information on how to enable the service drivers to register/unregister with the PCI Express Port Bus Driver.h]hThis guide describes the basics of the PCI Express Port Bus driver and provides information on how to enable the service drivers to register/unregister with the PCI Express Port Bus Driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubeh}(h]about-this-guideah ]h"]about this guideah$]h&]uh1jGhjIhhhhhK ubjH)}(hhh](jM)}(h'What is the PCI Express Port Bus Driverh]h'What is the PCI Express Port Bus Driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj})}(hXCA PCI Express Port is a logical PCI-PCI Bridge structure. There are two types of PCI Express Port: the Root Port and the Switch Port. The Root Port originates a PCI Express link from a PCI Express Root Complex and the Switch Port connects PCI Express links to internal logical PCI buses. The Switch Port, which has its secondary bus representing the switch's internal routing logic, is called the switch's Upstream Port. The switch's Downstream Port is bridging from switch's internal routing bus to a bus representing the downstream PCI Express link from the PCI Express Switch.h]hXKA PCI Express Port is a logical PCI-PCI Bridge structure. There are two types of PCI Express Port: the Root Port and the Switch Port. The Root Port originates a PCI Express link from a PCI Express Root Complex and the Switch Port connects PCI Express links to internal logical PCI buses. The Switch Port, which has its secondary bus representing the switch’s internal routing logic, is called the switch’s Upstream Port. The switch’s Downstream Port is bridging from switch’s internal routing bus to a bus representing the downstream PCI Express link from the PCI Express Switch.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(hXA PCI Express Port can provide up to four distinct functions, referred to in this document as services, depending on its port type. PCI Express Port's services include native hotplug support (HP), power management event support (PME), advanced error reporting support (AER), and virtual channel support (VC). These services may be handled by a single complex driver or be individually distributed and handled by corresponding service drivers.h]hXA PCI Express Port can provide up to four distinct functions, referred to in this document as services, depending on its port type. PCI Express Port’s services include native hotplug support (HP), power management event support (PME), advanced error reporting support (AER), and virtual channel support (VC). These services may be handled by a single complex driver or be individually distributed and handled by corresponding service drivers.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK hj hhubeh}(h]'what-is-the-pci-express-port-bus-driverah ]h"]'what is the pci express port bus driverah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(h(Why use the PCI Express Port Bus Driver?h]h(Why use the PCI Express Port Bus Driver?}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjBhhhhhK)ubj})}(hXIn existing Linux kernels, the Linux Device Driver Model allows a physical device to be handled by only a single driver. The PCI Express Port is a PCI-PCI Bridge device with multiple distinct services. To maintain a clean and simple solution each service may have its own software service driver. In this case several service drivers will compete for a single PCI-PCI Bridge device. For example, if the PCI Express Root Port native hotplug service driver is loaded first, it claims a PCI-PCI Bridge Root Port. The kernel therefore does not load other service drivers for that Root Port. In other words, it is impossible to have multiple service drivers load and run on a PCI-PCI Bridge device simultaneously using the current driver model.h]hXIn existing Linux kernels, the Linux Device Driver Model allows a physical device to be handled by only a single driver. The PCI Express Port is a PCI-PCI Bridge device with multiple distinct services. To maintain a clean and simple solution each service may have its own software service driver. In this case several service drivers will compete for a single PCI-PCI Bridge device. For example, if the PCI Express Root Port native hotplug service driver is loaded first, it claims a PCI-PCI Bridge Root Port. The kernel therefore does not load other service drivers for that Root Port. In other words, it is impossible to have multiple service drivers load and run on a PCI-PCI Bridge device simultaneously using the current driver model.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK+hjBhhubj})}(hXETo enable multiple service drivers running simultaneously requires having a PCI Express Port Bus driver, which manages all populated PCI Express Ports and distributes all provided service requests to the corresponding service drivers as required. Some key advantages of using the PCI Express Port Bus driver are listed below:h]hXETo enable multiple service drivers running simultaneously requires having a PCI Express Port Bus driver, which manages all populated PCI Express Ports and distributes all provided service requests to the corresponding service drivers as required. Some key advantages of using the PCI Express Port Bus driver are listed below:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK8hjBhhubh block_quote)}(hXU- Allow multiple service drivers to run simultaneously on a PCI-PCI Bridge Port device. - Allow service drivers implemented in an independent staged approach. - Allow one service driver to run on multiple PCI-PCI Bridge Port devices. - Manage and distribute resources of a PCI-PCI Bridge Port device to requested service drivers. h]h bullet_list)}(hhh](h list_item)}(hVAllow multiple service drivers to run simultaneously on a PCI-PCI Bridge Port device. h]j})}(hUAllow multiple service drivers to run simultaneously on a PCI-PCI Bridge Port device.h]hUAllow multiple service drivers to run simultaneously on a PCI-PCI Bridge Port device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK>hj|ubah}(h]h ]h"]h$]h&]uh1jzhjwubj{)}(hEAllow service drivers implemented in an independent staged approach. h]j})}(hDAllow service drivers implemented in an independent staged approach.h]hDAllow service drivers implemented in an independent staged approach.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKAhjubah}(h]h ]h"]h$]h&]uh1jzhjwubj{)}(hIAllow one service driver to run on multiple PCI-PCI Bridge Port devices. h]j})}(hHAllow one service driver to run on multiple PCI-PCI Bridge Port devices.h]hHAllow one service driver to run on multiple PCI-PCI Bridge Port devices.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKDhjubah}(h]h ]h"]h$]h&]uh1jzhjwubj{)}(h^Manage and distribute resources of a PCI-PCI Bridge Port device to requested service drivers. h]j})}(h]Manage and distribute resources of a PCI-PCI Bridge Port device to requested service drivers.h]h]Manage and distribute resources of a PCI-PCI Bridge Port device to requested service drivers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKGhjubah}(h]h ]h"]h$]h&]uh1jzhjwubeh}(h]h ]h"]h$]h&]bullet-uh1juhhhK>hjqubah}(h]h ]h"]h$]h&]uh1johhhK>hjBhhubeh}(h]'why-use-the-pci-express-port-bus-driverah ]h"](why use the pci express port bus driver?ah$]h&]uh1jGhjIhhhhhK)ubjH)}(hhh](jM)}(h?Configuring the PCI Express Port Bus Driver vs. Service Driversh]h?Configuring the PCI Express Port Bus Driver vs. Service Drivers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKKubjH)}(hhh](jM)}(hAIncluding the PCI Express Port Bus Driver Support into the Kernelh]hAIncluding the PCI Express Port Bus Driver Support into the Kernel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKNubj})}(hXIncluding the PCI Express Port Bus driver depends on whether the PCI Express support is included in the kernel config. The kernel will automatically include the PCI Express Port Bus driver as a kernel driver when the PCI Express support is enabled in the kernel.h]hXIncluding the PCI Express Port Bus driver depends on whether the PCI Express support is included in the kernel config. The kernel will automatically include the PCI Express Port Bus driver as a kernel driver when the PCI Express support is enabled in the kernel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKPhjhhubeh}(h]Aincluding-the-pci-express-port-bus-driver-support-into-the-kernelah ]h"]Aincluding the pci express port bus driver support into the kernelah$]h&]uh1jGhjhhhhhKNubjH)}(hhh](jM)}(hEnabling Service Driver Supporth]hEnabling Service Driver Support}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj*hhhhhKVubj})}(hXPCI device drivers are implemented based on Linux Device Driver Model. All service drivers are PCI device drivers. As discussed above, it is impossible to load any service driver once the kernel has loaded the PCI Express Port Bus Driver. To meet the PCI Express Port Bus Driver Model requires some minimal changes on existing service drivers that imposes no impact on the functionality of existing service drivers.h]hXPCI device drivers are implemented based on Linux Device Driver Model. All service drivers are PCI device drivers. As discussed above, it is impossible to load any service driver once the kernel has loaded the PCI Express Port Bus Driver. To meet the PCI Express Port Bus Driver Model requires some minimal changes on existing service drivers that imposes no impact on the functionality of existing service drivers.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKXhj*hhubj})}(hXA service driver is required to use the two APIs shown below to register its service with the PCI Express Port Bus driver (see section 5.2.1 & 5.2.2). It is important that a service driver initializes the pcie_port_service_driver data structure, included in header file /include/linux/pcieport_if.h, before calling these APIs. Failure to do so will result an identity mismatch, which prevents the PCI Express Port Bus driver from loading a service driver.h]hXA service driver is required to use the two APIs shown below to register its service with the PCI Express Port Bus driver (see section 5.2.1 & 5.2.2). It is important that a service driver initializes the pcie_port_service_driver data structure, included in header file /include/linux/pcieport_if.h, before calling these APIs. Failure to do so will result an identity mismatch, which prevents the PCI Express Port Bus driver from loading a service driver.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK_hj*hhubjH)}(hhh](jM)}(hpcie_port_service_registerh]hpcie_port_service_register}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjWhhhhhKhubh literal_block)}(hDint pcie_port_service_register(struct pcie_port_service_driver *new)h]hDint pcie_port_service_register(struct pcie_port_service_driver *new)}hjjsbah}(h]h ]h"]h$]h&]hhuh1jhhhhKkhjWhhubj})}(hXPThis API replaces the Linux Driver Model's pci_register_driver API. A service driver should always calls pcie_port_service_register at module init. Note that after service driver being loaded, calls such as pci_enable_device(dev) and pci_set_master(dev) are no longer necessary since these calls are executed by the PCI Port Bus driver.h]hXRThis API replaces the Linux Driver Model’s pci_register_driver API. A service driver should always calls pcie_port_service_register at module init. Note that after service driver being loaded, calls such as pci_enable_device(dev) and pci_set_master(dev) are no longer necessary since these calls are executed by the PCI Port Bus driver.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKmhjWhhubeh}(h]pcie-port-service-registerah ]h"]pcie_port_service_registerah$]h&]uh1jGhj*hhhhhKhubjH)}(hhh](jM)}(hpcie_port_service_unregisterh]hpcie_port_service_unregister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKtubji)}(hGvoid pcie_port_service_unregister(struct pcie_port_service_driver *new)h]hGvoid pcie_port_service_unregister(struct pcie_port_service_driver *new)}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhhKwhjhhubj})}(hpcie_port_service_unregister replaces the Linux Driver Model's pci_unregister_driver. It's always called by service driver when a module exits.h]hpcie_port_service_unregister replaces the Linux Driver Model’s pci_unregister_driver. It’s always called by service driver when a module exits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKyhjhhubeh}(h]pcie-port-service-unregisterah ]h"]pcie_port_service_unregisterah$]h&]uh1jGhj*hhhhhKtubjH)}(hhh](jM)}(h Sample Codeh]h Sample Code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhK~ubj})}(h\Below is sample service driver code to initialize the port service driver data structure. ::h]hYBelow is sample service driver code to initialize the port service driver data structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubji)}(hXstatic struct pcie_port_service_id service_id[] = { { .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, .port_type = PCIE_RC_PORT, .service_type = PCIE_PORT_SERVICE_AER, }, { /* end: all zeroes */ } }; static struct pcie_port_service_driver root_aerdrv = { .name = (char *)device_name, .id_table = service_id, .probe = aerdrv_load, .remove = aerdrv_unload, .suspend = aerdrv_suspend, .resume = aerdrv_resume, };h]hXstatic struct pcie_port_service_id service_id[] = { { .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, .port_type = PCIE_RC_PORT, .service_type = PCIE_PORT_SERVICE_AER, }, { /* end: all zeroes */ } }; static struct pcie_port_service_driver root_aerdrv = { .name = (char *)device_name, .id_table = service_id, .probe = aerdrv_load, .remove = aerdrv_unload, .suspend = aerdrv_suspend, .resume = aerdrv_resume, };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhhKhjhhubj})}(hIBelow is a sample code for registering/unregistering a service driver. ::h]hFBelow is a sample code for registering/unregistering a service driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubji)}(hX]static int __init aerdrv_service_init(void) { int retval = 0; retval = pcie_port_service_register(&root_aerdrv); if (!retval) { /* * FIX ME */ } return retval; } static void __exit aerdrv_service_exit(void) { pcie_port_service_unregister(&root_aerdrv); } module_init(aerdrv_service_init); module_exit(aerdrv_service_exit);h]hX]static int __init aerdrv_service_init(void) { int retval = 0; retval = pcie_port_service_register(&root_aerdrv); if (!retval) { /* * FIX ME */ } return retval; } static void __exit aerdrv_service_exit(void) { pcie_port_service_unregister(&root_aerdrv); } module_init(aerdrv_service_init); module_exit(aerdrv_service_exit);}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhhKhjhhubeh}(h] sample-codeah ]h"] sample codeah$]h&]uh1jGhj*hhhhhK~ubeh}(h]enabling-service-driver-supportah ]h"]enabling service driver supportah$]h&]uh1jGhjhhhhhKVubeh}(h]>configuring-the-pci-express-port-bus-driver-vs-service-driversah ]h"]?configuring the pci express port bus driver vs. service driversah$]h&]uh1jGhjIhhhhhKKubjH)}(hhh](jM)}(hPossible Resource Conflictsh]hPossible Resource Conflicts}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj$hhhhhKubj})}(hSince all service drivers of a PCI-PCI Bridge Port device are allowed to run simultaneously, below lists a few of possible resource conflicts with proposed solutions.h]hSince all service drivers of a PCI-PCI Bridge Port device are allowed to run simultaneously, below lists a few of possible resource conflicts with proposed solutions.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj$hhubjH)}(hhh](jM)}(hMSI and MSI-X Vector Resourceh]hMSI and MSI-X Vector Resource}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjChhhhhKubj})}(hX*Once MSI or MSI-X interrupts are enabled on a device, it stays in this mode until they are disabled again. Since service drivers of the same PCI-PCI Bridge port share the same physical device, if an individual service driver enables or disables MSI/MSI-X mode it may result unpredictable behavior.h]hX*Once MSI or MSI-X interrupts are enabled on a device, it stays in this mode until they are disabled again. Since service drivers of the same PCI-PCI Bridge port share the same physical device, if an individual service driver enables or disables MSI/MSI-X mode it may result unpredictable behavior.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjChhubj})}(hXTTo avoid this situation all service drivers are not permitted to switch interrupt mode on its device. The PCI Express Port Bus driver is responsible for determining the interrupt mode and this should be transparent to service drivers. Service drivers need to know only the vector IRQ assigned to the field irq of struct pcie_device, which is passed in when the PCI Express Port Bus driver probes each service driver. Service drivers should use (struct pcie_device*)dev->irq to call request_irq/free_irq. In addition, the interrupt mode is stored in the field interrupt_mode of struct pcie_device.h]hXTTo avoid this situation all service drivers are not permitted to switch interrupt mode on its device. The PCI Express Port Bus driver is responsible for determining the interrupt mode and this should be transparent to service drivers. Service drivers need to know only the vector IRQ assigned to the field irq of struct pcie_device, which is passed in when the PCI Express Port Bus driver probes each service driver. Service drivers should use (struct pcie_device*)dev->irq to call request_irq/free_irq. In addition, the interrupt mode is stored in the field interrupt_mode of struct pcie_device.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjChhubeh}(h]msi-and-msi-x-vector-resourceah ]h"]msi and msi-x vector resourceah$]h&]uh1jGhj$hhhhhKubjH)}(hhh](jM)}(hPCI Memory/IO Mapped Regionsh]hPCI Memory/IO Mapped Regions}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjxhhhhhKubj})}(hX{Service drivers for PCI Express Power Management (PME), Advanced Error Reporting (AER), Hot-Plug (HP) and Virtual Channel (VC) access PCI configuration space on the PCI Express port. In all cases the registers accessed are independent of each other. This patch assumes that all service drivers will be well behaved and not overwrite other service driver's configuration settings.h]hX}Service drivers for PCI Express Power Management (PME), Advanced Error Reporting (AER), Hot-Plug (HP) and Virtual Channel (VC) access PCI configuration space on the PCI Express port. In all cases the registers accessed are independent of each other. This patch assumes that all service drivers will be well behaved and not overwrite other service driver’s configuration settings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjxhhubeh}(h]pci-memory-io-mapped-regionsah ]h"]pci memory/io mapped regionsah$]h&]uh1jGhj$hhhhhKubjH)}(hhh](jM)}(hPCI Config Registersh]hPCI Config Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj})}(hX|Each service driver runs its PCI config operations on its own capability structure except the PCI Express capability structure, that is shared between many drivers including the service drivers. RMW Capability accessors (pcie_capability_clear_and_set_word(), pcie_capability_set_word(), and pcie_capability_clear_word()) protect a selected set of PCI Express Capability Registers:h]hX|Each service driver runs its PCI config operations on its own capability structure except the PCI Express capability structure, that is shared between many drivers including the service drivers. RMW Capability accessors (pcie_capability_clear_and_set_word(), pcie_capability_set_word(), and pcie_capability_clear_word()) protect a selected set of PCI Express Capability Registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubjv)}(hhh](j{)}(hLink Control Registerh]j})}(hjh]hLink Control Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubah}(h]h ]h"]h$]h&]uh1jzhjhhhhhNubj{)}(hRoot Control Registerh]j})}(hjh]hRoot Control Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubah}(h]h ]h"]h$]h&]uh1jzhjhhhhhNubj{)}(hLink Control 2 Register h]j})}(hLink Control 2 Registerh]hLink Control 2 Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubah}(h]h ]h"]h$]h&]uh1jzhjhhhhhNubeh}(h]h ]h"]h$]h&]j*uh1juhhhKhjhhubj})}(hAny change to those registers should be performed using RMW accessors to avoid problems due to concurrent updates. For the up-to-date list of protected registers, see pcie_capability_clear_and_set_word().h]hAny change to those registers should be performed using RMW accessors to avoid problems due to concurrent updates. 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