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field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hj| h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1jz hjw h³hÇh´K ubhŒ
field_body”“”)”}”(hŒ.Tom L Nguyen tom.l.nguyen@intel.com 11/03/2004”h]”hŒ paragraph”“”)”}”(hjŽ h]”(hŒ
Tom L Nguyen ”…””}”(hj’ h²hh³Nh´NubhŒ reference”“”)”}”(hŒtom.l.nguyen@intel.com”h]”hŒtom.l.nguyen@intel.com”…””}”(hj› h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”Œrefuri”Œ mailto:tom.l.nguyen@intel.com”uh1j™ hj’ ubhŒ 11/03/2004”…””}”(hj’ h²hh³Nh´Nubeh }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KhjŒ ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŠ hjw ubeh }”(h ]”h ]”h"]”h$]”h&]”uh1ju h³hÇh´Khjr h²hubjv )”}”(hhh]”(j{ )”}”(hŒ Copyright”h]”hŒ Copyright”…””}”(hjÄ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1jz hjÁ h³hÇh´K ubj‹ )”}”(hŒ |copy| 2004 Intel Corporation
”h]”j‘ )”}”(hŒ |copy| 2004 Intel Corporation”h]”(hŒÂ©”…””}”(hjÖ h²hh³Nh´NubhŒ 2004 Intel Corporation”…””}”(hjÖ h²hh³Nh´Nubeh }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K hjÒ ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŠ hjÁ ubeh }”(h ]”h ]”h"]”h$]”h&]”uh1ju h³hÇh´K hjr h²hubeh }”(h ]”h ]”h"]”h$]”h&]”uh1jp hj] h²hh³hÇh´Kubj\ )”}”(hhh]”(ja )”}”(hŒAbout this guide”h]”hŒAbout this guide”…””}”(hjý h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hjú h²hh³hÇh´K ubj‘ )”}”(hŒ½This guide describes the basics of the PCI Express Port Bus driver
and provides information on how to enable the service drivers to
register/unregister with the PCI Express Port Bus Driver.”h]”hŒ½This guide describes the basics of the PCI Express Port Bus driver
and provides information on how to enable the service drivers to
register/unregister with the PCI Express Port Bus Driver.”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Khjú h²hubeh }”(h ]”Œabout-this-guide”ah ]”h"]”Œabout this guide”ah$]”h&]”uh1j[ hj] h²hh³hÇh´K ubj\ )”}”(hhh]”(ja )”}”(hŒ'What is the PCI Express Port Bus Driver”h]”hŒ'What is the PCI Express Port Bus Driver”…””}”(hj$ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj! h²hh³hÇh´Kubj‘ )”}”(hXC A PCI Express Port is a logical PCI-PCI Bridge structure. There
are two types of PCI Express Port: the Root Port and the Switch
Port. The Root Port originates a PCI Express link from a PCI Express
Root Complex and the Switch Port connects PCI Express links to
internal logical PCI buses. The Switch Port, which has its secondary
bus representing the switch's internal routing logic, is called the
switch's Upstream Port. The switch's Downstream Port is bridging from
switch's internal routing bus to a bus representing the downstream
PCI Express link from the PCI Express Switch.”h]”hXK A PCI Express Port is a logical PCI-PCI Bridge structure. There
are two types of PCI Express Port: the Root Port and the Switch
Port. The Root Port originates a PCI Express link from a PCI Express
Root Complex and the Switch Port connects PCI Express links to
internal logical PCI buses. The Switch Port, which has its secondary
bus representing the switch’s internal routing logic, is called the
switch’s Upstream Port. The switch’s Downstream Port is bridging from
switch’s internal routing bus to a bus representing the downstream
PCI Express link from the PCI Express Switch.”…””}”(hj2 h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Khj! h²hubj‘ )”}”(hXº A PCI Express Port can provide up to four distinct functions,
referred to in this document as services, depending on its port type.
PCI Express Port's services include native hotplug support (HP),
power management event support (PME), advanced error reporting
support (AER), and virtual channel support (VC). These services may
be handled by a single complex driver or be individually distributed
and handled by corresponding service drivers.”h]”hX¼ A PCI Express Port can provide up to four distinct functions,
referred to in this document as services, depending on its port type.
PCI Express Port’s services include native hotplug support (HP),
power management event support (PME), advanced error reporting
support (AER), and virtual channel support (VC). These services may
be handled by a single complex driver or be individually distributed
and handled by corresponding service drivers.”…””}”(hj@ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K hj! h²hubeh }”(h ]”Œ'what-is-the-pci-express-port-bus-driver”ah ]”h"]”Œ'what is the pci express port bus driver”ah$]”h&]”uh1j[ hj] h²hh³hÇh´Kubj\ )”}”(hhh]”(ja )”}”(hŒ(Why use the PCI Express Port Bus Driver?”h]”hŒ(Why use the PCI Express Port Bus Driver?”…””}”(hjY h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hjV h²hh³hÇh´K)ubj‘ )”}”(hXã In existing Linux kernels, the Linux Device Driver Model allows a
physical device to be handled by only a single driver. The PCI
Express Port is a PCI-PCI Bridge device with multiple distinct
services. To maintain a clean and simple solution each service
may have its own software service driver. In this case several
service drivers will compete for a single PCI-PCI Bridge device.
For example, if the PCI Express Root Port native hotplug service
driver is loaded first, it claims a PCI-PCI Bridge Root Port. The
kernel therefore does not load other service drivers for that Root
Port. In other words, it is impossible to have multiple service
drivers load and run on a PCI-PCI Bridge device simultaneously
using the current driver model.”h]”hXã In existing Linux kernels, the Linux Device Driver Model allows a
physical device to be handled by only a single driver. The PCI
Express Port is a PCI-PCI Bridge device with multiple distinct
services. To maintain a clean and simple solution each service
may have its own software service driver. In this case several
service drivers will compete for a single PCI-PCI Bridge device.
For example, if the PCI Express Root Port native hotplug service
driver is loaded first, it claims a PCI-PCI Bridge Root Port. The
kernel therefore does not load other service drivers for that Root
Port. In other words, it is impossible to have multiple service
drivers load and run on a PCI-PCI Bridge device simultaneously
using the current driver model.”…””}”(hjg h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K+hjV h²hubj‘ )”}”(hXE To enable multiple service drivers running simultaneously requires
having a PCI Express Port Bus driver, which manages all populated
PCI Express Ports and distributes all provided service requests
to the corresponding service drivers as required. Some key
advantages of using the PCI Express Port Bus driver are listed below:”h]”hXE To enable multiple service drivers running simultaneously requires
having a PCI Express Port Bus driver, which manages all populated
PCI Express Ports and distributes all provided service requests
to the corresponding service drivers as required. Some key
advantages of using the PCI Express Port Bus driver are listed below:”…””}”(hju h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K8hjV h²hubhŒ block_quote”“”)”}”(hXU - Allow multiple service drivers to run simultaneously on
a PCI-PCI Bridge Port device.
- Allow service drivers implemented in an independent
staged approach.
- Allow one service driver to run on multiple PCI-PCI Bridge
Port devices.
- Manage and distribute resources of a PCI-PCI Bridge Port
device to requested service drivers.
”h]”hŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒVAllow multiple service drivers to run simultaneously on
a PCI-PCI Bridge Port device.
”h]”j‘ )”}”(hŒUAllow multiple service drivers to run simultaneously on
a PCI-PCI Bridge Port device.”h]”hŒUAllow multiple service drivers to run simultaneously on
a PCI-PCI Bridge Port device.”…””}”(hj” h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K>hj ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hj‹ ubj )”}”(hŒEAllow service drivers implemented in an independent
staged approach.
”h]”j‘ )”}”(hŒDAllow service drivers implemented in an independent
staged approach.”h]”hŒDAllow service drivers implemented in an independent
staged approach.”…””}”(hj¬ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KAhj¨ ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hj‹ ubj )”}”(hŒIAllow one service driver to run on multiple PCI-PCI Bridge
Port devices.
”h]”j‘ )”}”(hŒHAllow one service driver to run on multiple PCI-PCI Bridge
Port devices.”h]”hŒHAllow one service driver to run on multiple PCI-PCI Bridge
Port devices.”…””}”(hjÄ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KDhjÀ ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hj‹ ubj )”}”(hŒ^Manage and distribute resources of a PCI-PCI Bridge Port
device to requested service drivers.
”h]”j‘ )”}”(hŒ]Manage and distribute resources of a PCI-PCI Bridge Port
device to requested service drivers.”h]”hŒ]Manage and distribute resources of a PCI-PCI Bridge Port
device to requested service drivers.”…””}”(hjÜ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KGhjØ ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hj‹ ubeh }”(h ]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j‰ h³hÇh´K>hj… ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jƒ h³hÇh´K>hjV h²hubeh }”(h ]”Œ'why-use-the-pci-express-port-bus-driver”ah ]”h"]”Œ(why use the pci express port bus driver?”ah$]”h&]”uh1j[ hj] h²hh³hÇh´K)ubj\ )”}”(hhh]”(ja )”}”(hŒ?Configuring the PCI Express Port Bus Driver vs. Service Drivers”h]”hŒ?Configuring the PCI Express Port Bus Driver vs. Service Drivers”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj h²hh³hÇh´KKubj\ )”}”(hhh]”(ja )”}”(hŒAIncluding the PCI Express Port Bus Driver Support into the Kernel”h]”hŒAIncluding the PCI Express Port Bus Driver Support into the Kernel”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj h²hh³hÇh´KNubj‘ )”}”(hX Including the PCI Express Port Bus driver depends on whether the PCI
Express support is included in the kernel config. The kernel will
automatically include the PCI Express Port Bus driver as a kernel
driver when the PCI Express support is enabled in the kernel.”h]”hX Including the PCI Express Port Bus driver depends on whether the PCI
Express support is included in the kernel config. The kernel will
automatically include the PCI Express Port Bus driver as a kernel
driver when the PCI Express support is enabled in the kernel.”…””}”(hj( h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KPhj h²hubeh }”(h ]”ŒAincluding-the-pci-express-port-bus-driver-support-into-the-kernel”ah ]”h"]”ŒAincluding the pci express port bus driver support into the kernel”ah$]”h&]”uh1j[ hj h²hh³hÇh´KNubj\ )”}”(hhh]”(ja )”}”(hŒ Enabling Service Driver Support”h]”hŒ Enabling Service Driver Support”…””}”(hjA h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj> h²hh³hÇh´KVubj‘ )”}”(hXŸ PCI device drivers are implemented based on Linux Device Driver Model.
All service drivers are PCI device drivers. As discussed above, it is
impossible to load any service driver once the kernel has loaded the
PCI Express Port Bus Driver. To meet the PCI Express Port Bus Driver
Model requires some minimal changes on existing service drivers that
imposes no impact on the functionality of existing service drivers.”h]”hXŸ PCI device drivers are implemented based on Linux Device Driver Model.
All service drivers are PCI device drivers. As discussed above, it is
impossible to load any service driver once the kernel has loaded the
PCI Express Port Bus Driver. To meet the PCI Express Port Bus Driver
Model requires some minimal changes on existing service drivers that
imposes no impact on the functionality of existing service drivers.”…””}”(hjO h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KXhj> h²hubj‘ )”}”(hXÇ A service driver is required to use the two APIs shown below to
register its service with the PCI Express Port Bus driver (see
section 5.2.1 & 5.2.2). It is important that a service driver
initializes the pcie_port_service_driver data structure, included in
header file /include/linux/pcieport_if.h, before calling these APIs.
Failure to do so will result an identity mismatch, which prevents
the PCI Express Port Bus driver from loading a service driver.”h]”hXÇ A service driver is required to use the two APIs shown below to
register its service with the PCI Express Port Bus driver (see
section 5.2.1 & 5.2.2). It is important that a service driver
initializes the pcie_port_service_driver data structure, included in
header file /include/linux/pcieport_if.h, before calling these APIs.
Failure to do so will result an identity mismatch, which prevents
the PCI Express Port Bus driver from loading a service driver.”…””}”(hj] h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K_hj> h²hubj\ )”}”(hhh]”(ja )”}”(hŒpcie_port_service_register”h]”hŒpcie_port_service_register”…””}”(hjn h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hjk h²hh³hÇh´KhubhŒ
literal_block”“”)”}”(hŒDint pcie_port_service_register(struct pcie_port_service_driver *new)”h]”hŒDint pcie_port_service_register(struct pcie_port_service_driver *new)”…””}”hj~ sbah }”(h ]”h ]”h"]”h$]”h&]”hÅhÆuh1j| h³hÇh´Kkhjk h²hubj‘ )”}”(hXP This API replaces the Linux Driver Model's pci_register_driver API. A
service driver should always calls pcie_port_service_register at
module init. Note that after service driver being loaded, calls
such as pci_enable_device(dev) and pci_set_master(dev) are no longer
necessary since these calls are executed by the PCI Port Bus driver.”h]”hXR This API replaces the Linux Driver Model’s pci_register_driver API. A
service driver should always calls pcie_port_service_register at
module init. Note that after service driver being loaded, calls
such as pci_enable_device(dev) and pci_set_master(dev) are no longer
necessary since these calls are executed by the PCI Port Bus driver.”…””}”(hjŒ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Kmhjk h²hubeh }”(h ]”Œpcie-port-service-register”ah ]”h"]”Œpcie_port_service_register”ah$]”h&]”uh1j[ hj> h²hh³hÇh´Khubj\ )”}”(hhh]”(ja )”}”(hŒ pcie_port_service_unregister”h]”hŒ pcie_port_service_unregister”…””}”(hj¥ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj¢ h²hh³hÇh´Ktubj} )”}”(hŒGvoid pcie_port_service_unregister(struct pcie_port_service_driver *new)”h]”hŒGvoid pcie_port_service_unregister(struct pcie_port_service_driver *new)”…””}”hj³ sbah }”(h ]”h ]”h"]”h$]”h&]”hÅhÆuh1j| h³hÇh´Kwhj¢ h²hubj‘ )”}”(hŒpcie_port_service_unregister replaces the Linux Driver Model's
pci_unregister_driver. It's always called by service driver when a
module exits.”h]”hŒ“pcie_port_service_unregister replaces the Linux Driver Model’s
pci_unregister_driver. It’s always called by service driver when a
module exits.”…””}”(hjÁ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Kyhj¢ h²hubeh }”(h ]”Œ pcie-port-service-unregister”ah ]”h"]”Œ pcie_port_service_unregister”ah$]”h&]”uh1j[ hj> h²hh³hÇh´Ktubj\ )”}”(hhh]”(ja )”}”(hŒ Sample Code”h]”hŒ Sample Code”…””}”(hjÚ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj× h²hh³hÇh´K~ubj‘ )”}”(hŒ\Below is sample service driver code to initialize the port service
driver data structure.
::”h]”hŒYBelow is sample service driver code to initialize the port service
driver data structure.”…””}”(hjè h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K€hj× h²hubj} )”}”(hXæ static struct pcie_port_service_id service_id[] = { {
.vendor = PCI_ANY_ID,
.device = PCI_ANY_ID,
.port_type = PCIE_RC_PORT,
.service_type = PCIE_PORT_SERVICE_AER,
}, { /* end: all zeroes */ }
};
static struct pcie_port_service_driver root_aerdrv = {
.name = (char *)device_name,
.id_table = service_id,
.probe = aerdrv_load,
.remove = aerdrv_unload,
.suspend = aerdrv_suspend,
.resume = aerdrv_resume,
};”h]”hXæ static struct pcie_port_service_id service_id[] = { {
.vendor = PCI_ANY_ID,
.device = PCI_ANY_ID,
.port_type = PCIE_RC_PORT,
.service_type = PCIE_PORT_SERVICE_AER,
}, { /* end: all zeroes */ }
};
static struct pcie_port_service_driver root_aerdrv = {
.name = (char *)device_name,
.id_table = service_id,
.probe = aerdrv_load,
.remove = aerdrv_unload,
.suspend = aerdrv_suspend,
.resume = aerdrv_resume,
};”…””}”hjö sbah }”(h ]”h ]”h"]”h$]”h&]”hÅhÆuh1j| h³hÇh´K„hj× h²hubj‘ )”}”(hŒIBelow is a sample code for registering/unregistering a service
driver.
::”h]”hŒFBelow is a sample code for registering/unregistering a service
driver.”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K—hj× h²hubj} )”}”(hX] static int __init aerdrv_service_init(void)
{
int retval = 0;
retval = pcie_port_service_register(&root_aerdrv);
if (!retval) {
/*
* FIX ME
*/
}
return retval;
}
static void __exit aerdrv_service_exit(void)
{
pcie_port_service_unregister(&root_aerdrv);
}
module_init(aerdrv_service_init);
module_exit(aerdrv_service_exit);”h]”hX] static int __init aerdrv_service_init(void)
{
int retval = 0;
retval = pcie_port_service_register(&root_aerdrv);
if (!retval) {
/*
* FIX ME
*/
}
return retval;
}
static void __exit aerdrv_service_exit(void)
{
pcie_port_service_unregister(&root_aerdrv);
}
module_init(aerdrv_service_init);
module_exit(aerdrv_service_exit);”…””}”hj sbah }”(h ]”h ]”h"]”h$]”h&]”hÅhÆuh1j| h³hÇh´K›hj× h²hubeh }”(h ]”Œ sample-code”ah ]”h"]”Œ sample code”ah$]”h&]”uh1j[ hj> h²hh³hÇh´K~ubeh }”(h ]”Œ enabling-service-driver-support”ah ]”h"]”Œ enabling service driver support”ah$]”h&]”uh1j[ hj h²hh³hÇh´KVubeh }”(h ]”Œ>configuring-the-pci-express-port-bus-driver-vs-service-drivers”ah ]”h"]”Œ?configuring the pci express port bus driver vs. service drivers”ah$]”h&]”uh1j[ hj] h²hh³hÇh´KKubj\ )”}”(hhh]”(ja )”}”(hŒPossible Resource Conflicts”h]”hŒPossible Resource Conflicts”…””}”(hj; h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj8 h²hh³hÇh´K±ubj‘ )”}”(hŒ¦Since all service drivers of a PCI-PCI Bridge Port device are
allowed to run simultaneously, below lists a few of possible resource
conflicts with proposed solutions.”h]”hŒ¦Since all service drivers of a PCI-PCI Bridge Port device are
allowed to run simultaneously, below lists a few of possible resource
conflicts with proposed solutions.”…””}”(hjI h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K³hj8 h²hubj\ )”}”(hhh]”(ja )”}”(hŒ MSI and MSI-X Vector Resource”h]”hŒ MSI and MSI-X Vector Resource”…””}”(hjZ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hjW h²hh³hÇh´K¸ubj‘ )”}”(hX* Once MSI or MSI-X interrupts are enabled on a device, it stays in this
mode until they are disabled again. Since service drivers of the same
PCI-PCI Bridge port share the same physical device, if an individual
service driver enables or disables MSI/MSI-X mode it may result
unpredictable behavior.”h]”hX* Once MSI or MSI-X interrupts are enabled on a device, it stays in this
mode until they are disabled again. Since service drivers of the same
PCI-PCI Bridge port share the same physical device, if an individual
service driver enables or disables MSI/MSI-X mode it may result
unpredictable behavior.”…””}”(hjh h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KºhjW h²hubj‘ )”}”(hXT To avoid this situation all service drivers are not permitted to
switch interrupt mode on its device. The PCI Express Port Bus driver
is responsible for determining the interrupt mode and this should be
transparent to service drivers. Service drivers need to know only
the vector IRQ assigned to the field irq of struct pcie_device, which
is passed in when the PCI Express Port Bus driver probes each service
driver. Service drivers should use (struct pcie_device*)dev->irq to
call request_irq/free_irq. In addition, the interrupt mode is stored
in the field interrupt_mode of struct pcie_device.”h]”hXT To avoid this situation all service drivers are not permitted to
switch interrupt mode on its device. The PCI Express Port Bus driver
is responsible for determining the interrupt mode and this should be
transparent to service drivers. Service drivers need to know only
the vector IRQ assigned to the field irq of struct pcie_device, which
is passed in when the PCI Express Port Bus driver probes each service
driver. Service drivers should use (struct pcie_device*)dev->irq to
call request_irq/free_irq. In addition, the interrupt mode is stored
in the field interrupt_mode of struct pcie_device.”…””}”(hjv h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KÀhjW h²hubeh }”(h ]”Œ msi-and-msi-x-vector-resource”ah ]”h"]”Œ msi and msi-x vector resource”ah$]”h&]”uh1j[ hj8 h²hh³hÇh´K¸ubj\ )”}”(hhh]”(ja )”}”(hŒ PCI Memory/IO Mapped Regions”h]”hŒ PCI Memory/IO Mapped Regions”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hjŒ h²hh³hÇh´KËubj‘ )”}”(hX{ Service drivers for PCI Express Power Management (PME), Advanced
Error Reporting (AER), Hot-Plug (HP) and Virtual Channel (VC) access
PCI configuration space on the PCI Express port. In all cases the
registers accessed are independent of each other. This patch assumes
that all service drivers will be well behaved and not overwrite
other service driver's configuration settings.”h]”hX} Service drivers for PCI Express Power Management (PME), Advanced
Error Reporting (AER), Hot-Plug (HP) and Virtual Channel (VC) access
PCI configuration space on the PCI Express port. In all cases the
registers accessed are independent of each other. This patch assumes
that all service drivers will be well behaved and not overwrite
other service driver’s configuration settings.”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KÍhjŒ h²hubeh }”(h ]”Œ pci-memory-io-mapped-regions”ah ]”h"]”Œ pci memory/io mapped regions”ah$]”h&]”uh1j[ hj8 h²hh³hÇh´KËubj\ )”}”(hhh]”(ja )”}”(hŒPCI Config Registers”h]”hŒPCI Config Registers”…””}”(hj¶ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j` hj³ h²hh³hÇh´KÕubj‘ )”}”(hX| Each service driver runs its PCI config operations on its own
capability structure except the PCI Express capability structure,
that is shared between many drivers including the service drivers.
RMW Capability accessors (pcie_capability_clear_and_set_word(),
pcie_capability_set_word(), and pcie_capability_clear_word()) protect
a selected set of PCI Express Capability Registers:”h]”hX| Each service driver runs its PCI config operations on its own
capability structure except the PCI Express capability structure,
that is shared between many drivers including the service drivers.
RMW Capability accessors (pcie_capability_clear_and_set_word(),
pcie_capability_set_word(), and pcie_capability_clear_word()) protect
a selected set of PCI Express Capability Registers:”…””}”(hjÄ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´K×hj³ h²hubjŠ )”}”(hhh]”(j )”}”(hŒLink Control Register”h]”j‘ )”}”(hj× h]”hŒLink Control Register”…””}”(hjÙ h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´KÞhjÕ ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hjÒ h²hh³hÇh´Nubj )”}”(hŒRoot Control Register”h]”j‘ )”}”(hjî h]”hŒRoot Control Register”…””}”(hjð h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Kßhjì ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hjÒ h²hh³hÇh´Nubj )”}”(hŒLink Control 2 Register
”h]”j‘ )”}”(hŒLink Control 2 Register”h]”hŒLink Control 2 Register”…””}”(hj h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Kàhj ubah }”(h ]”h ]”h"]”h$]”h&]”uh1jŽ hjÒ h²hh³hÇh´Nubeh }”(h ]”h ]”h"]”h$]”h&]”jö Œ*”uh1j‰ h³hÇh´KÞhj³ h²hubj‘ )”}”(hŒÌAny change to those registers should be performed using RMW accessors to
avoid problems due to concurrent updates. For the up-to-date list of
protected registers, see pcie_capability_clear_and_set_word().”h]”hŒÌAny change to those registers should be performed using RMW accessors to
avoid problems due to concurrent updates. For the up-to-date list of
protected registers, see pcie_capability_clear_and_set_word().”…””}”(hj" h²hh³Nh´Nubah }”(h ]”h ]”h"]”h$]”h&]”uh1j h³hÇh´Kâhj³ h²hubeh }”(h ]”Œpci-config-registers”ah ]”h"]”Œpci config registers”ah$]”h&]”uh1j[ hj8 h²hh³hÇh´KÕubeh }”(h ]”Œpossible-resource-conflicts”ah ]”h"]”Œpossible resource conflicts”ah$]”h&]”uh1j[ hj] h²hh³hÇh´K±ubeh }”(h ]”Œ+the-pci-express-port-bus-driver-guide-howto”ah ]”h"]”Œ+the pci express port bus driver guide howto”ah$]”h&]”uh1j[ hhh²hh³hÇh´Kubeh }”(h ]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(j` NŒ generator”NŒ datestamp”NŒ source_link”NŒ
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_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒ trim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œ character_level_inline_markup”‰Œdoctitle_xform”‰Œ
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j j j j+ j j: j. jI j= jX jL uŒsubstitution_names”}”(Œamp”hóŒapos”j Œast”j Œbrvbar”j Œbsol”j/ Œcent”j> Œcolon”jM Œcomma”j\ Œcommat”jk Œcopy”jz Œcurren”j‰ Œdarr”j˜ Œdeg”j§ Œdivide”j¶ Œdollar”jÅ Œequals”jÔ Œexcl”jã Œfrac12”jò Œfrac14”j Œfrac18”j Œfrac34”j Œfrac38”j. Œfrac58”j= Œfrac78”jL Œgt”j[ Œhalf”jj Œhorbar”jy Œhyphen”jˆ Œiexcl”j— Œiquest”j¦ Œlaquo”jµ Œlarr”jÄ Œlcub”jÓ Œldquo”jâ Œlowbar”jñ Œlpar”j Œlsqb”j Œlsquo”j Œlt”j- Œmicro”j< Œmiddot”jK Œnbsp”jZ Œnot”ji Œnum”jx Œohm”j‡ Œordf”j– Œordm”j¥ Œpara”j´ Œpercnt”jà Œperiod”jÒ Œplus”já Œplusmn”jð Œpound”jÿ Œquest”j Œquot”j Œraquo”j, Œrarr”j; Œrcub”jJ Œrdquo”jY Œreg”jh Œrpar”jw Œrsqb”j† Œrsquo”j• Œsect”j¤ Œsemi”j³ Œshy”j Œsol”jÑ Œsung”jà Œsup1”jï Œsup2”jþ Œsup3”j
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footnote_refs”}”Œ
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id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ#Documentation/PCI/pciebus-howto.rst”(NNNNt”†”aŒ
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