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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h;The PCI Express Advanced Error Reporting Driver Guide HOWTOh]h;The PCI Express Advanced Error Reporting Driver Guide HOWTO}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(hAuthorsh]hAuthors}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjchhhKubh field_body)}(hR- T. Long Nguyen - Yanmin Zhang h]h bullet_list)}(hhh](h list_item)}(h'T. Long Nguyen h]henumerated_list)}(hhh]j)}(h$Long Nguyen h]h paragraph)}(hjh](h Long Nguyen <}(hjhhhNhNubh reference)}(htom.l.nguyen@intel.comh]htom.l.nguyen@intel.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:tom.l.nguyen@intel.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]enumtype upperalphaprefixhsuffix.startKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(h&Yanmin Zhang h]j)}(h%Yanmin Zhang h](hYanmin Zhang <}(hjhhhNhNubj)}(hyanmin.zhang@intel.comh]hyanmin.zhang@intel.com}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:yanmin.zhang@intel.comuh1jhjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]bullet-uh1j|hhhKhjxubah}(h]h ]h"]h$]h&]uh1jvhjcubeh}(h]h ]h"]h$]h&]uh1jahhhKhj^hhubjb)}(hhh](jg)}(h Copyrighth]h Copyright}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhj hhhKubjw)}(h|copy| 2006 Intel Corporation h]j)}(h|copy| 2006 Intel Corporationh](h©}(hj"hhhNhNubh 2006 Intel Corporation}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK hjubah}(h]h ]h"]h$]h&]uh1jvhj ubeh}(h]h ]h"]h$]h&]uh1jahhhK hj^hhubeh}(h]h ]h"]h$]h&]uh1j\hjIhhhhhKubjH)}(hhh](jM)}(hOverviewh]hOverview}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjFhhhhhKubjH)}(hhh](jM)}(hAbout this guideh]hAbout this guide}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjWhhhhhKubj)}(hThis guide describes the basics of the PCI Express (PCIe) Advanced Error Reporting (AER) driver and provides information on how to use it, as well as how to enable the drivers of Endpoint devices to conform with the PCIe AER driver.h]hThis guide describes the basics of the PCI Express (PCIe) Advanced Error Reporting (AER) driver and provides information on how to use it, as well as how to enable the drivers of Endpoint devices to conform with the PCIe AER driver.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjWhhubeh}(h]about-this-guideah ]h"]about this guideah$]h&]uh1jGhjFhhhhhKubjH)}(hhh](jM)}(hWhat is the PCIe AER Driver?h]hWhat is the PCIe AER Driver?}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj~hhhhhKubj)}(hXPCIe error signaling can occur on the PCIe link itself or on behalf of transactions initiated on the link. PCIe defines two error reporting paradigms: the baseline capability and the Advanced Error Reporting capability. The baseline capability is required of all PCIe components providing a minimum defined set of error reporting requirements. Advanced Error Reporting capability is implemented with a PCIe Advanced Error Reporting extended capability structure providing more robust error reporting.h]hXPCIe error signaling can occur on the PCIe link itself or on behalf of transactions initiated on the link. PCIe defines two error reporting paradigms: the baseline capability and the Advanced Error Reporting capability. The baseline capability is required of all PCIe components providing a minimum defined set of error reporting requirements. Advanced Error Reporting capability is implemented with a PCIe Advanced Error Reporting extended capability structure providing more robust error reporting.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj~hhubj)}(hThe PCIe AER driver provides the infrastructure to support PCIe Advanced Error Reporting capability. The PCIe AER driver provides three basic functions:h]hThe PCIe AER driver provides the infrastructure to support PCIe Advanced Error Reporting capability. The PCIe AER driver provides three basic functions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK%hj~hhubh block_quote)}(h- Gathers the comprehensive error information if errors occurred. - Reports error to the users. - Performs error recovery actions. h]j})}(hhh](j)}(h?Gathers the comprehensive error information if errors occurred.h]j)}(hjh]h?Gathers the comprehensive error information if errors occurred.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK)hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hReports error to the users.h]j)}(hjh]hReports error to the users.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h!Performs error recovery actions. h]j)}(h Performs error recovery actions.h]h Performs error recovery actions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1j|hhhK)hjubah}(h]h ]h"]h$]h&]uh1jhhhK)hj~hhubj)}(hZThe AER driver only attaches to Root Ports and RCECs that support the PCIe AER capability.h]hZThe AER driver only attaches to Root Ports and RCECs that support the PCIe AER capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK-hj~hhubeh}(h]what-is-the-pcie-aer-driverah ]h"]what is the pcie aer driver?ah$]h&]uh1jGhjFhhhhhKubeh}(h]overviewah ]h"]overviewah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(h User Guideh]h User Guide}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj$hhhhhK2ubjH)}(hhh](jM)}(h6Include the PCIe AER Root Driver into the Linux Kernelh]h6Include the PCIe AER Root Driver into the Linux Kernel}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj5hhhhhK5ubj)}(hThe PCIe AER driver is a Root Port service driver attached via the PCIe Port Bus driver. If a user wants to use it, the driver must be compiled. It is enabled with CONFIG_PCIEAER, which depends on CONFIG_PCIEPORTBUS.h]hThe PCIe AER driver is a Root Port service driver attached via the PCIe Port Bus driver. If a user wants to use it, the driver must be compiled. It is enabled with CONFIG_PCIEAER, which depends on CONFIG_PCIEPORTBUS.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK7hj5hhubeh}(h]6include-the-pcie-aer-root-driver-into-the-linux-kernelah ]h"]6include the pcie aer root driver into the linux kernelah$]h&]uh1jGhj$hhhhhK5ubjH)}(hhh](jM)}(hLoad PCIe AER Root Driverh]hLoad PCIe AER Root Driver}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj\hhhhhK=ubj)}(hXSSome systems have AER support in firmware. Enabling Linux AER support at the same time the firmware handles AER would result in unpredictable behavior. Therefore, Linux does not handle AER events unless the firmware grants AER control to the OS via the ACPI _OSC method. See the PCI Firmware Specification for details regarding _OSC usage.h]hXSSome systems have AER support in firmware. Enabling Linux AER support at the same time the firmware handles AER would result in unpredictable behavior. Therefore, Linux does not handle AER events unless the firmware grants AER control to the OS via the ACPI _OSC method. See the PCI Firmware Specification for details regarding _OSC usage.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK?hj\hhubeh}(h]load-pcie-aer-root-driverah ]h"]load pcie aer root driverah$]h&]uh1jGhj$hhhhhK=ubjH)}(hhh](jM)}(hAER error outputh]hAER error output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKFubj)}(hXWhen a PCIe AER error is captured, an error message will be output to console. If it's a correctable error, it is output as an info message. Otherwise, it is printed as an error. So users could choose different log level to filter out correctable error messages.h]hXWhen a PCIe AER error is captured, an error message will be output to console. If it’s a correctable error, it is output as an info message. Otherwise, it is printed as an error. So users could choose different log level to filter out correctable error messages.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKHhjhhubj)}(hBelow shows an example::h]hBelow shows an example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKMhjhhubh literal_block)}(hX%0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID) 0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000 0000:50:00.0: [20] Unsupported Request (First) 0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100h]hX%0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID) 0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000 0000:50:00.0: [20] Unsupported Request (First) 0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKOhjhhubj)}(hIn the example, 'Requester ID' means the ID of the device that sent the error message to the Root Port. Please refer to PCIe specs for other fields.h]hIn the example, ‘Requester ID’ means the ID of the device that sent the error message to the Root Port. Please refer to PCIe specs for other fields.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKThjhhubeh}(h]aer-error-outputah ]h"]aer error outputah$]h&]uh1jGhj$hhhhhKFubjH)}(hhh](jM)}(hAER Statistics / Countersh]hAER Statistics / Counters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKYubj)}(hWhen PCIe AER errors are captured, the counters / statistics are also exposed in the form of sysfs attributes which are documented at Documentation/ABI/testing/sysfs-bus-pci-devices-aer_statsh]hWhen PCIe AER errors are captured, the counters / statistics are also exposed in the form of sysfs attributes which are documented at Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK[hjhhubeh}(h]aer-statistics-countersah ]h"]aer statistics / countersah$]h&]uh1jGhj$hhhhhKYubeh}(h] user-guideah ]h"] user guideah$]h&]uh1jGhjIhhhhhK2ubjH)}(hhh](jM)}(hDeveloper Guideh]hDeveloper Guide}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhK`ubj)}(hCTo enable error recovery, a software driver must provide callbacks.h]hCTo enable error recovery, a software driver must provide callbacks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKbhjhhubj)}(hCTo support AER better, developers need to understand how AER works.h]hCTo support AER better, developers need to understand how AER works.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKdhjhhubj)}(hPCIe errors are classified into two types: correctable errors and uncorrectable errors. This classification is based on the impact of those errors, which may result in degraded performance or function failure.h]hPCIe errors are classified into two types: correctable errors and uncorrectable errors. This classification is based on the impact of those errors, which may result in degraded performance or function failure.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKfhjhhubj)}(hCorrectable errors pose no impacts on the functionality of the interface. The PCIe protocol can recover without any software intervention or any loss of data. These errors are detected and corrected by hardware.h]hCorrectable errors pose no impacts on the functionality of the interface. The PCIe protocol can recover without any software intervention or any loss of data. These errors are detected and corrected by hardware.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKkhjhhubj)}(hXUnlike correctable errors, uncorrectable errors impact functionality of the interface. Uncorrectable errors can cause a particular transaction or a particular PCIe link to be unreliable. Depending on those error conditions, uncorrectable errors are further classified into non-fatal errors and fatal errors. Non-fatal errors cause the particular transaction to be unreliable, but the PCIe link itself is fully functional. Fatal errors, on the other hand, cause the link to be unreliable.h]hXUnlike correctable errors, uncorrectable errors impact functionality of the interface. Uncorrectable errors can cause a particular transaction or a particular PCIe link to be unreliable. Depending on those error conditions, uncorrectable errors are further classified into non-fatal errors and fatal errors. Non-fatal errors cause the particular transaction to be unreliable, but the PCIe link itself is fully functional. Fatal errors, on the other hand, cause the link to be unreliable.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKphjhhubj)}(hXoWhen PCIe error reporting is enabled, a device will automatically send an error message to the Root Port above it when it captures an error. The Root Port, upon receiving an error reporting message, internally processes and logs the error message in its AER Capability structure. Error information being logged includes storing the error reporting agent's requestor ID into the Error Source Identification Registers and setting the error bits of the Root Error Status Register accordingly. If AER error reporting is enabled in the Root Error Command Register, the Root Port generates an interrupt when an error is detected.h]hXqWhen PCIe error reporting is enabled, a device will automatically send an error message to the Root Port above it when it captures an error. The Root Port, upon receiving an error reporting message, internally processes and logs the error message in its AER Capability structure. Error information being logged includes storing the error reporting agent’s requestor ID into the Error Source Identification Registers and setting the error bits of the Root Error Status Register accordingly. If AER error reporting is enabled in the Root Error Command Register, the Root Port generates an interrupt when an error is detected.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKyhjhhubj)}(hNote that the errors as described above are related to the PCIe hierarchy and links. These errors do not include any device specific errors because device specific errors will still get sent directly to the device driver.h]hNote that the errors as described above are related to the PCIe hierarchy and links. These errors do not include any device specific errors because device specific errors will still get sent directly to the device driver.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubjH)}(hhh](jM)}(hProvide callbacksh]hProvide callbacks}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjxhhhhhKubjH)}(hhh](jM)}(h&callback reset_link to reset PCIe linkh]h&callback reset_link to reset PCIe link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj)}(hX8This callback is used to reset the PCIe physical link when a fatal error happens. The Root Port AER service driver provides a default reset_link function, but different Upstream Ports might have different specifications to reset the PCIe link, so Upstream Port drivers may provide their own reset_link functions.h]hX8This callback is used to reset the PCIe physical link when a fatal error happens. The Root Port AER service driver provides a default reset_link function, but different Upstream Ports might have different specifications to reset the PCIe link, so Upstream Port drivers may provide their own reset_link functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hGSection 3.2.2.2 provides more detailed info on when to call reset_link.h]hGSection 3.2.2.2 provides more detailed info on when to call reset_link.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]&callback-reset-link-to-reset-pcie-linkah ]h"]&callback reset_link to reset pcie linkah$]h&]uh1jGhjxhhhhhKubjH)}(hhh](jM)}(hPCI error-recovery callbacksh]hPCI error-recovery callbacks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj)}(hThe PCIe AER Root driver uses error callbacks to coordinate with downstream device drivers associated with a hierarchy in question when performing error recovery actions.h]hThe PCIe AER Root driver uses error callbacks to coordinate with downstream device drivers associated with a hierarchy in question when performing error recovery actions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hXLData struct pci_driver has a pointer, err_handler, to point to pci_error_handlers who consists of a couple of callback function pointers. The AER driver follows the rules defined in pci-error-recovery.rst except PCIe-specific parts (e.g. reset_link). Please refer to pci-error-recovery.rst for detailed definitions of the callbacks.h]hXLData struct pci_driver has a pointer, err_handler, to point to pci_error_handlers who consists of a couple of callback function pointers. The AER driver follows the rules defined in pci-error-recovery.rst except PCIe-specific parts (e.g. reset_link). Please refer to pci-error-recovery.rst for detailed definitions of the callbacks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hEThe sections below specify when to call the error callback functions.h]hEThe sections below specify when to call the error callback functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]pci-error-recovery-callbacksah ]h"]pci error-recovery callbacksah$]h&]uh1jGhjxhhhhhKubjH)}(hhh](jM)}(hCorrectable errorsh]hCorrectable errors}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj)}(hX8Correctable errors pose no impacts on the functionality of the interface. The PCIe protocol can recover without any software intervention or any loss of data. These errors do not require any recovery actions. The AER driver clears the device's correctable error status register accordingly and logs these errors.h]hX:Correctable errors pose no impacts on the functionality of the interface. The PCIe protocol can recover without any software intervention or any loss of data. These errors do not require any recovery actions. The AER driver clears the device’s correctable error status register accordingly and logs these errors.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubeh}(h]correctable-errorsah ]h"]correctable errorsah$]h&]uh1jGhjxhhhhhKubjH)}(hhh](jM)}(h,Non-correctable (non-fatal and fatal) errorsh]h,Non-correctable (non-fatal and fatal) errors}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj( hhhhhKubj)}(hIf an error message indicates a non-fatal error, performing link reset at upstream is not required. The AER driver calls error_detected(dev, pci_channel_io_normal) to all drivers associated within a hierarchy in question. For example::h]hIf an error message indicates a non-fatal error, performing link reset at upstream is not required. The AER driver calls error_detected(dev, pci_channel_io_normal) to all drivers associated within a hierarchy in question. For example:}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj( hhubj)}(hCEndpoint <==> Downstream Port B <==> Upstream Port A <==> Root Porth]hCEndpoint <==> Downstream Port B <==> Upstream Port A <==> Root Port}hjG sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj( hhubj)}(hcIf Upstream Port A captures an AER error, the hierarchy consists of Downstream Port B and Endpoint.h]hcIf Upstream Port A captures an AER error, the hierarchy consists of Downstream Port B and Endpoint.}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj( hhubj)}(hA driver may return PCI_ERS_RESULT_CAN_RECOVER, PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on whether it can recover or the AER driver calls mmio_enabled as next.h]hA driver may return PCI_ERS_RESULT_CAN_RECOVER, PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on whether it can recover or the AER driver calls mmio_enabled as next.}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj( hhubj)}(hXzIf an error message indicates a fatal error, kernel will broadcast error_detected(dev, pci_channel_io_frozen) to all drivers within a hierarchy in question. Then, performing link reset at upstream is necessary. As different kinds of devices might use different approaches to reset link, AER port service driver is required to provide the function to reset link via callback parameter of pcie_do_recovery() function. If reset_link is not NULL, recovery function will use it to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes to mmio_enabled.h]hXzIf an error message indicates a fatal error, kernel will broadcast error_detected(dev, pci_channel_io_frozen) to all drivers within a hierarchy in question. Then, performing link reset at upstream is necessary. As different kinds of devices might use different approaches to reset link, AER port service driver is required to provide the function to reset link via callback parameter of pcie_do_recovery() function. If reset_link is not NULL, recovery function will use it to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes to mmio_enabled.}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj( hhubeh}(h]*non-correctable-non-fatal-and-fatal-errorsah ]h"],non-correctable (non-fatal and fatal) errorsah$]h&]uh1jGhjxhhhhhKubeh}(h]provide-callbacksah ]h"]provide callbacksah$]h&]uh1jGhjhhhhhKubjH)}(hhh](jM)}(hFrequent Asked Questionsh]hFrequent Asked Questions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubhdefinition_list)}(hhh](hdefinition_list_item)}(hQ: What happens if a PCIe device driver does not provide an error recovery handler (pci_driver->err_handler is equal to NULL)? h](hterm)}(hQ:h]hQ:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhKhj ubh definition)}(hhh]j)}(h{What happens if a PCIe device driver does not provide an error recovery handler (pci_driver->err_handler is equal to NULL)?h]h{What happens if a PCIe device driver does not provide an error recovery handler (pci_driver->err_handler is equal to NULL)?}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhKhj ubj )}(hA: The devices attached with the driver won't be recovered. If the error is fatal, kernel will print out warning messages. Please refer to section 3 for more information. h](j )}(hA:h]hA:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhKhj ubj )}(hhh]j)}(hThe devices attached with the driver won't be recovered. If the error is fatal, kernel will print out warning messages. Please refer to section 3 for more information.h]hThe devices attached with the driver won’t be recovered. If the error is fatal, kernel will print out warning messages. Please refer to section 3 for more information.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhKhj hhubj )}(hYQ: What happens if an upstream port service driver does not provide callback reset_link? h](j )}(hQ:h]hQ:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhKhj ubj )}(hhh]j)}(hUWhat happens if an upstream port service driver does not provide callback reset_link?h]hUWhat happens if an upstream port service driver does not provide callback reset_link?}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhKhj hhubj )}(h|A: Fatal error recovery will fail if the errors are reported by the upstream ports who are attached by the service driver. h](j )}(hA:h]hA:}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1j hhhKhj8 ubj )}(hhh]j)}(hwFatal error recovery will fail if the errors are reported by the upstream ports who are attached by the service driver.h]hwFatal error recovery will fail if the errors are reported by the upstream ports who are attached by the service driver.}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjJ ubah}(h]h ]h"]h$]h&]uh1j hj8 ubeh}(h]h ]h"]h$]h&]uh1j hhhKhj hhubeh}(h]h ]h"]h$]h&]uh1j hj hhhhhNubeh}(h]frequent-asked-questionsah ]h"]frequent asked questionsah$]h&]uh1jGhjhhhhhKubeh}(h]developer-guideah ]h"]developer guideah$]h&]uh1jGhjIhhhhhK`ubjH)}(hhh](jM)}(hSoftware error injectionh]hSoftware error injection}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj} hhhhhKubj)}(hDebugging PCIe AER error recovery code is quite difficult because it is hard to trigger real hardware errors. Software based error injection can be used to fake various kinds of PCIe errors.h]hDebugging PCIe AER error recovery code is quite difficult because it is hard to trigger real hardware errors. Software based error injection can be used to fake various kinds of PCIe errors.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubj)}(hFirst you should enable PCIe AER software error injection in kernel configuration, that is, following item should be in your .config.h]hFirst you should enable PCIe AER software error injection in kernel configuration, that is, following item should be in your .config.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubj)}(h2CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=mh]h2CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubj)}(hiAfter reboot with new kernel or insert the module, a device file named /dev/aer_inject should be created.h]hiAfter reboot with new kernel or insert the module, a device file named /dev/aer_inject should be created.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubj)}(hLThen, you need a user space tool named aer-inject, which can be gotten from:h]hLThen, you need a user space tool named aer-inject, which can be gotten from:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubj)}(h(https://github.com/intel/aer-inject.git h]j)}(h'https://github.com/intel/aer-inject.gith]j)}(hj h]h'https://github.com/intel/aer-inject.git}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurij uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubj)}(hRMore information about aer-inject can be found in the document in its source code.h]hRMore information about aer-inject can be found in the document in its source code.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj} hhubeh}(h]software-error-injectionah ]h"]software error injectionah$]h&]uh1jGhjIhhhhhKubeh}(h];the-pci-express-advanced-error-reporting-driver-guide-howtoah ]h"];the pci express advanced error reporting driver guide howtoah$]h&]uh1jGhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(jLN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj7 error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}(hhhhhhj jjjj*jj9j-jHj<jWjKjfjZjujijjxjjjjjjjjjjjjjjjjj jjjj)jj8j,jGj;jVjJjejYjtjhjjwjjjjjjjjjjjjjjjjj jjj j(jj7j+jFj:jUjIjdjXjsjgjjvjjjjjjjjjjjjjjjjj jjj j'jj6j*jEj9jTjHjcjWjrjfjjujjjjjjjjjjjjjjjjjjjj j&jj5j)jDj8usubstitution_names}(amphߌaposhasthbrvbarj bsoljcentj*colonj9commajHcommatjWcopyjfcurrenjudarrjdegjdividejdollarjequalsjexcljfrac12jfrac14jfrac18jfrac34j frac38jfrac58j)frac78j8gtjGhalfjVhorbarjehyphenjtiexcljiquestjlaquojlarrjlcubjldquojlowbarjlparjlsqbjlsquoj ltjmicroj(middotj7nbspjFnotjUnumjdohmjsordfjordmjparajpercntjperiodjplusjplusmnjpoundjquestjquotj raquojrarrj'rcubj6rdquojEregjTrparjcrsqbjrrsquojsectjsemijshyjsoljsungjsup1jsup2jsup3jtimesjtradejuarrj&verbarj5yenjDurefnames}refids}nameids}(j j j!jj{jxjjjjjYjVjj}jjjjjz jw j j jjjjj% j" j j jr jo j j u nametypes}(j j!j{jjjYjjjjz j jjj% j jr j uh}(j jIjjFjxjWjj~jj$jVj5j}j\jjjjjw jj jxjjjjj" j j j( jo j j j} u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]hsystem_message)}(hhh]j)}(h;Enumerated list start value not ordinal-1: "T" (ordinal 20)h]h?Enumerated list start value not ordinal-1: “T” (ordinal 20)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1j hjubatransform_messages] transformerN include_log]#Documentation/PCI/pcieaer-howto.rst(NNNNta decorationNhhub.