E`sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget2/translations/zh_CN/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/zh_TW/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/it_IT/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/ja_JP/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/ko_KR/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/pt_BR/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/sp_SP/PCI/endpoint/pci-test-functionmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhL/var/lib/git/docbuild/linux/Documentation/PCI/endpoint/pci-test-function.rsthKubhsection)}(hhh](htitle)}(hPCI Test Functionh]hPCI Test Function}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh field_list)}(hhh]hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(h'Kishon Vijay Abraham I h]h paragraph)}(h&Kishon Vijay Abraham I h](hKishon Vijay Abraham I <}(hhhhhNhNubh reference)}(h kishon@ti.comh]h kishon@ti.com}(hj hhhNhNubah}(h]h ]h"]h$]h&]refurimailto:kishon@ti.comuh1jhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hXTraditionally PCI RC has always been validated by using standard PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards. However with the addition of EP-core in linux kernel, it is possible to configure a PCI controller that can operate in EP mode to work as a test device.h]hXTraditionally PCI RC has always been validated by using standard PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards. However with the addition of EP-core in linux kernel, it is possible to configure a PCI controller that can operate in EP mode to work as a test device.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hThe PCI endpoint test device is a virtual device (defined in software) used to test the endpoint functionality and serve as a sample driver for other PCI endpoint devices (to use the EP framework).h]hThe PCI endpoint test device is a virtual device (defined in software) used to test the endpoint functionality and serve as a sample driver for other PCI endpoint devices (to use the EP framework).}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h9The PCI endpoint test device has the following registers:h]h9The PCI endpoint test device has the following registers:}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hX1) PCI_ENDPOINT_TEST_MAGIC 2) PCI_ENDPOINT_TEST_COMMAND 3) PCI_ENDPOINT_TEST_STATUS 4) PCI_ENDPOINT_TEST_SRC_ADDR 5) PCI_ENDPOINT_TEST_DST_ADDR 6) PCI_ENDPOINT_TEST_SIZE 7) PCI_ENDPOINT_TEST_CHECKSUM 8) PCI_ENDPOINT_TEST_IRQ_TYPE 9) PCI_ENDPOINT_TEST_IRQ_NUMBER h]henumerated_list)}(hhh](h list_item)}(hPCI_ENDPOINT_TEST_MAGICh]h)}(hjnh]hPCI_ENDPOINT_TEST_MAGIC}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjlubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_COMMANDh]h)}(hjh]hPCI_ENDPOINT_TEST_COMMAND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_STATUSh]h)}(hjh]hPCI_ENDPOINT_TEST_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_SRC_ADDRh]h)}(hjh]hPCI_ENDPOINT_TEST_SRC_ADDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_DST_ADDRh]h)}(hjh]hPCI_ENDPOINT_TEST_DST_ADDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_SIZEh]h)}(hjh]hPCI_ENDPOINT_TEST_SIZE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_CHECKSUMh]h)}(hjh]hPCI_ENDPOINT_TEST_CHECKSUM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_IRQ_TYPEh]h)}(hjh]hPCI_ENDPOINT_TEST_IRQ_TYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jjhjgubjk)}(hPCI_ENDPOINT_TEST_IRQ_NUMBER h]h)}(hPCI_ENDPOINT_TEST_IRQ_NUMBERh]hPCI_ENDPOINT_TEST_IRQ_NUMBER}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubah}(h]h ]h"]h$]h&]uh1jjhjgubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1jehjaubah}(h]h ]h"]h$]h&]uh1j_hhhKhhhhubh bullet_list)}(hhh]jk)}(hPCI_ENDPOINT_TEST_MAGIC h]h)}(hPCI_ENDPOINT_TEST_MAGICh]hPCI_ENDPOINT_TEST_MAGIC}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubah}(h]h ]h"]h$]h&]uh1jjhjOhhhhhNubah}(h]h ]h"]h$]h&]bullet*uh1jMhhhKhhhhubh)}(hzThis register will be used to test BAR0. A known pattern will be written and read back from MAGIC register to verify BAR0.h]hzThis register will be used to test BAR0. A known pattern will be written and read back from MAGIC register to verify BAR0.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hhhhubjN)}(hhh]jk)}(hPCI_ENDPOINT_TEST_COMMAND h]h)}(hPCI_ENDPOINT_TEST_COMMANDh]hPCI_ENDPOINT_TEST_COMMAND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubah}(h]h ]h"]h$]h&]jpjquh1jMhhhK$hhhhubh)}(hmThis register will be used by the host driver to indicate the function that the endpoint device must perform.h]hmThis register will be used by the host driver to indicate the function that the endpoint device must perform.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK@uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hBitfieldh]hBitfield}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(hBit 0h]hBit 0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hraise legacy IRQh]hraise legacy IRQ}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 1h]hBit 1}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(h raise MSI IRQh]h raise MSI IRQ}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjkubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 2h]hBit 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hraise MSI-X IRQh]hraise MSI-X IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 3h]hBit 3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h'read command (read data from RC buffer)h]h'read command (read data from RC buffer)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 4h]hBit 4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h'write command (write data to RC buffer)h]h'write command (write data to RC buffer)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 5h]hBit 5}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj0ubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]h)}(h@copy command (copy data from one RC buffer to another RC buffer)h]h@copy command (copy data from one RC buffer to another RC buffer)}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjGubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhhhhhNubjN)}(hhh]jk)}(hPCI_ENDPOINT_TEST_STATUS h]h)}(hPCI_ENDPOINT_TEST_STATUSh]hPCI_ENDPOINT_TEST_STATUS}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjzubah}(h]h ]h"]h$]h&]uh1jjhjwhhhhhNubah}(h]h ]h"]h$]h&]jpjquh1jMhhhK4hhhhubh)}(h=This register reflects the status of the PCI endpoint device.h]h=This register reflects the status of the PCI endpoint device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hhhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h)}(hBitfieldh]hBitfield}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hBit 0h]hBit 0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h read successh]h read success}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 1h]hBit 1}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h write failh]h write fail}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 4h]hBit 4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h copy successh]h copy success}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 5h]hBit 5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h copy failh]h copy fail}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 6h]hBit 6}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(h IRQ raisedh]h IRQ raised}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjgubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 7h]hBit 7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hsource address is invalidh]hsource address is invalid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hBit 8h]hBit 8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hdestination address is invalidh]hdestination address is invalid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhhhhhNubjN)}(hhh]jk)}(hPCI_ENDPOINT_TEST_SRC_ADDR h]h)}(hPCI_ENDPOINT_TEST_SRC_ADDRh]hPCI_ENDPOINT_TEST_SRC_ADDR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjubah}(h]h ]h"]h$]h&]uh1jjhjhhhhhNubah}(h]h ]h"]h$]h&]jpjquh1jMhhhKFhhhhubh)}(hXThis register contains the source address (RC buffer address) for the COPY/READ command.h]hXThis register contains the source address (RC buffer address) for the COPY/READ command.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhhhhubjN)}(hhh]jk)}(hPCI_ENDPOINT_TEST_DST_ADDR h]h)}(hPCI_ENDPOINT_TEST_DST_ADDRh]hPCI_ENDPOINT_TEST_DST_ADDR}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhj7ubah}(h]h ]h"]h$]h&]uh1jjhj4hhhhhNubah}(h]h ]h"]h$]h&]jpjquh1jMhhhKKhhhhubh)}(h^This register contains the destination address (RC buffer address) for the COPY/WRITE command.h]h^This register contains the destination address (RC buffer address) for the COPY/WRITE command.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhhhhubjN)}(hhh]jk)}(hPCI_ENDPOINT_TEST_IRQ_TYPE h]h)}(hPCI_ENDPOINT_TEST_IRQ_TYPEh]hPCI_ENDPOINT_TEST_IRQ_TYPE}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjfubah}(h]h ]h"]h$]h&]uh1jjhjchhhhhNubah}(h]h ]h"]h$]h&]jpjquh1jMhhhKPhhhhubh)}(h}This register contains the interrupt type (Legacy/MSI) triggered for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.h]h}This register contains the interrupt type (Legacy/MSI) triggered for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhhhhubh)}(hPossible types:h]hPossible types:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhhhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hLegacyh]hLegacy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h0h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMSIh]hMSI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMSI-Xh]hMSI-X}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhj.ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh]h)}(h2h]h2}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjEubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhhhhhNubjN)}(hhh]jk)}(hPCI_ENDPOINT_TEST_IRQ_NUMBER h]h)}(hPCI_ENDPOINT_TEST_IRQ_NUMBERh]hPCI_ENDPOINT_TEST_IRQ_NUMBER}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hjxubah}(h]h ]h"]h$]h&]uh1jjhjuhhhhhNubah}(h]h ]h"]h$]h&]jpjquh1jMhhhK]hhhhubh)}(h2This register contains the triggered ID interrupt.h]h2This register contains the triggered ID interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hhhhubh)}(hAdmissible values:h]hAdmissible values:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahhhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hLegacyh]hLegacy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hMSIh]hMSI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h [1 .. 32]h]h [1 .. 32]}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h 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