€•quŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ'/translations/zh_CN/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/zh_TW/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/it_IT/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ja_JP/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ko_KR/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/pt_BR/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/sp_SP/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³ŒA/var/lib/git/docbuild/linux/Documentation/PCI/boot-interrupts.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒBoot Interrupts”h]”hŒBoot Interrupts”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ field_list”“”)”}”(hhh]”hŒfield”“”)”}”(hhh]”(hŒ field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hhéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hçhhäh³hÇh´KubhŒ field_body”“”)”}”(hŒ0- Sean V Kelley ”h]”hŒ bullet_list”“”)”}”(hhh]”hŒ list_item”“”)”}”(hŒ.Sean V Kelley ”h]”hŒ paragraph”“”)”}”(hŒ-Sean V Kelley ”h]”(hŒSean V Kelley <”…””}”(hj h²hh³Nh´NubhŒ reference”“”)”}”(hŒsean.v.kelley@linux.intel.com”h]”hŒsean.v.kelley@linux.intel.com”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œ$mailto:sean.v.kelley@linux.intel.com”uh1jhj ubhŒ>”…””}”(hj h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhhÿubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1hýh³hÇh´Khhùubah}”(h]”h ]”h"]”h$]”h&]”uh1h÷hhäubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâh³hÇh´Khhßh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒOverview”h]”hŒOverview”…””}”(hjQh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjNh²hh³hÇh´K ubj )”}”(hXQOn PCI Express, interrupts are represented with either MSI or inbound interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a given Core IO converts the legacy interrupt messages from PCI Express to MSI interrupts. If the IO-APIC is disabled (via the mask bits in the IO-APIC table entries), the messages are routed to the legacy PCH. This in-band interrupt mechanism was traditionally necessary for systems that did not support the IO-APIC and for boot. Intel in the past has used the term "boot interrupts" to describe this mechanism. Further, the PCI Express protocol describes this in-band legacy wire-interrupt INTx mechanism for I/O devices to signal PCI-style level interrupts. The subsequent paragraphs describe problems with the Core IO handling of INTx message routing to the PCH and mitigation within BIOS and the OS.”h]”hXUOn PCI Express, interrupts are represented with either MSI or inbound interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a given Core IO converts the legacy interrupt messages from PCI Express to MSI interrupts. If the IO-APIC is disabled (via the mask bits in the IO-APIC table entries), the messages are routed to the legacy PCH. This in-band interrupt mechanism was traditionally necessary for systems that did not support the IO-APIC and for boot. Intel in the past has used the term “boot interrupts†to describe this mechanism. Further, the PCI Express protocol describes this in-band legacy wire-interrupt INTx mechanism for I/O devices to signal PCI-style level interrupts. The subsequent paragraphs describe problems with the Core IO handling of INTx message routing to the PCH and mitigation within BIOS and the OS.”…””}”(hj_h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K hjNh²hubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K ubhÉ)”}”(hhh]”(hÎ)”}”(hŒIssue”h]”hŒIssue”…””}”(hjxh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjuh²hh³hÇh´Kubj )”}”(hXÍWhen in-band legacy INTx messages are forwarded to the PCH, they in turn trigger a new interrupt for which the OS likely lacks a handler. When an interrupt goes unhandled over time, they are tracked by the Linux kernel as Spurious Interrupts. The IRQ will be disabled by the Linux kernel after it reaches a specific count with the error "nobody cared". This disabled IRQ now prevents valid usage by an existing interrupt which may happen to share the IRQ line::”h]”hXÐWhen in-band legacy INTx messages are forwarded to the PCH, they in turn trigger a new interrupt for which the OS likely lacks a handler. When an interrupt goes unhandled over time, they are tracked by the Linux kernel as Spurious Interrupts. The IRQ will be disabled by the Linux kernel after it reaches a specific count with the error “nobody caredâ€. This disabled IRQ now prevents valid usage by an existing interrupt which may happen to share the IRQ line:”…””}”(hj†h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Khjuh²hubhŒ literal_block”“”)”}”(hX{irq 19: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1 Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 Call Trace: ? dump_stack+0x46/0x5e ? __report_bad_irq+0x2e/0xb0 ? note_interrupt+0x242/0x290 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] ? handle_irq_event_percpu+0x55/0x70 ? handle_irq_event+0x4f/0x80 ? handle_fasteoi_irq+0x81/0x180 ? handle_irq+0x1c/0x30 ? do_IRQ+0x41/0xd0 ? common_interrupt+0x84/0x84 handlers: irq_default_primary_handler threaded usb_hcd_irq Disabling IRQ #19”h]”hX{irq 19: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1 Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 Call Trace: ? dump_stack+0x46/0x5e ? __report_bad_irq+0x2e/0xb0 ? note_interrupt+0x242/0x290 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] ? handle_irq_event_percpu+0x55/0x70 ? handle_irq_event+0x4f/0x80 ? handle_fasteoi_irq+0x81/0x180 ? handle_irq+0x1c/0x30 ? do_IRQ+0x41/0xd0 ? common_interrupt+0x84/0x84 handlers: irq_default_primary_handler threaded usb_hcd_irq Disabling IRQ #19”…””}”hj–sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j”h³hÇh´K%hjuh²hubeh}”(h]”Œissue”ah ]”h"]”Œissue”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Conditions”h]”hŒ Conditions”…””}”(hj¯h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¬h²hh³hÇh´K=ubj )”}”(hXûThe use of threaded interrupts is the most likely condition to trigger this problem today. Threaded interrupts may not be re-enabled after the IRQ handler wakes. These "one shot" conditions mean that the threaded interrupt needs to keep the interrupt line masked until the threaded handler has run. Especially when dealing with high data rate interrupts, the thread needs to run to completion; otherwise some handlers will end up in stack overflows since the interrupt of the issuing device is still active.”h]”hXÿThe use of threaded interrupts is the most likely condition to trigger this problem today. Threaded interrupts may not be re-enabled after the IRQ handler wakes. These “one shot†conditions mean that the threaded interrupt needs to keep the interrupt line masked until the threaded handler has run. Especially when dealing with high data rate interrupts, the thread needs to run to completion; otherwise some handlers will end up in stack overflows since the interrupt of the issuing device is still active.”…””}”(hj½h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K?hj¬h²hubeh}”(h]”Œ conditions”ah ]”h"]”Œ conditions”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K=ubhÉ)”}”(hhh]”(hÎ)”}”(hŒAffected Chipsets”h]”hŒAffected Chipsets”…””}”(hjÖh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÓh²hh³hÇh´KHubj )”}”(hŒëThe legacy interrupt forwarding mechanism exists today in a number of devices including but not limited to chipsets from AMD/ATI, Broadcom, and Intel. Changes made through the mitigations below have been applied to drivers/pci/quirks.c”h]”hŒëThe legacy interrupt forwarding mechanism exists today in a number of devices including but not limited to chipsets from AMD/ATI, Broadcom, and Intel. Changes made through the mitigations below have been applied to drivers/pci/quirks.c”…””}”(hjäh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KJhjÓh²hubj )”}”(hŒÃStarting with ICX there are no longer any IO-APICs in the Core IO's devices. IO-APIC is only in the PCH. Devices connected to the Core IO's PCIe Root Ports will use native MSI/MSI-X mechanisms.”h]”hŒÇStarting with ICX there are no longer any IO-APICs in the Core IO’s devices. IO-APIC is only in the PCH. Devices connected to the Core IO’s PCIe Root Ports will use native MSI/MSI-X mechanisms.”…””}”(hjòh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KOhjÓh²hubeh}”(h]”Œaffected-chipsets”ah ]”h"]”Œaffected chipsets”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KHubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Mitigations”h]”hŒ Mitigations”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´KTubj )”}”(hŒàThe mitigations take the form of PCI quirks. The preference has been to first identify and make use of a means to disable the routing to the PCH. In such a case a quirk to disable boot interrupt generation can be added. [1]_”h]”(hŒÜThe mitigations take the form of PCI quirks. The preference has been to first identify and make use of a means to disable the routing to the PCH. In such a case a quirk to disable boot interrupt generation can be added. ”…””}”(hjh²hh³Nh´NubhŒfootnote_reference”“”)”}”(hŒ[1]_”h]”hŒ1”…””}”(hj#h²hh³Nh´Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œrefid”Œid4”Œdocname”ŒPCI/boot-interrupts”uh1j!hjŒresolved”Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KVhjh²hubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hXIntel® 6300ESB I/O Controller Hub Alternate Base Address Register: BIE: Boot Interrupt Enable == =========================== 0 Boot interrupt is enabled. 1 Boot interrupt is disabled. == =========================== ”h]”(hŒterm”“”)”}”(hŒ"Intel® 6300ESB I/O Controller Hub”h]”hŒ"Intel® 6300ESB I/O Controller Hub”…””}”(hjJh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jHh³hÇh´KbhjDubhŒ definition”“”)”}”(hhh]”j>)”}”(hhh]”jC)”}”(hŒØAlternate Base Address Register: BIE: Boot Interrupt Enable == =========================== 0 Boot interrupt is enabled. 1 Boot interrupt is disabled. == =========================== ”h]”(jI)”}”(hŒ Alternate Base Address Register:”h]”hŒ Alternate Base Address Register:”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jHh³hÇh´Kbhj`ubjY)”}”(hhh]”(j )”}”(hŒBIE: Boot Interrupt Enable”h]”hŒBIE: Boot Interrupt Enable”…””}”(hjuh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K]hjrubhŒ block_quote”“”)”}”(hŒ== =========================== 0 Boot interrupt is enabled. 1 Boot interrupt is disabled. == =========================== ”h]”hŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1j“hjubj”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1j“hjubhŒtbody”“”)”}”(hhh]”(hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”j )”}”(hŒ0”h]”hŒ0”…””}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K`hjµubah}”(h]”h ]”h"]”h$]”h&]”uh1j³hj°ubj´)”}”(hhh]”j )”}”(hŒBoot interrupt is enabled.”h]”hŒBoot interrupt is enabled.”…””}”(hjÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K`hjÌubah}”(h]”h ]”h"]”h$]”h&]”uh1j³hj°ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j®hj«ubj¯)”}”(hhh]”(j´)”}”(hhh]”j )”}”(hŒ1”h]”hŒ1”…””}”(hjïh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kahjìubah}”(h]”h ]”h"]”h$]”h&]”uh1j³hjéubj´)”}”(hhh]”j )”}”(hŒBoot interrupt is disabled.”h]”hŒBoot interrupt is disabled.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kahjubah}”(h]”h ]”h"]”h$]”h&]”uh1j³hjéubeh}”(h]”h ]”h"]”h$]”h&]”uh1j®hj«ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j©hjubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jŽhj‹ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‰hj…ubah}”(h]”h ]”h"]”h$]”h&]”uh1jƒh³hÇh´K_hjrubeh}”(h]”h ]”h"]”h$]”h&]”uh1jXhj`ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jBh³hÇh´Kbhj]ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=hjZubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjDubeh}”(h]”h ]”h"]”h$]”h&]”uh1jBh³hÇh´Kbhj?ubjC)”}”(hXþIntel® Sandy Bridge through Sky Lake based Xeon servers: Coherent Interface Protocol Interrupt Control dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) ”h]”(jI)”}”(hŒ9Intel® Sandy Bridge through Sky Lake based Xeon servers:”h]”hŒ9Intel® Sandy Bridge through Sky Lake based Xeon servers:”…””}”(hj[h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jHh³hÇh´KkhjWubjY)”}”(hhh]”j>)”}”(hhh]”jC)”}”(hX¾Coherent Interface Protocol Interrupt Control dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) ”h]”(jI)”}”(hŒ-Coherent Interface Protocol Interrupt Control”h]”hŒ-Coherent Interface Protocol Interrupt Control”…””}”(hjsh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jHh³hÇh´KkhjoubjY)”}”(hhh]”j>)”}”(hhh]”jC)”}”(hXmdis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) ”h]”(jI)”}”(hŒ:dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2:”h]”hŒ:dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2:”…””}”(hj‹h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jHh³hÇh´Kkhj‡ubjY)”}”(hhh]”j )”}”(hX1When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set)”h]”hX1When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set)”…””}”(hjœh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kghj™ubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhj‡ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jBh³hÇh´Kkhj„ubah}”(h]”h ]”h"]”h$]”h&]”uh1j=hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjoubeh}”(h]”h ]”h"]”h$]”h&]”uh1jBh³hÇh´Kkhjlubah}”(h]”h ]”h"]”h$]”h&]”uh1j=hjiubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjWubeh}”(h]”h ]”h"]”h$]”h&]”uh1jBh³hÇh´Kkhj?h²hubeh}”(h]”h ]”h"]”h$]”h&]”uh1j=hjh²hh³Nh´Nubj )”}”(hX*In the absence of a way to directly disable the routing, another approach has been to make use of PCI Interrupt pin to INTx routing tables for purposes of redirecting the interrupt handler to the rerouted interrupt line by default. Therefore, on chipsets where this INTx routing cannot be disabled, the Linux kernel will reroute the valid interrupt to its legacy interrupt. This redirection of the handler will prevent the occurrence of the spurious interrupt detection which would ordinarily disable the IRQ line due to excessive unhandled counts. [2]_”h]”(hX&In the absence of a way to directly disable the routing, another approach has been to make use of PCI Interrupt pin to INTx routing tables for purposes of redirecting the interrupt handler to the rerouted interrupt line by default. Therefore, on chipsets where this INTx routing cannot be disabled, the Linux kernel will reroute the valid interrupt to its legacy interrupt. This redirection of the handler will prevent the occurrence of the spurious interrupt detection which would ordinarily disable the IRQ line due to excessive unhandled counts. ”…””}”(hjàh²hh³Nh´Nubj")”}”(hŒ[2]_”h]”hŒ2”…””}”(hjèh²hh³Nh´Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”j2Œid5”j4j5uh1j!hjàj6Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kmhjh²hubj )”}”(hŒêThe config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS exists to enable (or disable) the redirection of the interrupt handler to the PCH interrupt line. The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute. [3]_”h]”(hŒæThe config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS exists to enable (or disable) the redirection of the interrupt handler to the PCH interrupt line. The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute. ”…””}”(hjþh²hh³Nh´Nubj")”}”(hŒ[3]_”h]”hŒ3”…””}”(hjh²hh³Nh´Nubah}”(h]”Œid3”ah ]”h"]”h$]”h&]”j2Œid6”j4j5uh1j!hjþj6Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kvhjh²hubeh}”(h]”Œ mitigations”ah ]”h"]”Œ mitigations”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KTubhÉ)”}”(hhh]”(hÎ)”}”(hŒMore Documentation”h]”hŒMore Documentation”…””}”(hj'h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj$h²hh³hÇh´K}ubj )”}”(hŒÆThere is an overview of the legacy interrupt handling in several datasheets (6300ESB and 6700PXH below). While largely the same, it provides insight into the evolution of its handling with chipsets.”h]”hŒÆThere is an overview of the legacy interrupt handling in several datasheets (6300ESB and 6700PXH below). While largely the same, it provides insight into the evolution of its handling with chipsets.”…””}”(hj5h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Khj$h²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒ*Example of disabling of the boot interrupt”h]”hŒ*Example of disabling of the boot interrupt”…””}”(hjFh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjCh²hh³hÇh´K„ubj„)”}”(hXÚ- Intel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf - Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf ”h]”hþ)”}”(hhh]”(j)”}”(hŒªIntel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf ”h]”j )”}”(hŒ©Intel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf”h]”(hŒRIntel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt ”…””}”(hj_h²hh³Nh´Nubj)”}”(hŒWhttps://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf”h]”hŒWhttps://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf”…””}”(hjgh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jiuh1jhj_ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K†hj[ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjXubj)”}”(hX!Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf ”h]”j )”}”(hX Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf”h]”(hŒºIntel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control ”…””}”(hj†h²hh³Nh´Nubj)”}”(hŒfhttps://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf”h]”hŒfhttps://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf”…””}”(hjŽh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”juh1jhj†ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KŠhj‚ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjXubeh}”(h]”h ]”h"]”h$]”h&]”j:j;uh1hýh³hÇh´K†hjTubah}”(h]”h ]”h"]”h$]”h&]”uh1jƒh³hÇh´K†hjCh²hubeh}”(h]”Œ*example-of-disabling-of-the-boot-interrupt”ah ]”h"]”Œ*example of disabling of the boot interrupt”ah$]”h&]”uh1hÈhj$h²hh³hÇh´K„ubhÉ)”}”(hhh]”(hÎ)”}”(hŒExample of handler rerouting”h]”hŒExample of handler rerouting”…””}”(hjÀh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj½h²hh³hÇh´Kubj„)”}”(hŒÉ- Intel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf ”h]”hþ)”}”(hhh]”j)”}”(hŒÃIntel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf ”h]”j )”}”(hŒÁIntel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf”h]”(hŒmIntel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt ”…””}”(hjÙh²hh³Nh´Nubj)”}”(hŒThttps://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf”h]”hŒThttps://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf”…””}”(hjáh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jãuh1jhjÙubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K’hjÕubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÒubah}”(h]”h ]”h"]”h$]”h&]”j:j;uh1hýh³hÇh´K’hjÎubah}”(h]”h ]”h"]”h$]”h&]”uh1jƒh³hÇh´K’hj½h²hubj )”}”(hŒNIf you have any legacy PCI interrupt questions that aren't answered, email me.”h]”hŒPIf you have any legacy PCI interrupt questions that aren’t answered, email me.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K—hj½h²hubj>)”}”(hhh]”jC)”}”(hŒ4Cheers, Sean V Kelley sean.v.kelley@linux.intel.com ”h]”(jI)”}”(hŒCheers,”h]”hŒCheers,”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jHh³hÇh´K›hjubjY)”}”(hhh]”j )”}”(hŒ+Sean V Kelley sean.v.kelley@linux.intel.com”h]”(hŒSean V Kelley ”…””}”(hj.h²hh³Nh´Nubj)”}”(hŒsean.v.kelley@linux.intel.com”h]”hŒsean.v.kelley@linux.intel.com”…””}”(hj6h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œ$mailto:sean.v.kelley@linux.intel.com”uh1jhj.ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kšhj+ubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jBh³hÇh´K›hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j=hj½h²hh³hÇh´NubhŒfootnote”“”)”}”(hŒIhttps://lore.kernel.org/r/12131949181903-git-send-email-sassmann@suse.de/”h]”(hŒlabel”“”)”}”(hŒ1”h]”hŒ1”…””}”(hjfh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jdhj`ubj )”}”(hjbh]”j)”}”(hjbh]”hŒIhttps://lore.kernel.org/r/12131949181903-git-send-email-sassmann@suse.de/”…””}”(hjwh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jbuh1jhjtubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Khj`ubeh}”(h]”j3ah ]”h"]”Œ1”ah$]”h&]”j-aj4j5uh1j^h³hÇh´Khj½h²hj6Kubj_)”}”(hŒIhttps://lore.kernel.org/r/12131949182094-git-send-email-sassmann@suse.de/”h]”(je)”}”(hŒ2”h]”hŒ2”…””}”(hj–h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jdhj’ubj )”}”(hj”h]”j)”}”(hj”h]”hŒIhttps://lore.kernel.org/r/12131949182094-git-send-email-sassmann@suse.de/”…””}”(hj§h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j”uh1jhj¤ubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kžhj’ubeh}”(h]”j÷ah ]”h"]”Œ2”ah$]”h&]”jòaj4j5uh1j^h³hÇh´Kžhj½h²hj6Kubj_)”}”(hŒ3https://lore.kernel.org/r/487C8EA7.6020205@suse.de/”h]”(je)”}”(hŒ3”h]”hŒ3”…””}”(hjÆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jdhjÂubj )”}”(hjÄh]”j)”}”(hjÄh]”hŒ3https://lore.kernel.org/r/487C8EA7.6020205@suse.de/”…””}”(hj×h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jÄuh1jhjÔubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KŸhjÂubeh}”(h]”jah ]”h"]”Œ3”ah$]”h&]”jaj4j5uh1j^h³hÇh´KŸhj½h²hj6Kubeh}”(h]”Œexample-of-handler-rerouting”ah ]”h"]”Œexample of handler rerouting”ah$]”h&]”uh1hÈhj$h²hh³hÇh´Kubeh}”(h]”Œmore-documentation”ah ]”h"]”Œmore documentation”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K}ubeh}”(h]”Œboot-interrupts”ah ]”h"]”Œboot interrupts”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”j³Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j,Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”(Œ1”]”j#aŒ2”]”jèaŒ3”]”jauŒrefids”}”Œnameids”}”(jjjrjoj©j¦jÐjÍjjj!jjÿjüjºj·j÷jôjj3j¿j÷jïjuŒ nametypes”}”(j‰jr‰j©‰jЉj‰j!‰jÿ‰jº‰j÷‰jˆj¿ˆjïˆuh}”(jhÊjojNj¦jujÍj¬jjÓjjj-j#jòjèjjjüj$j·jCjôj½j3j`j÷j’jjÂuŒ footnote_refs”}”(jl]”j#ajn]”jèajp]”jauŒ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”(j`j’jÂeŒ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”j:Ks…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.