€•ÃsŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ'/translations/zh_CN/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/zh_TW/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/it_IT/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ja_JP/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ko_KR/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/sp_SP/PCI/boot-interrupts”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1h¡hhhžhhŸŒA/var/lib/git/docbuild/linux/Documentation/PCI/boot-interrupts.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒBoot Interrupts”h]”hŒBoot Interrupts”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ field_list”“”)”}”(hhh]”hŒfield”“”)”}”(hhh]”(hŒ field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hhÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÓhhÐhŸh³h KubhŒ field_body”“”)”}”(hŒ0- Sean V Kelley ”h]”hŒ bullet_list”“”)”}”(hhh]”hŒ list_item”“”)”}”(hŒ.Sean V Kelley ”h]”hŒ paragraph”“”)”}”(hŒ-Sean V Kelley ”h]”(hŒSean V Kelley <”…””}”(hhöhžhhŸNh NubhŒ reference”“”)”}”(hŒsean.v.kelley@linux.intel.com”h]”hŒsean.v.kelley@linux.intel.com”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œ$mailto:sean.v.kelley@linux.intel.com”uh1hþhhöubhŒ>”…””}”(hhöhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khhðubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhëubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1héhŸh³h Khhåubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhÐubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h KhhËhžhubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒOverview”h]”hŒOverview”…””}”(hj=hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj:hžhhŸh³h K ubhõ)”}”(hXQOn PCI Express, interrupts are represented with either MSI or inbound interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a given Core IO converts the legacy interrupt messages from PCI Express to MSI interrupts. If the IO-APIC is disabled (via the mask bits in the IO-APIC table entries), the messages are routed to the legacy PCH. This in-band interrupt mechanism was traditionally necessary for systems that did not support the IO-APIC and for boot. Intel in the past has used the term "boot interrupts" to describe this mechanism. Further, the PCI Express protocol describes this in-band legacy wire-interrupt INTx mechanism for I/O devices to signal PCI-style level interrupts. The subsequent paragraphs describe problems with the Core IO handling of INTx message routing to the PCH and mitigation within BIOS and the OS.”h]”hXUOn PCI Express, interrupts are represented with either MSI or inbound interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a given Core IO converts the legacy interrupt messages from PCI Express to MSI interrupts. If the IO-APIC is disabled (via the mask bits in the IO-APIC table entries), the messages are routed to the legacy PCH. This in-band interrupt mechanism was traditionally necessary for systems that did not support the IO-APIC and for boot. Intel in the past has used the term “boot interrupts†to describe this mechanism. Further, the PCI Express protocol describes this in-band legacy wire-interrupt INTx mechanism for I/O devices to signal PCI-style level interrupts. The subsequent paragraphs describe problems with the Core IO handling of INTx message routing to the PCH and mitigation within BIOS and the OS.”…””}”(hjKhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K hj:hžhubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1h´hh¶hžhhŸh³h K ubhµ)”}”(hhh]”(hº)”}”(hŒIssue”h]”hŒIssue”…””}”(hjdhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjahžhhŸh³h Kubhõ)”}”(hXÍWhen in-band legacy INTx messages are forwarded to the PCH, they in turn trigger a new interrupt for which the OS likely lacks a handler. When an interrupt goes unhandled over time, they are tracked by the Linux kernel as Spurious Interrupts. The IRQ will be disabled by the Linux kernel after it reaches a specific count with the error "nobody cared". This disabled IRQ now prevents valid usage by an existing interrupt which may happen to share the IRQ line::”h]”hXÐWhen in-band legacy INTx messages are forwarded to the PCH, they in turn trigger a new interrupt for which the OS likely lacks a handler. When an interrupt goes unhandled over time, they are tracked by the Linux kernel as Spurious Interrupts. The IRQ will be disabled by the Linux kernel after it reaches a specific count with the error “nobody caredâ€. This disabled IRQ now prevents valid usage by an existing interrupt which may happen to share the IRQ line:”…””}”(hjrhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KhjahžhubhŒ literal_block”“”)”}”(hX{irq 19: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1 Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 Call Trace: ? dump_stack+0x46/0x5e ? __report_bad_irq+0x2e/0xb0 ? note_interrupt+0x242/0x290 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] ? handle_irq_event_percpu+0x55/0x70 ? handle_irq_event+0x4f/0x80 ? handle_fasteoi_irq+0x81/0x180 ? handle_irq+0x1c/0x30 ? do_IRQ+0x41/0xd0 ? common_interrupt+0x84/0x84 handlers: irq_default_primary_handler threaded usb_hcd_irq Disabling IRQ #19”h]”hX{irq 19: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1 Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 Call Trace: ? dump_stack+0x46/0x5e ? __report_bad_irq+0x2e/0xb0 ? note_interrupt+0x242/0x290 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] ? handle_irq_event_percpu+0x55/0x70 ? handle_irq_event+0x4f/0x80 ? handle_fasteoi_irq+0x81/0x180 ? handle_irq+0x1c/0x30 ? do_IRQ+0x41/0xd0 ? common_interrupt+0x84/0x84 handlers: irq_default_primary_handler threaded usb_hcd_irq Disabling IRQ #19”…””}”hj‚sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j€hŸh³h K%hjahžhubeh}”(h]”Œissue”ah ]”h"]”Œissue”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒ Conditions”h]”hŒ Conditions”…””}”(hj›hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj˜hžhhŸh³h K=ubhõ)”}”(hXûThe use of threaded interrupts is the most likely condition to trigger this problem today. Threaded interrupts may not be re-enabled after the IRQ handler wakes. These "one shot" conditions mean that the threaded interrupt needs to keep the interrupt line masked until the threaded handler has run. Especially when dealing with high data rate interrupts, the thread needs to run to completion; otherwise some handlers will end up in stack overflows since the interrupt of the issuing device is still active.”h]”hXÿThe use of threaded interrupts is the most likely condition to trigger this problem today. Threaded interrupts may not be re-enabled after the IRQ handler wakes. These “one shot†conditions mean that the threaded interrupt needs to keep the interrupt line masked until the threaded handler has run. Especially when dealing with high data rate interrupts, the thread needs to run to completion; otherwise some handlers will end up in stack overflows since the interrupt of the issuing device is still active.”…””}”(hj©hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K?hj˜hžhubeh}”(h]”Œ conditions”ah ]”h"]”Œ conditions”ah$]”h&]”uh1h´hh¶hžhhŸh³h K=ubhµ)”}”(hhh]”(hº)”}”(hŒAffected Chipsets”h]”hŒAffected Chipsets”…””}”(hjÂhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj¿hžhhŸh³h KHubhõ)”}”(hŒëThe legacy interrupt forwarding mechanism exists today in a number of devices including but not limited to chipsets from AMD/ATI, Broadcom, and Intel. Changes made through the mitigations below have been applied to drivers/pci/quirks.c”h]”hŒëThe legacy interrupt forwarding mechanism exists today in a number of devices including but not limited to chipsets from AMD/ATI, Broadcom, and Intel. Changes made through the mitigations below have been applied to drivers/pci/quirks.c”…””}”(hjÐhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KJhj¿hžhubhõ)”}”(hŒÃStarting with ICX there are no longer any IO-APICs in the Core IO's devices. IO-APIC is only in the PCH. Devices connected to the Core IO's PCIe Root Ports will use native MSI/MSI-X mechanisms.”h]”hŒÇStarting with ICX there are no longer any IO-APICs in the Core IO’s devices. IO-APIC is only in the PCH. Devices connected to the Core IO’s PCIe Root Ports will use native MSI/MSI-X mechanisms.”…””}”(hjÞhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KOhj¿hžhubeh}”(h]”Œaffected-chipsets”ah ]”h"]”Œaffected chipsets”ah$]”h&]”uh1h´hh¶hžhhŸh³h KHubhµ)”}”(hhh]”(hº)”}”(hŒ Mitigations”h]”hŒ Mitigations”…””}”(hj÷hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjôhžhhŸh³h KTubhõ)”}”(hŒàThe mitigations take the form of PCI quirks. The preference has been to first identify and make use of a means to disable the routing to the PCH. In such a case a quirk to disable boot interrupt generation can be added. [1]_”h]”(hŒÜThe mitigations take the form of PCI quirks. The preference has been to first identify and make use of a means to disable the routing to the PCH. In such a case a quirk to disable boot interrupt generation can be added. ”…””}”(hjhžhhŸNh NubhŒfootnote_reference”“”)”}”(hŒ[1]_”h]”hŒ1”…””}”(hjhžhhŸNh Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œrefid”Œid4”Œdocname”ŒPCI/boot-interrupts”uh1j hjŒresolved”Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KVhjôhžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hXIntel® 6300ESB I/O Controller Hub Alternate Base Address Register: BIE: Boot Interrupt Enable == =========================== 0 Boot interrupt is enabled. 1 Boot interrupt is disabled. == =========================== ”h]”(hŒterm”“”)”}”(hŒ"Intel® 6300ESB I/O Controller Hub”h]”hŒ"Intel® 6300ESB I/O Controller Hub”…””}”(hj6hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4hŸh³h Kbhj0ubhŒ definition”“”)”}”(hhh]”j*)”}”(hhh]”j/)”}”(hŒØAlternate Base Address Register: BIE: Boot Interrupt Enable == =========================== 0 Boot interrupt is enabled. 1 Boot interrupt is disabled. == =========================== ”h]”(j5)”}”(hŒ Alternate Base Address Register:”h]”hŒ Alternate Base Address Register:”…””}”(hjPhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4hŸh³h KbhjLubjE)”}”(hhh]”(hõ)”}”(hŒBIE: Boot Interrupt Enable”h]”hŒBIE: Boot Interrupt Enable”…””}”(hjahžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K]hj^ubhŒ block_quote”“”)”}”(hŒ== =========================== 0 Boot interrupt is enabled. 1 Boot interrupt is disabled. == =========================== ”h]”hŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj|ubj€)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj|ubhŒtbody”“”)”}”(hhh]”(hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”hõ)”}”(hŒ0”h]”hŒ0”…””}”(hj¤hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K`hj¡ubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjœubj )”}”(hhh]”hõ)”}”(hŒBoot interrupt is enabled.”h]”hŒBoot interrupt is enabled.”…””}”(hj»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K`hj¸ubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjœubeh}”(h]”h ]”h"]”h$]”h&]”uh1jšhj—ubj›)”}”(hhh]”(j )”}”(hhh]”hõ)”}”(hŒ1”h]”hŒ1”…””}”(hjÛhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KahjØubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjÕubj )”}”(hhh]”hõ)”}”(hŒBoot interrupt is disabled.”h]”hŒBoot interrupt is disabled.”…””}”(hjòhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kahjïubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjÕubeh}”(h]”h ]”h"]”h$]”h&]”uh1jšhj—ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j•hj|ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jzhjwubah}”(h]”h ]”h"]”h$]”h&]”uh1juhjqubah}”(h]”h ]”h"]”h$]”h&]”uh1johŸh³h K_hj^ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jDhjLubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.hŸh³h KbhjIubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjFubah}”(h]”h ]”h"]”h$]”h&]”uh1jDhj0ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.hŸh³h Kbhj+ubj/)”}”(hXþIntel® Sandy Bridge through Sky Lake based Xeon servers: Coherent Interface Protocol Interrupt Control dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) ”h]”(j5)”}”(hŒ9Intel® Sandy Bridge through Sky Lake based Xeon servers:”h]”hŒ9Intel® Sandy Bridge through Sky Lake based Xeon servers:”…””}”(hjGhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4hŸh³h KkhjCubjE)”}”(hhh]”j*)”}”(hhh]”j/)”}”(hX¾Coherent Interface Protocol Interrupt Control dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) ”h]”(j5)”}”(hŒ-Coherent Interface Protocol Interrupt Control”h]”hŒ-Coherent Interface Protocol Interrupt Control”…””}”(hj_hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4hŸh³h Kkhj[ubjE)”}”(hhh]”j*)”}”(hhh]”j/)”}”(hXmdis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2: When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set) ”h]”(j5)”}”(hŒ:dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2:”h]”hŒ:dis_intx_route2pch/dis_intx_route2ich/dis_intx_route2dmi2:”…””}”(hjwhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4hŸh³h KkhjsubjE)”}”(hhh]”hõ)”}”(hX1When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set)”h]”hX1When this bit is set. Local INTx messages received from the Intel® Quick Data DMA/PCI Express ports are not routed to legacy PCH - they are either converted into MSI via the integrated IO-APIC (if the IO-APIC mask bit is clear in the appropriate entries) or cause no further action (when mask bit is set)”…””}”(hjˆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kghj…ubah}”(h]”h ]”h"]”h$]”h&]”uh1jDhjsubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.hŸh³h Kkhjpubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjmubah}”(h]”h ]”h"]”h$]”h&]”uh1jDhj[ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.hŸh³h KkhjXubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjUubah}”(h]”h ]”h"]”h$]”h&]”uh1jDhjCubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.hŸh³h Kkhj+hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j)hjôhžhhŸNh Nubhõ)”}”(hX*In the absence of a way to directly disable the routing, another approach has been to make use of PCI Interrupt pin to INTx routing tables for purposes of redirecting the interrupt handler to the rerouted interrupt line by default. Therefore, on chipsets where this INTx routing cannot be disabled, the Linux kernel will reroute the valid interrupt to its legacy interrupt. This redirection of the handler will prevent the occurrence of the spurious interrupt detection which would ordinarily disable the IRQ line due to excessive unhandled counts. [2]_”h]”(hX&In the absence of a way to directly disable the routing, another approach has been to make use of PCI Interrupt pin to INTx routing tables for purposes of redirecting the interrupt handler to the rerouted interrupt line by default. Therefore, on chipsets where this INTx routing cannot be disabled, the Linux kernel will reroute the valid interrupt to its legacy interrupt. This redirection of the handler will prevent the occurrence of the spurious interrupt detection which would ordinarily disable the IRQ line due to excessive unhandled counts. ”…””}”(hjÌhžhhŸNh Nubj)”}”(hŒ[2]_”h]”hŒ2”…””}”(hjÔhžhhŸNh Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”jŒid5”j j!uh1j hjÌj"Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kmhjôhžhubhõ)”}”(hŒêThe config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS exists to enable (or disable) the redirection of the interrupt handler to the PCH interrupt line. The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute. [3]_”h]”(hŒæThe config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS exists to enable (or disable) the redirection of the interrupt handler to the PCH interrupt line. The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute. ”…””}”(hjêhžhhŸNh Nubj)”}”(hŒ[3]_”h]”hŒ3”…””}”(hjòhžhhŸNh Nubah}”(h]”Œid3”ah ]”h"]”h$]”h&]”jŒid6”j j!uh1j hjêj"Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kvhjôhžhubeh}”(h]”Œ mitigations”ah ]”h"]”Œ mitigations”ah$]”h&]”uh1h´hh¶hžhhŸh³h KTubhµ)”}”(hhh]”(hº)”}”(hŒMore Documentation”h]”hŒMore Documentation”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjhžhhŸh³h K}ubhõ)”}”(hŒÆThere is an overview of the legacy interrupt handling in several datasheets (6300ESB and 6700PXH below). While largely the same, it provides insight into the evolution of its handling with chipsets.”h]”hŒÆThere is an overview of the legacy interrupt handling in several datasheets (6300ESB and 6700PXH below). While largely the same, it provides insight into the evolution of its handling with chipsets.”…””}”(hj!hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khjhžhubhµ)”}”(hhh]”(hº)”}”(hŒ*Example of disabling of the boot interrupt”h]”hŒ*Example of disabling of the boot interrupt”…””}”(hj2hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj/hžhhŸh³h K„ubjp)”}”(hXÚ- Intel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf - Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf ”h]”hê)”}”(hhh]”(hï)”}”(hŒªIntel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf ”h]”hõ)”}”(hŒ©Intel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf”h]”(hŒRIntel® 6300ESB I/O Controller Hub (Document # 300641-004US) 5.7.3 Boot Interrupt ”…””}”(hjKhžhhŸNh Nubhÿ)”}”(hŒWhttps://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf”h]”hŒWhttps://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf”…””}”(hjShžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jUuh1hþhjKubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K†hjGubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjDubhï)”}”(hX!Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf ”h]”hõ)”}”(hX Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf”h]”(hŒºIntel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families Datasheet - Volume 2: Registers (Document # 330784-003) 6.6.41 cipintrc Coherent Interface Protocol Interrupt Control ”…””}”(hjrhžhhŸNh Nubhÿ)”}”(hŒfhttps://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf”h]”hŒfhttps://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2.pdf”…””}”(hjzhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j|uh1hþhjrubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KŠhjnubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjDubeh}”(h]”h ]”h"]”h$]”h&]”j&j'uh1héhŸh³h K†hj@ubah}”(h]”h ]”h"]”h$]”h&]”uh1johŸh³h K†hj/hžhubeh}”(h]”Œ*example-of-disabling-of-the-boot-interrupt”ah ]”h"]”Œ*example of disabling of the boot interrupt”ah$]”h&]”uh1h´hjhžhhŸh³h K„ubhµ)”}”(hhh]”(hº)”}”(hŒExample of handler rerouting”h]”hŒExample of handler rerouting”…””}”(hj¬hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj©hžhhŸh³h Kubjp)”}”(hŒÉ- Intel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf ”h]”hê)”}”(hhh]”hï)”}”(hŒÃIntel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf ”h]”hõ)”}”(hŒÁIntel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf”h]”(hŒmIntel® 6700PXH 64-bit PCI Hub (Document # 302628) 2.15.2 PCI Express Legacy INTx Support and Boot Interrupt ”…””}”(hjÅhžhhŸNh Nubhÿ)”}”(hŒThttps://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf”h]”hŒThttps://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf”…””}”(hjÍhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jÏuh1hþhjÅubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K’hjÁubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhj¾ubah}”(h]”h ]”h"]”h$]”h&]”j&j'uh1héhŸh³h K’hjºubah}”(h]”h ]”h"]”h$]”h&]”uh1johŸh³h K’hj©hžhubhõ)”}”(hŒNIf you have any legacy PCI interrupt questions that aren't answered, email me.”h]”hŒPIf you have any legacy PCI interrupt questions that aren’t answered, email me.”…””}”(hjôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K—hj©hžhubj*)”}”(hhh]”j/)”}”(hŒ4Cheers, Sean V Kelley sean.v.kelley@linux.intel.com ”h]”(j5)”}”(hŒCheers,”h]”hŒCheers,”…””}”(hj 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j!uh1jJhŸh³h Khj©hžhj"KubjK)”}”(hŒIhttps://lore.kernel.org/r/12131949182094-git-send-email-sassmann@suse.de/”h]”(jQ)”}”(hŒ2”h]”hŒ2”…””}”(hj‚hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jPhj~ubhõ)”}”(hj€h]”hÿ)”}”(hj€h]”hŒIhttps://lore.kernel.org/r/12131949182094-git-send-email-sassmann@suse.de/”…””}”(hj“hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j€uh1hþhjubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kžhj~ubeh}”(h]”jãah ]”h"]”Œ2”ah$]”h&]”jÞaj j!uh1jJhŸh³h Kžhj©hžhj"KubjK)”}”(hŒ3https://lore.kernel.org/r/487C8EA7.6020205@suse.de/”h]”(jQ)”}”(hŒ3”h]”hŒ3”…””}”(hj²hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jPhj®ubhõ)”}”(hj°h]”hÿ)”}”(hj°h]”hŒ3https://lore.kernel.org/r/487C8EA7.6020205@suse.de/”…””}”(hjÃhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j°uh1hþhjÀubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KŸhj®ubeh}”(h]”jah ]”h"]”Œ3”ah$]”h&]”jüaj j!uh1jJhŸh³h KŸhj©hžhj"Kubeh}”(h]”Œexample-of-handler-rerouting”ah ]”h"]”Œexample of handler rerouting”ah$]”h&]”uh1h´hjhžhhŸh³h Kubeh}”(h]”Œmore-documentation”ah ]”h"]”Œmore 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