# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (c) 2020 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP iMX8QM Soc USB Controller maintainers: - Frank Li properties: compatible: const: fsl,imx8qm-usb3 reg: items: - description: Register set for iMX USB3 Platform Control "#address-cells": enum: [ 1, 2 ] "#size-cells": enum: [ 1, 2 ] ranges: true clocks: items: - description: Standby clock. Used during ultra low power states. - description: USB bus clock for usb3 controller. - description: AXI clock for AXI interface. - description: ipg clock for register access. - description: Core clock for usb3 controller. clock-names: items: - const: lpm - const: bus - const: aclk - const: ipg - const: core power-domains: maxItems: 1 # Required child node: patternProperties: "^usb@[0-9a-f]+$": $ref: cdns,usb3.yaml# required: - compatible - reg - "#address-cells" - "#size-cells" - ranges - clocks - clock-names - power-domains additionalProperties: false examples: - | #include #include #include usb@5b110000 { compatible = "fsl,imx8qm-usb3"; reg = <0x5b110000 0x10000>; ranges; clocks = <&usb3_lpcg IMX_LPCG_CLK_1>, <&usb3_lpcg IMX_LPCG_CLK_0>, <&usb3_lpcg IMX_LPCG_CLK_7>, <&usb3_lpcg IMX_LPCG_CLK_4>, <&usb3_lpcg IMX_LPCG_CLK_5>; clock-names = "lpm", "bus", "aclk", "ipg", "core"; assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; assigned-clock-rates = <250000000>; power-domains = <&pd IMX_SC_R_USB_2>; #address-cells = <1>; #size-cells = <1>; usb@5b120000 { compatible = "cdns,usb3"; reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */ <0x5b130000 0x10000>, /* memory area for HOST registers */ <0x5b140000 0x10000>; /* memory area for DEVICE registers */ reg-names = "otg", "xhci", "dev"; interrupt-parent = <&gic>; interrupts = , , , ; interrupt-names = "host", "peripheral", "otg", "wakeup"; phys = <&usb3_phy>; phy-names = "cdns3,usb3-phy"; }; };