# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - Michal Simek allOf: - $ref: spi-controller.yaml# properties: compatible: enum: - xlnx,versal-qspi-1.0 - xlnx,zynqmp-qspi-1.0 reg: maxItems: 2 interrupts: maxItems: 1 clock-names: items: - const: ref_clk - const: pclk clocks: maxItems: 2 iommus: maxItems: 1 power-domains: maxItems: 1 required: - compatible - reg - interrupts - clock-names - clocks unevaluatedProperties: false examples: - | #include soc { #address-cells = <2>; #size-cells = <2>; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; }; };