NXP Layerscape PCIe Gen4 controller This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all the common properties defined in mobiveil-pcie.txt. Required properties: - compatible: should contain the platform identifier such as: "fsl,lx2160a-pcie" - reg: base addresses and lengths of the PCIe controller register blocks. "csr_axi_slave": Bridge config registers "config_axi_slave": PCIe controller registers - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. - interrupt-names: It could include the following entries: "intr": The interrupt that is asserted for controller interrupts "aer": Asserted for aer interrupt when chip support the aer interrupt with none MSI/MSI-X/INTx mode,but there is interrupt line for aer. "pme": Asserted for pme interrupt when chip support the pme interrupt with none MSI/MSI-X/INTx mode,but there is interrupt line for pme. - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. - msi-parent : See the generic MSI binding described in Documentation/devicetree/bindings/interrupt-controller/msi.txt. Example: pcie@3400000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ interrupt-names = "aer", "pme", "intr"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; apio-wins = <8>; ppio-wins = <8>; dma-coherent; bus-range = <0x0 0xff>; msi-parent = <&its>; ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; };