# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Neural Processing Unit IP from Rockchip

maintainers:
  - Tomeu Vizoso <tomeu@tomeuvizoso.net>

description:
  Rockchip IP for accelerating inference of neural networks.

  There is to be a node per each NPU core in the SoC, and each core should reference all the
  resources that it needs to function, such as clocks, power domains, and resets.

properties:
  $nodename:
    pattern: '^npu@[a-f0-9]+$'

  compatible:
    enum:
      - rockchip,rk3588-rknn-core

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: pc # Program Control-related registers
      - const: cna # Convolution Neural Network Accelerator registers
      - const: core # Main NPU core processing unit registers

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: aclk
      - const: hclk
      - const: npu
      - const: pclk

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 1

  npu-supply: true

  power-domains:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: srst_a
      - const: srst_h

  sram-supply: true

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - iommus
  - power-domains
  - resets
  - reset-names
  - npu-supply
  - sram-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/rk3588-power.h>
    #include <dt-bindings/reset/rockchip,rk3588-cru.h>

    bus {
      #address-cells = <2>;
      #size-cells = <2>;

      npu@fdab0000 {
        compatible = "rockchip,rk3588-rknn-core";
        reg = <0x0 0xfdab0000 0x0 0x1000>,
              <0x0 0xfdab1000 0x0 0x1000>,
              <0x0 0xfdab3000 0x0 0x1000>;
        reg-names = "pc", "cna", "core";
        clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
                 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
        clock-names = "aclk", "hclk", "npu", "pclk";
        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
        iommus = <&rknn_mmu_0>;
        npu-supply = <&vdd_npu_s0>;
        power-domains = <&power RK3588_PD_NPUTOP>;
        resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
        reset-names = "srst_a", "srst_h";
        sram-supply = <&vdd_npu_mem_s0>;
      };
    };
...