* Allwinner sun8i GMAC ethernet controller This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: - compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-r40-gmac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" "allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device - interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device - clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device - reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - syscon: A phandle to the device containing the EMAC or GMAC clock register Optional properties: - allwinner,tx-delay-ps: TX clock delay chain value in ps. Range is 0-700. Default is 0. Unavailable for allwinner,sun8i-r40-gmac - allwinner,rx-delay-ps: RX clock delay chain value in ps. Range is 0-3100. Default is 0. Range is 0-700 for allwinner,sun8i-r40-gmac Both delay properties need to be a multiple of 100. They control the clock delay for external RGMII PHY. They do not apply to the internal PHY or external non-RGMII PHYs. Optional properties for the following compatibles: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: - mdio bus node: should be named mdio with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. The following compatibles require that the emac node have a mdio-mux child node called "mdio-mux": - "allwinner,sun8i-h3-emac" - "allwinner,sun8i-v3s-emac": Required properties for the mdio-mux node: - compatible = "allwinner,sun8i-h3-mdio-mux" - mdio-parent-bus: a phandle to EMAC mdio - one child mdio for the integrated mdio with the compatible "allwinner,sun8i-h3-mdio-internal" - one child mdio for the external mdio if present (V3s have none) Required properties for the mdio-mux children node: - reg: 1 for internal MDIO bus, 2 for external MDIO bus The following compatibles require a PHY node representing the integrated PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": Additional information regarding generic multiplexer properties can be found at Documentation/devicetree/bindings/net/mdio-mux.txt Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY - Must be a child of the integrated mdio Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; reg = <0x01c0b000 0x104>; interrupts = ; interrupt-names = "macirq"; resets = <&ccu RST_BUS_EMAC>; reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; mdio: mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; }; mdio-mux { compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; #address-cells = <1>; #size-cells = <0>; mdio-parent-bus = <&mdio>; int_mdio: mdio@1 { compatible = "allwinner,sun8i-h3-mdio-internal"; reg = <1>; #address-cells = <1>; #size-cells = <0>; int_mii_phy: ethernet-phy@1 { reg = <1>; clocks = <&ccu CLK_BUS_EPHY>; resets = <&ccu RST_BUS_EPHY>; phy-is-integrated; }; }; ext_mdio: mdio@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; }; }; Example with external PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; reg = <0x01c0b000 0x104>; interrupts = ; interrupt-names = "macirq"; resets = <&ccu RST_BUS_EMAC>; reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; phy-handle = <&ext_rgmii_phy>; phy-mode = "rgmii"; allwinner,leds-active-low; mdio: mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; }; mdio-mux { compatible = "allwinner,sun8i-h3-mdio-mux"; #address-cells = <1>; #size-cells = <0>; mdio-parent-bus = <&mdio>; int_mdio: mdio@1 { compatible = "allwinner,sun8i-h3-mdio-internal"; reg = <1>; #address-cells = <1>; #size-cells = <0>; int_mii_phy: ethernet-phy@1 { reg = <1>; clocks = <&ccu CLK_BUS_EPHY>; resets = <&ccu RST_BUS_EPHY>; }; }; ext_mdio: mdio@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; ext_rgmii_phy: ethernet-phy@1 { reg = <1>; }; }: }; }; Example with SoC without integrated PHY emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-a83t-emac"; syscon = <&syscon>; reg = <0x01c0b000 0x104>; interrupts = ; interrupt-names = "macirq"; resets = <&ccu RST_BUS_EMAC>; reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; phy-handle = <&ext_rgmii_phy>; phy-mode = "rgmii"; mdio: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ext_rgmii_phy: ethernet-phy@1 { reg = <1>; }; }; };