# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpass.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos SoC Low Power Audio Subsystem (LPASS) maintainers: - Krzysztof Kozlowski - Sylwester Nawrocki properties: compatible: const: samsung,exynos5433-lpass '#address-cells': const: 1 clocks: maxItems: 1 clock-names: items: - const: sfr0_ctrl power-domains: maxItems: 1 ranges: true reg: minItems: 2 maxItems: 2 '#size-cells': const: 1 patternProperties: "^dma-controller@[0-9a-f]+$": $ref: /schemas/dma/arm,pl330.yaml "^i2s@[0-9a-f]+$": $ref: /schemas/sound/samsung-i2s.yaml "^serial@[0-9a-f]+$": $ref: /schemas/serial/samsung_uart.yaml required: - compatible - '#address-cells' - clocks - clock-names - ranges - reg - '#size-cells' additionalProperties: false examples: - | #include #include audio-subsystem@11400000 { compatible = "samsung,exynos5433-lpass"; reg = <0x11400000 0x100>, <0x11500000 0x08>; clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; clock-names = "sfr0_ctrl"; power-domains = <&pd_aud>; #address-cells = <1>; #size-cells = <1>; ranges; dma-controller@11420000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11420000 0x1000>; interrupts = ; clocks = <&cmu_aud CLK_ACLK_DMAC>; clock-names = "apb_pclk"; #dma-cells = <1>; dma-channels = <8>; dma-requests = <32>; power-domains = <&pd_aud>; }; i2s@11440000 { compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s"; reg = <0x11440000 0x100>; dmas = <&adma 0>, <&adma 2>; dma-names = "tx", "rx"; interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, <&cmu_aud CLK_SCLK_AUD_I2S>, <&cmu_aud CLK_SCLK_I2S_BCLK>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; #clock-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; power-domains = <&pd_aud>; #sound-dai-cells = <1>; }; serial@11460000 { compatible = "samsung,exynos5433-uart"; reg = <0x11460000 0x100>; interrupts = ; clocks = <&cmu_aud CLK_PCLK_AUD_UART>, <&cmu_aud CLK_SCLK_AUD_UART>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart_aud_bus>; power-domains = <&pd_aud>; }; };