# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/media/amphion,vpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Amphion VPU codec IP maintainers: - Ming Qian - Shijie Qin description: |- The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present on NXP i.MX8Q SoCs. properties: $nodename: pattern: "^vpu@[0-9a-f]+$" compatible: items: - enum: - nxp,imx8qm-vpu - nxp,imx8qxp-vpu reg: maxItems: 1 power-domains: maxItems: 1 "#address-cells": const: 1 "#size-cells": const: 1 ranges: true patternProperties: "^mailbox@[0-9a-f]+$": description: Each vpu encoder or decoder correspond a MU, which used for communication between driver and firmware. Implement via mailbox on driver. $ref: ../mailbox/fsl,mu.yaml# "^vpu-core@[0-9a-f]+$": description: Each core correspond a decoder or encoder, need to configure them separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC has one decoder and one encoder. type: object properties: compatible: items: - enum: - nxp,imx8q-vpu-decoder - nxp,imx8q-vpu-encoder reg: maxItems: 1 power-domains: maxItems: 1 mbox-names: items: - const: tx0 - const: tx1 - const: rx mboxes: description: List of phandle of 2 MU channels for tx, 1 MU channel for rx. maxItems: 3 memory-region: description: Phandle to the reserved memory nodes to be associated with the remoteproc device. The reserved memory nodes should be carveout nodes, and should be defined as per the bindings in Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt items: - description: region reserved for firmware image sections. - description: region used for RPC shared memory between firmware and driver. required: - compatible - reg - power-domains - mbox-names - mboxes - memory-region additionalProperties: false required: - compatible - reg - power-domains additionalProperties: false examples: # Device node example for i.MX8QM platform: - | #include vpu: vpu@2c000000 { compatible = "nxp,imx8qm-vpu"; ranges = <0x2c000000 0x2c000000 0x2000000>; reg = <0x2c000000 0x1000000>; #address-cells = <1>; #size-cells = <1>; power-domains = <&pd IMX_SC_R_VPU>; mu_m0: mailbox@2d000000 { compatible = "fsl,imx6sx-mu"; reg = <0x2d000000 0x20000>; interrupts = <0 472 4>; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_VPU_MU_0>; }; mu1_m0: mailbox@2d020000 { compatible = "fsl,imx6sx-mu"; reg = <0x2d020000 0x20000>; interrupts = <0 473 4>; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_VPU_MU_1>; }; mu2_m0: mailbox@2d040000 { compatible = "fsl,imx6sx-mu"; reg = <0x2d040000 0x20000>; interrupts = <0 474 4>; #mbox-cells = <2>; power-domains = <&pd IMX_SC_R_VPU_MU_2>; }; vpu_core0: vpu-core@2d080000 { compatible = "nxp,imx8q-vpu-decoder"; reg = <0x2d080000 0x10000>; power-domains = <&pd IMX_SC_R_VPU_DEC_0>; mbox-names = "tx0", "tx1", "rx"; mboxes = <&mu_m0 0 0>, <&mu_m0 0 1>, <&mu_m0 1 0>; memory-region = <&decoder_boot>, <&decoder_rpc>; }; vpu_core1: vpu-core@2d090000 { compatible = "nxp,imx8q-vpu-encoder"; reg = <0x2d090000 0x10000>; power-domains = <&pd IMX_SC_R_VPU_ENC_0>; mbox-names = "tx0", "tx1", "rx"; mboxes = <&mu1_m0 0 0>, <&mu1_m0 0 1>, <&mu1_m0 1 0>; memory-region = <&encoder1_boot>, <&encoder1_rpc>; }; vpu_core2: vpu-core@2d0a0000 { reg = <0x2d0a0000 0x10000>; compatible = "nxp,imx8q-vpu-encoder"; power-domains = <&pd IMX_SC_R_VPU_ENC_1>; mbox-names = "tx0", "tx1", "rx"; mboxes = <&mu2_m0 0 0>, <&mu2_m0 0 1>, <&mu2_m0 1 0>; memory-region = <&encoder2_boot>, <&encoder2_rpc>; }; }; ...