# SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic i.MX bus frequency device maintainers: - Peng Fan description: | The i.MX SoC family has multiple buses for which clock frequency (and sometimes voltage) can be adjusted. Some of those buses expose register areas mentioned in the memory maps as GPV ("Global Programmers View") but not all. Access to this area might be denied for normal (non-secure) world. The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris FlexNOC but DT bindings are specific to the integration of these bus interconnect IPs into imx SOCs. properties: compatible: oneOf: - items: - enum: - fsl,imx8mm-nic - fsl,imx8mn-nic - fsl,imx8mp-nic - fsl,imx8mq-nic - const: fsl,imx8m-nic - items: - enum: - fsl,imx8mm-noc - fsl,imx8mn-noc - fsl,imx8mp-noc - fsl,imx8mq-noc - const: fsl,imx8m-noc - const: fsl,imx8m-nic reg: maxItems: 1 clocks: maxItems: 1 operating-points-v2: true opp-table: type: object fsl,ddrc: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to DDR Controller. '#interconnect-cells': description: If specified then also act as an interconnect provider. Should only be set once per soc on the main noc. const: 1 required: - compatible - clocks additionalProperties: false examples: - | #include #include #include noc: interconnect@32700000 { compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; reg = <0x32700000 0x100000>; clocks = <&clk IMX8MM_CLK_NOC>; #interconnect-cells = <1>; fsl,ddrc = <&ddrc>; operating-points-v2 = <&noc_opp_table>; noc_opp_table: opp-table { compatible = "operating-points-v2"; opp-133333333 { opp-hz = /bits/ 64 <133333333>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; }; ddrc: memory-controller@3d400000 { compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; reg = <0x3d400000 0x400000>; clock-names = "core", "pll", "alt", "apb"; clocks = <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_DRAM_PLL>, <&clk IMX8MM_CLK_DRAM_ALT>, <&clk IMX8MM_CLK_DRAM_APB>; };