# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU dt properties for QCM2290 target maintainers: - Loic Poulain description: | Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS and DPU are mentioned for QCM2290 target. properties: compatible: items: - const: qcom,qcm2290-mdss reg: maxItems: 1 reg-names: const: mdss power-domains: maxItems: 1 clocks: items: - description: Display AHB clock from gcc - description: Display AXI clock - description: Display core clock clock-names: items: - const: iface - const: bus - const: core interrupts: maxItems: 1 interrupt-controller: true "#address-cells": true "#size-cells": true "#interrupt-cells": const: 1 iommus: items: - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 ranges: true interconnects: items: - description: Interconnect path specifying the port ids for data bus interconnect-names: const: mdp0-mem resets: items: - description: MDSS_CORE reset patternProperties: "^display-controller@[0-9a-f]+$": type: object description: Node containing the properties of DPU. additionalProperties: false properties: compatible: items: - const: qcom,qcm2290-dpu reg: items: - description: Address offset and size for mdp register set - description: Address offset and size for vbif register set reg-names: items: - const: mdp - const: vbif clocks: items: - description: Display AXI clock from gcc - description: Display AHB clock from dispcc - description: Display core clock from dispcc - description: Display lut clock from dispcc - description: Display vsync clock from dispcc clock-names: items: - const: bus - const: iface - const: core - const: lut - const: vsync interrupts: maxItems: 1 power-domains: maxItems: 1 operating-points-v2: true opp-table: type: object ports: $ref: /schemas/graph.yaml#/properties/ports description: | Contains the list of output ports from DPU device. These ports connect to interfaces that are external to the DPU hardware, such as DSI. Each output port contains an endpoint that describes how it is connected to an external interface. properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: DPU_INTF1 (DSI1) required: - port@0 required: - compatible - reg - reg-names - clocks - interrupts - power-domains - operating-points-v2 - ports required: - compatible - reg - reg-names - power-domains - clocks - interrupts - interrupt-controller - iommus - ranges additionalProperties: false examples: - | #include #include #include #include #include mdss: mdss@5e00000 { #address-cells = <1>; #size-cells = <1>; compatible = "qcom,qcm2290-mdss"; reg = <0x05e00000 0x1000>; reg-names = "mdss"; power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "bus", "core"; interrupts = ; interrupt-controller; #interrupt-cells = <1>; interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>; interconnect-names = "mdp0-mem"; iommus = <&apps_smmu 0x420 0x2>, <&apps_smmu 0x421 0x0>; ranges; mdss_mdp: display-controller@5e01000 { compatible = "qcom,qcm2290-dpu"; reg = <0x05e01000 0x8f000>, <0x05eb0000 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "core", "lut", "vsync"; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmpd QCM2290_VDDCX>; interrupt-parent = <&mdss>; interrupts = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; }; }; }; }; ...