# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ultrarisc,dp1000-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UltraRISC DP1000 Clock Controller

maintainers:
  - Jia Wang <wangjia@ultrarisc.com>

description: |
  The UltraRISC DP1000 clock controller is driven from a single external
  oscillator input. It provides a system PLL with fractional multiplier
  and post-divider stages, several fixed-ratio derived clocks for
  the on-chip subsystem, Clock Configuration Register (CCR) divider
  outputs for GMAC and the UART, I2C, and SPI root clocks, and
  per-instance gate clocks for UART0-3, I2C0-3, and SPI0-1.

  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/ultrarisc,dp1000-clk.h

properties:
  compatible:
    const: ultrarisc,dp1000-clk

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    description:
      External oscillator input clock used as the parent of the PLLs.

  "#clock-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ultrarisc,dp1000-clk.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      clock-controller@11080000 {
        compatible = "ultrarisc,dp1000-clk";
        reg = <0x0 0x11080000 0x0 0x1000>;
        clocks = <&osc>;
        #clock-cells = <1>;
      };
    };