Binding for a type of quad channel digital frequency synthesizer found on
certain STMicroelectronics consumer electronics SoC devices.

This version contains a programmable PLL which can generate up to 216, 432
or 660MHz (from a 30MHz oscillator input) as the input to the digital
synthesizers.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be:
  "st,quadfs"
  "st,quadfs-d0"
  "st,quadfs-d2"
  "st,quadfs-d3"
  "st,quadfs-pll"


- #clock-cells : from common clock binding; shall be set to 1.

- reg : A Base address and length of the register set.

- clocks : from common clock binding

- clock-output-names : From common clock binding. The block has 4
                       clock outputs but not all of them in a specific instance
                       have to be used in the SoC. If a clock name is left as
                       an empty string then no clock will be created for the
                       output associated with that string index. If fewer than
                       4 strings are provided then no clocks will be created
                       for the remaining outputs.

Example:

	clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
		#clock-cells = <1>;
		compatible = "st,quadfs-pll";
		reg = <0x9103000 0x1000>;

		clocks = <&clk_sysin>;

		clock-output-names = "clk-s-c0-fs0-ch0",
				     "clk-s-c0-fs0-ch1",
				     "clk-s-c0-fs0-ch2",
				     "clk-s-c0-fs0-ch3";
	};