# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on GLYMUR

maintainers:
  - Taniya Das <taniya.das@oss.qualcomm.com>

description: |
  Qualcomm display clock control module which supports the clocks, resets and
  power domains for the MDSS instances on GLYMUR SoC.

  See also:
    include/dt-bindings/clock/qcom,dispcc-glymur.h

properties:
  compatible:
    enum:
      - qcom,glymur-dispcc

  clocks:
    items:
      - description: Board CXO clock
      - description: Board sleep clock
      - description: DisplayPort 0 link clock
      - description: DisplayPort 0 VCO div clock
      - description: DisplayPort 1 link clock
      - description: DisplayPort 1 VCO div clock
      - description: DisplayPort 2 link clock
      - description: DisplayPort 2 VCO div clock
      - description: DisplayPort 3 link clock
      - description: DisplayPort 3 VCO div clock
      - description: DSI 0 PLL byte clock
      - description: DSI 0 PLL DSI clock
      - description: DSI 1 PLL byte clock
      - description: DSI 1 PLL DSI clock
      - description: Standalone PHY 0 PLL link clock
      - description: Standalone PHY 0 VCO div clock
      - description: Standalone PHY 1 PLL link clock
      - description: Standalone PHY 1 VCO div clock

  power-domains:
    description:
      A phandle and PM domain specifier for the MMCX power domain.
    maxItems: 1

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.
    maxItems: 1

required:
  - compatible
  - clocks
  - power-domains
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    clock-controller@af00000 {
      compatible = "qcom,glymur-dispcc";
      reg = <0x0af00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>,
               <&mdss_dp_phy0 0>,
               <&mdss_dp_phy0 1>,
               <&mdss_dp_phy1 0>,
               <&mdss_dp_phy1 1>,
               <&mdss_dp_phy2 0>,
               <&mdss_dp_phy2 1>,
               <&mdss_dp_phy3 0>,
               <&mdss_dp_phy3 1>,
               <&mdss_dsi0_phy 0>,
               <&mdss_dsi0_phy 1>,
               <&mdss_dsi1_phy 0>,
               <&mdss_dsi1_phy 1>,
               <&mdss_phy0_link 0>,
               <&mdss_phy0_vco_div 0>,
               <&mdss_phy1_link 1>,
               <&mdss_phy1_vco_div 1>;
      power-domains = <&rpmhpd RPMHPD_MMCX>;
      required-opps = <&rpmhpd_opp_low_svs>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...